On Fri, Jul 13, 2012 at 12:35 PM, Tom Cooksey tom.cooksey@arm.com wrote:
My other thought is around atomicity. Could this be extended to (safely) allow for hardware devices which might want to access multiple buffers simultaneously? I think it probably can with some tweaks to the interface? An atomic function which does something like "give me all the fences for all these buffers and add this fence to each instead/as-well-as"?
fwiw, what I'm leaning towards right now is combining dma-fence w/ Maarten's idea of dma-buf-mgr (not sure if you saw his patches?). And let dmabufmgr handle the multi-buffer reservation stuff. And possibly the read vs write access, although this I'm not 100% sure on... the other option being the concept of read vs write (or exclusive/non-exclusive) fences.
In the current state, the fence is quite simple, and doesn't care *what* it is fencing, which seems advantageous when you get into trying to deal with combinations of devices sharing buffers, some of whom can do hw sync, and some who can't. So having a bit of partitioning from the code dealing w/ sequencing who can access the buffers when and for what purpose seems like it might not be a bad idea. Although I'm still working through the different alternatives.
BR, -R
Hey,
Op 13-07-12 20:52, Rob Clark schreef:
On Fri, Jul 13, 2012 at 12:35 PM, Tom Cooksey tom.cooksey@arm.com wrote:
My other thought is around atomicity. Could this be extended to (safely) allow for hardware devices which might want to access multiple buffers simultaneously? I think it probably can with some tweaks to the interface? An atomic function which does something like "give me all the fences for all these buffers and add this fence to each instead/as-well-as"?
fwiw, what I'm leaning towards right now is combining dma-fence w/ Maarten's idea of dma-buf-mgr (not sure if you saw his patches?). And let dmabufmgr handle the multi-buffer reservation stuff. And possibly the read vs write access, although this I'm not 100% sure on... the other option being the concept of read vs write (or exclusive/non-exclusive) fences.
Agreed, dmabufmgr is meant for reserving multiple buffers without deadlocks. The underlying mechanism for synchronization can be dma-fences, it wouldn't really change dmabufmgr much.
In the current state, the fence is quite simple, and doesn't care *what* it is fencing, which seems advantageous when you get into trying to deal with combinations of devices sharing buffers, some of whom can do hw sync, and some who can't. So having a bit of partitioning from the code dealing w/ sequencing who can access the buffers when and for what purpose seems like it might not be a bad idea. Although I'm still working through the different alternatives.
Yeah, I managed to get nouveau hooked up with generating irqs on completion today using an invalid command. It's also no longer a performance regression, so software syncing is no longer a problem for nouveau. i915 already generates irqs and r600 presumably too.
Monday I'll take a better look at your patch, end of day now. :)
~Maarten
On Fri, Jul 13, 2012 at 4:44 PM, Maarten Lankhorst maarten.lankhorst@canonical.com wrote:
Hey,
Op 13-07-12 20:52, Rob Clark schreef:
On Fri, Jul 13, 2012 at 12:35 PM, Tom Cooksey tom.cooksey@arm.com wrote:
My other thought is around atomicity. Could this be extended to (safely) allow for hardware devices which might want to access multiple buffers simultaneously? I think it probably can with some tweaks to the interface? An atomic function which does something like "give me all the fences for all these buffers and add this fence to each instead/as-well-as"?
fwiw, what I'm leaning towards right now is combining dma-fence w/ Maarten's idea of dma-buf-mgr (not sure if you saw his patches?). And let dmabufmgr handle the multi-buffer reservation stuff. And possibly the read vs write access, although this I'm not 100% sure on... the other option being the concept of read vs write (or exclusive/non-exclusive) fences.
Agreed, dmabufmgr is meant for reserving multiple buffers without deadlocks. The underlying mechanism for synchronization can be dma-fences, it wouldn't really change dmabufmgr much.
In the current state, the fence is quite simple, and doesn't care *what* it is fencing, which seems advantageous when you get into trying to deal with combinations of devices sharing buffers, some of whom can do hw sync, and some who can't. So having a bit of partitioning from the code dealing w/ sequencing who can access the buffers when and for what purpose seems like it might not be a bad idea. Although I'm still working through the different alternatives.
Yeah, I managed to get nouveau hooked up with generating irqs on completion today using an invalid command. It's also no longer a performance regression, so software syncing is no longer a problem for nouveau. i915 already generates irqs and r600 presumably too.
Monday I'll take a better look at your patch, end of day now. :)
let me send you a slightly updated version.. I fixed locally some locking fail in attach_fence() and get_fence() that I managed to introduce when converting from global spinlock to using the waitqueue's spinlock.
BR, -R
~Maarten
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