[PATCH 1/2] amdgpu: add bo handle to hash table when cpu mapping

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[PATCH] drm: keep connector status...

Chunming Zhou

4 Dec 2015 4 Dec '15

6:25 a.m.

Change-Id: Id79d98877c61510a1986d65befec6ce6713edae7 Signed-off-by: Chunming Zhou David1.Zhou@amd.com Reviewed-by: Jammy Zhou Jammy.Zhou@amd.com Reviewed-by: Christian König christian.koenig@amd.com --- amdgpu/amdgpu_bo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c index e47410c..5a0f4ac 100644 --- a/amdgpu/amdgpu_bo.c +++ b/amdgpu/amdgpu_bo.c @@ -462,7 +462,7 @@ int amdgpu_bo_cpu_map(amdgpu_bo_handle bo, void **cpu) pthread_mutex_unlock(&bo->cpu_access_mutex); return -errno; } - + amdgpu_add_handle_to_table(bo); bo->cpu_ptr = ptr; bo->cpu_map_count = 1; pthread_mutex_unlock(&bo->cpu_access_mutex);

-- 1.9.1

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Chunming Zhou

4 Dec 4 Dec

6:25 a.m.

New subject: [PATCH] drm/amdgpu: return bo itself if userptr is cpu addr of bo V2

V2: get original gem handle from gobj

Change-Id: I705eadfe03cd85c75bff252563d69f3c8a536868 Signed-off-by: Chunming Zhou David1.Zhou@amd.com Reviewed-by: Christian König christian.koenig@amd.com Reviewed-by: Jammy Zhou Jammy.Zhou@amd.com --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 59 +++++++++++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 1 + include/uapi/drm/amdgpu_drm.h | 12 +++++++ 4 files changed, 74 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 5b4f39c..1ffcbc1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1842,6 +1842,8 @@ int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); +int amdgpu_gem_find_bo_by_cpu_mapping_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp); int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index fc32fc0..e461357 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -216,6 +216,65 @@ error_unlock: return r; }

+static int amdgpu_gem_get_handle_from_object(struct drm_file *filp, + struct drm_gem_object *obj) +{ + int i; + struct drm_gem_object *tmp; + spin_lock(&filp->table_lock); + idr_for_each_entry(&filp->object_idr, tmp, i) { + if (obj == tmp) { + drm_gem_object_reference(obj); + spin_unlock(&filp->table_lock); + return i; + } + } + spin_unlock(&filp->table_lock); + return 0; +} + + +int amdgpu_gem_find_bo_by_cpu_mapping_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp) +{ + struct drm_amdgpu_gem_find_bo *args = data; + struct drm_gem_object *gobj; + struct amdgpu_bo *bo; + struct ttm_buffer_object *tbo; + struct vm_area_struct *vma; + uint32_t handle; + int r; + + if (offset_in_page(args->addr | args->size)) + return -EINVAL; + + down_read(&current->mm->mmap_sem); + vma = find_vma(current->mm, args->addr); + if (!vma || vma->vm_file != filp->filp || + (args->size > (vma->vm_end - args->addr))) { + args->handle = 0; + up_read(&current->mm->mmap_sem); + return -EINVAL; + } + tbo = vma->vm_private_data; + bo = container_of(tbo, struct amdgpu_bo, tbo); + amdgpu_bo_ref(bo); + gobj = &bo->gem_base; + handle = amdgpu_gem_get_handle_from_object(filp, gobj); + if (handle == 0) { + r = drm_gem_handle_create(filp, gobj, &handle); + if (r) { + DRM_ERROR("create gem handle failed\n"); + up_read(&current->mm->mmap_sem); + return r; + } + } + args->handle = handle; + args->offset = args->addr - vma->vm_start; + up_read(&current->mm->mmap_sem); + return 0; +} + int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index ff8f099..2c4c059 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -709,5 +709,6 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(AMDGPU_GEM_FIND_BO, amdgpu_gem_find_bo_by_cpu_mapping_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), }; int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms); diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 6dcaa79..c9c01d58 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -47,6 +47,7 @@ #define DRM_AMDGPU_GEM_OP 0x10 #define DRM_AMDGPU_GEM_USERPTR 0x11 #define DRM_AMDGPU_WAIT_FENCES 0x12 +#define DRM_AMDGPU_GEM_FIND_BO 0x13

#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) @@ -61,6 +62,7 @@ #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) +#define DRM_IOCTL_AMDGPU_GEM_FIND_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_FIND_BO, struct drm_amdgpu_gem_find_bo)

#define AMDGPU_GEM_DOMAIN_CPU 0x1 #define AMDGPU_GEM_DOMAIN_GTT 0x2 @@ -199,6 +201,16 @@ struct drm_amdgpu_gem_userptr { uint32_t handle; };

+struct drm_amdgpu_gem_find_bo { + uint64_t addr; + uint64_t size; + uint32_t flags; + /* Resulting GEM handle */ + uint32_t handle; + /* offset in bo */ + uint64_t offset; +}; + /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf

-- 1.9.1

Chunming Zhou

6:25 a.m.

New subject: [PATCH 2/2] amdgpu: add amdgpu_find_bo_by_cpu_mapping interface

userspace needs to know if the user memory is from BO or malloc.

Change-Id: Ie2dbc13f1c02bc0a996f64f9db83a21da63c1d70 Signed-off-by: Chunming Zhou David1.Zhou@amd.com Reviewed-by: Jammy Zhou Jammy.Zhou@amd.com Reviewed-by: Christian König christian.koenig@amd.com --- amdgpu/amdgpu.h | 24 ++++++++++++++++++++++++ amdgpu/amdgpu_bo.c | 37 +++++++++++++++++++++++++++++++++++++ include/drm/amdgpu_drm.h | 12 ++++++++++++ 3 files changed, 73 insertions(+)

diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h index baae113..4925056 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h @@ -672,6 +672,30 @@ int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev, amdgpu_bo_handle *buf_handle);

/** + * Validate if the user memory comes from BO + * + * \param dev - [in] Device handle. See #amdgpu_device_initialize() + * \param cpu - [in] CPU address of user allocated memory which we + * want to map to GPU address space (make GPU accessible) + * (This address must be correctly aligned). + * \param size - [in] Size of allocation (must be correctly aligned) + * \param buf_handle - [out] Buffer handle for the userptr memory + * if the user memory is not from BO, the buf_handle will be NULL. + * \param offset_in_bo - [out] offset in this BO for this user memory + * + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + * +*/ +int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev, + void *cpu, + uint64_t size, + amdgpu_bo_handle *buf_handle, + uint64_t *offset_in_bo); + + +/** * Free previosuly allocated memory * * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c index 5a0f4ac..82659a4 100644 --- a/amdgpu/amdgpu_bo.c +++ b/amdgpu/amdgpu_bo.c @@ -528,6 +528,43 @@ int amdgpu_bo_wait_for_idle(amdgpu_bo_handle bo, } }

+int amdgpu_find_bo_by_cpu_mapping(amdgpu_device_handle dev, + void *cpu, + uint64_t size, + amdgpu_bo_handle *buf_handle, + uint64_t *offset_in_bo) +{ + int r; + struct amdgpu_bo *bo; + struct drm_amdgpu_gem_find_bo args; + + args.addr = (uintptr_t)cpu; + args.size = size; + r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_FIND_BO, + &args, sizeof(args)); + if (r) + return r; + if (args.handle == 0) + return -EINVAL; + bo = util_hash_table_get(dev->bo_handles, + (void*)(uintptr_t)args.handle); + if (!bo) { + bo = calloc(1, sizeof(struct amdgpu_bo)); + if (!bo) + return -ENOMEM; + atomic_set(&bo->refcount, 1); + bo->dev = dev; + bo->alloc_size = size; + bo->handle = args.handle; + } else + atomic_inc(&bo->refcount); + + *buf_handle = bo; + *offset_in_bo = args.offset; + return r; +} + + int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev, void *cpu, uint64_t size, diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h index 050e7fe..e07904c 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h @@ -47,6 +47,7 @@ #define DRM_AMDGPU_GEM_OP 0x10 #define DRM_AMDGPU_GEM_USERPTR 0x11 #define DRM_AMDGPU_WAIT_FENCES 0x12 +#define DRM_AMDGPU_GEM_FIND_BO 0x13

#define AMDGPU_GEM_DOMAIN_CPU 0x1 #define AMDGPU_GEM_DOMAIN_GTT 0x2 @@ -201,6 +203,16 @@ struct drm_amdgpu_gem_userptr { uint32_t handle; };

-- 1.9.1

Christian König

8:32 a.m.

New subject: [PATCH 2/2] amdgpu: add amdgpu_find_bo_by_cpu_mapping interface

On 04.12.2015 07:25, Chunming Zhou wrote:

...

userspace needs to know if the user memory is from BO or malloc.

Change-Id: Ie2dbc13f1c02bc0a996f64f9db83a21da63c1d70 Signed-off-by: Chunming Zhou David1.Zhou@amd.com Reviewed-by: Jammy Zhou Jammy.Zhou@amd.com Reviewed-by: Christian König christian.koenig@amd.com

Looks like I was a bit too quick with my rb. After reading the code once more I've found we missed something important, see below.

...

args.addr = (uintptr_t)cpu;

args.size = size;

You need to grab the bo_table_mutex here, otherwise we could race with closing the handle and accessing bo_handles.

That could certainly cause a crash.

Regards, Christian.

...

r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_FIND_BO,
		&args, sizeof(args));
if (r)
return r;
if (args.handle == 0)
return -EINVAL;
bo = util_hash_table_get(dev->bo_handles,
		 (void*)(uintptr_t)args.handle);
if (!bo) {
bo = calloc(1, sizeof(struct amdgpu_bo));
if (!bo)
	return -ENOMEM;
atomic_set(&bo->refcount, 1);
bo->dev = dev;
bo->alloc_size = size;
bo->handle = args.handle;
} else
atomic_inc(&bo->refcount);
*buf_handle = bo;

*offset_in_bo = args.offset;

return r;
+}

int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev, void *cpu, uint64_t size,

diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h index 050e7fe..e07904c 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h @@ -47,6 +47,7 @@ #define DRM_AMDGPU_GEM_OP 0x10 #define DRM_AMDGPU_GEM_USERPTR 0x11 #define DRM_AMDGPU_WAIT_FENCES 0x12 +#define DRM_AMDGPU_GEM_FIND_BO 0x13

#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) @@ -61,6 +62,7 @@ #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) +#define DRM_IOCTL_AMDGPU_GEM_FIND_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_FIND_BO, struct drm_amdgpu_gem_find_bo)

#define AMDGPU_GEM_DOMAIN_CPU 0x1 #define AMDGPU_GEM_DOMAIN_GTT 0x2 @@ -201,6 +203,16 @@ struct drm_amdgpu_gem_userptr { uint32_t handle; };

+struct drm_amdgpu_gem_find_bo {
  uint64_t                addr;
  uint64_t                size;
  uint32_t                flags;
  /* Resulting GEM handle */
  uint32_t                handle;
  /* offset in bo */
  uint64_t                offset;
+};

/* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf

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Christian König
Chunming Zhou