On Renesas RZ/{G2L,V2L} platforms changing the lanes from 4 to 3 at lower frequencies causes display instability. On such platforms, it is better to avoid switching lanes from 4 to 3 as it needs different set of PLL parameter constraints to make the display stable with 3 lanes.

This patch adds an option to disable lane switching if 'adi,disable-lanes-override' property is present in DT.

Signed-off-by: Biju Das biju.das.jz@bp.renesas.com Reviewed-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com --- drivers/gpu/drm/bridge/adv7511/adv7511.h | 1 + drivers/gpu/drm/bridge/adv7511/adv7533.c | 5 ++++- 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511.h b/drivers/gpu/drm/bridge/adv7511/adv7511.h index 592ecfcf00ca..7505601f10fb 100644 --- a/drivers/gpu/drm/bridge/adv7511/adv7511.h +++ b/drivers/gpu/drm/bridge/adv7511/adv7511.h @@ -368,6 +368,7 @@ struct adv7511 { struct mipi_dsi_device *dsi; u8 num_dsi_lanes; bool use_timing_gen; + bool override_lanes;

enum adv7511_type type; struct platform_device *audio_pdev; diff --git a/drivers/gpu/drm/bridge/adv7511/adv7533.c b/drivers/gpu/drm/bridge/adv7511/adv7533.c index eb7579dec40a..7f6a8e95d70e 100644 --- a/drivers/gpu/drm/bridge/adv7511/adv7533.c +++ b/drivers/gpu/drm/bridge/adv7511/adv7533.c @@ -108,7 +108,7 @@ void adv7533_mode_set(struct adv7511 *adv, const struct drm_display_mode *mode) if (adv->num_dsi_lanes != 4) return;

- if (mode->clock > 80000) + if (!adv->override_lanes || mode->clock > 80000) lanes = 4; else lanes = 3; @@ -195,6 +195,9 @@ int adv7533_parse_dt(struct device_node *np, struct adv7511 *adv) adv->use_timing_gen = !of_property_read_bool(np, "adi,disable-timing-generator");

+ adv->override_lanes = !of_property_read_bool(np, + "adi,disable-lanes-override"); + /* TODO: Check if these need to be parsed by DT or not */ adv->rgb = true; adv->embedded_sync = false;

Hi Biju,

Thank you for the patch.

On Wed, Mar 09, 2022 at 03:11:08PM +0000, Biju Das wrote:

On Renesas RZ/{G2L,V2L} platforms changing the lanes from 4 to 3 at lower frequencies causes display instability. On such platforms, it is better to avoid switching lanes from 4 to 3 as it needs different set of PLL parameter constraints to make the display stable with 3 lanes.

Is this because the PLL calculation code doesn't work properly, or because the hardware can't support this ?

This patch introduces 'adi,disable-lanes-override' property to disable lane switching at lower frequencies.

Signed-off-by: Biju Das biju.das.jz@bp.renesas.com Reviewed-by: Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com

---

.../devicetree/bindings/display/bridge/adi,adv7533.yaml | 5 +++++ 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/bridge/adi,adv7533.yaml b/Documentation/devicetree/bindings/display/bridge/adi,adv7533.yaml index f36209137c8a..2dc378039d21 100644 --- a/Documentation/devicetree/bindings/display/bridge/adi,adv7533.yaml +++ b/Documentation/devicetree/bindings/display/bridge/adi,adv7533.yaml @@ -84,6 +84,11 @@ properties: timings for HDMI output. type: boolean

• adi,disable-lanes-override:
• description:

•  Disables the overriding lanes at lower frequencies.
  

• type: boolean
• adi,dsi-lanes: description: Number of DSI data lanes connected to the DSI host. $ref: /schemas/types.yaml#/definitions/uint32