Hi Alexander,

On Thu, 2018-12-20 at 11:06 +0300, Alexander Shiyan wrote:

The CSI0/CSI1 registers offset is at +0xe030000/+0xe038000 relative to the control module registers on IPUv3EX. This patch fixes wrong values for i.MX51 CSI0/CSI1.

Signed-off-by: Alexander Shiyan shc_work@mail.ru

drivers/gpu/ipu-v3/ipu-common.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c index 474b00e19697..5b7cdbfe062f 100644 --- a/drivers/gpu/ipu-v3/ipu-common.c +++ b/drivers/gpu/ipu-v3/ipu-common.c @@ -898,8 +898,8 @@ static struct ipu_devtype ipu_type_imx51 = { .cpmem_ofs = 0x1f000000, .srm_ofs = 0x1f040000, .tpm_ofs = 0x1f060000,

• .csi0_ofs = 0x1f030000,
• .csi1_ofs = 0x1f038000,

• .csi0_ofs = 0x1e030000,
• .csi1_ofs = 0x1e038000,

Thank you for the patch. This fix matches the documentation in the MCIMX51RM, table 42-1 "IPUv3EX internal memory map". Applied to imx-drm/fixes.

.ic_ofs = 0x1e020000, .disp0_ofs = 0x1e040000, .disp1_ofs = 0x1e048000,

regards Philipp