Hi Marek,

Thanks for your patch! Perhaps something to improve:

[auto build test WARNING on drm-intel/for-linux-next] [also build test WARNING on drm-exynos/exynos-drm-next next-20220225] [cannot apply to drm/drm-next drm-tip/drm-tip tegra-drm/drm/tegra/for-next v5.17-rc6] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch]

url: https://github.com/0day-ci/linux/commits/Marek-Vasut/dt-bindings-mxsfb-Add-c... base: git://anongit.freedesktop.org/drm-intel for-linux-next config: mips-randconfig-c004-20220227 (https://download.01.org/0day-ci/archive/20220301/202203010150.L57Eax3W-lkp@i...) compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project d271fc04d5b97b12e6b797c6067d3c96a8d7470e) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install mips cross compiling tool for clang build # apt-get install binutils-mips-linux-gnu # https://github.com/0day-ci/linux/commit/d6832d6fb879aabce18d9b451ed1ead1da38... git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Marek-Vasut/dt-bindings-mxsfb-Add-compatible-for-i-MX8MP/20220228-084809 git checkout d6832d6fb879aabce18d9b451ed1ead1da38c333 # save the config file to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=mips clang-analyzer

If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot yujie.liu@intel.com

clang-analyzer warnings: (new ones prefixed by >>)

...

drivers/gpu/drm/mxsfb/mxsfb_kms.c:258:8: warning: The left expression of the compound assignment is an uninitialized value. The computed value will also be garbage [clang-analyzer-core.uninitialized.Assign]

ctrl |= CTRL_INV_HS; ^

vim +258 drivers/gpu/drm/mxsfb/mxsfb_kms.c

56c727244a47cf Marek Vasut 2022-02-28 251 d6832d6fb879aa Marek Vasut 2022-02-28 252 static void mxsfb_v8_set_mode(struct mxsfb_drm_private *mxsfb, u32 bus_flags) d6832d6fb879aa Marek Vasut 2022-02-28 253 { d6832d6fb879aa Marek Vasut 2022-02-28 254 struct drm_display_mode *m = &mxsfb->crtc.state->adjusted_mode; d6832d6fb879aa Marek Vasut 2022-02-28 @255 u32 ctrl; d6832d6fb879aa Marek Vasut 2022-02-28 256 d6832d6fb879aa Marek Vasut 2022-02-28 257 if (m->flags & DRM_MODE_FLAG_PHSYNC) d6832d6fb879aa Marek Vasut 2022-02-28 @258 ctrl |= CTRL_INV_HS; d6832d6fb879aa Marek Vasut 2022-02-28 259 if (m->flags & DRM_MODE_FLAG_PVSYNC) d6832d6fb879aa Marek Vasut 2022-02-28 260 ctrl |= CTRL_INV_VS; d6832d6fb879aa Marek Vasut 2022-02-28 261 /* Make sure Data Enable is high active by default */ d6832d6fb879aa Marek Vasut 2022-02-28 262 if (!(bus_flags & DRM_BUS_FLAG_DE_LOW)) d6832d6fb879aa Marek Vasut 2022-02-28 263 ctrl |= CTRL_INV_DE; d6832d6fb879aa Marek Vasut 2022-02-28 264 if (bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) d6832d6fb879aa Marek Vasut 2022-02-28 265 ctrl |= CTRL_INV_PXCK; d6832d6fb879aa Marek Vasut 2022-02-28 266 d6832d6fb879aa Marek Vasut 2022-02-28 267 writel(ctrl, mxsfb->base + LCDC_CTRL); d6832d6fb879aa Marek Vasut 2022-02-28 268 d6832d6fb879aa Marek Vasut 2022-02-28 269 writel(DISP_SIZE_DELTA_Y(m->crtc_vdisplay) | d6832d6fb879aa Marek Vasut 2022-02-28 270 DISP_SIZE_DELTA_X(m->crtc_hdisplay), d6832d6fb879aa Marek Vasut 2022-02-28 271 mxsfb->base + LCDC_V8_DISP_SIZE); d6832d6fb879aa Marek Vasut 2022-02-28 272 d6832d6fb879aa Marek Vasut 2022-02-28 273 writel(HSYN_PARA_BP_H(m->htotal - m->hsync_end) | d6832d6fb879aa Marek Vasut 2022-02-28 274 HSYN_PARA_FP_H(m->hsync_start - m->hdisplay), d6832d6fb879aa Marek Vasut 2022-02-28 275 mxsfb->base + LCDC_V8_HSYN_PARA); d6832d6fb879aa Marek Vasut 2022-02-28 276 d6832d6fb879aa Marek Vasut 2022-02-28 277 writel(VSYN_PARA_BP_V(m->vtotal - m->vsync_end) | d6832d6fb879aa Marek Vasut 2022-02-28 278 VSYN_PARA_FP_V(m->vsync_start - m->vdisplay), d6832d6fb879aa Marek Vasut 2022-02-28 279 mxsfb->base + LCDC_V8_VSYN_PARA); d6832d6fb879aa Marek Vasut 2022-02-28 280 d6832d6fb879aa Marek Vasut 2022-02-28 281 writel(VSYN_HSYN_WIDTH_PW_V(m->vsync_end - m->vsync_start) | d6832d6fb879aa Marek Vasut 2022-02-28 282 VSYN_HSYN_WIDTH_PW_H(m->hsync_end - m->hsync_start), d6832d6fb879aa Marek Vasut 2022-02-28 283 mxsfb->base + LCDC_V8_VSYN_HSYN_WIDTH); d6832d6fb879aa Marek Vasut 2022-02-28 284 d6832d6fb879aa Marek Vasut 2022-02-28 285 writel(CTRLDESCL0_1_HEIGHT(m->crtc_vdisplay) | d6832d6fb879aa Marek Vasut 2022-02-28 286 CTRLDESCL0_1_WIDTH(m->crtc_hdisplay), d6832d6fb879aa Marek Vasut 2022-02-28 287 mxsfb->base + LCDC_V8_CTRLDESCL0_1); d6832d6fb879aa Marek Vasut 2022-02-28 288 d6832d6fb879aa Marek Vasut 2022-02-28 289 writel(CTRLDESCL0_3_PITCH(mxsfb->crtc.primary->state->fb->pitches[0]), d6832d6fb879aa Marek Vasut 2022-02-28 290 mxsfb->base + LCDC_V8_CTRLDESCL0_3); d6832d6fb879aa Marek Vasut 2022-02-28 291 } d6832d6fb879aa Marek Vasut 2022-02-28 292

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