This series adds some of the host controller changes needed for SDM845.\ The DT patches in the series do some minor clean ups and add missing bindings for 14nm DSI PHY (8x96) and new bindings for 10nm PHY.
Archit Taneja (7): drm/msm/dsi: Use msm_clk_get in dsi_get_config drm/msm/dsi: Add SDM845 in dsi_cfg drm/msm/dsi: Add byte_intf_clk dt-bindings: display: msm/dsi: Remove unused properties dt-bindings: display: msm/dsi: Fix the PHY regulator supply props dt-bindings: display: msm/dsi: Add compatible for 14nm DSI PHY dt-bindings: display: msm/dsi: Add updates for SDM845
.../devicetree/bindings/display/msm/dsi.txt | 26 +++++++++++---- drivers/gpu/drm/msm/dsi/dsi_cfg.c | 19 +++++++++++ drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 + drivers/gpu/drm/msm/dsi/dsi_host.c | 38 +++++++++++++++++++--- 4 files changed, 74 insertions(+), 10 deletions(-)
We try to get the interface clock in dsi_get_config early during DSI's component bind. Try getting both the "iface" and "iface_clk" clock name variants so that we are compatible with both new and legacy DT.
Signed-off-by: Archit Taneja architt@codeaurora.org --- drivers/gpu/drm/msm/dsi/dsi_host.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 0f7324a686ca..7611fe014036 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -214,7 +214,7 @@ static const struct msm_dsi_cfg_handler *dsi_get_config( goto exit; }
- ahb_clk = clk_get(dev, "iface_clk"); + ahb_clk = msm_clk_get(msm_host->pdev, "iface"); if (IS_ERR(ahb_clk)) { pr_err("%s: cannot get interface clock\n", __func__); goto put_gdsc; @@ -225,7 +225,7 @@ static const struct msm_dsi_cfg_handler *dsi_get_config( ret = regulator_enable(gdsc_reg); if (ret) { pr_err("%s: unable to enable gdsc\n", __func__); - goto put_clk; + goto put_gdsc; }
ret = clk_prepare_enable(ahb_clk); @@ -249,8 +249,6 @@ static const struct msm_dsi_cfg_handler *dsi_get_config( disable_gdsc: regulator_disable(gdsc_reg); pm_runtime_put_sync(dev); -put_clk: - clk_put(ahb_clk); put_gdsc: regulator_put(gdsc_reg); exit:
SDM845 contains 2 DSI6G v2.2.1 host controllers. Add them in dsi_cfg.
Cc: Jordan Crouse jcrouse@codeaurora.org Signed-off-by: Archit Taneja architt@codeaurora.org --- drivers/gpu/drm/msm/dsi/dsi_cfg.c | 19 +++++++++++++++++++ drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 + 2 files changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c index 65c1dfbbe019..0327bb54b01b 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c @@ -118,6 +118,24 @@ static const struct msm_dsi_config msm8996_dsi_cfg = { .num_dsi = 2, };
+static const char * const dsi_sdm845_bus_clk_names[] = { + "iface", "bus", +}; + +static const struct msm_dsi_config sdm845_dsi_cfg = { + .io_offset = DSI_6G_REG_SHIFT, + .reg_cfg = { + .num = 1, + .regs = { + {"vdda", 21800, 4 }, /* 1.2 V */ + }, + }, + .bus_clk_names = dsi_sdm845_bus_clk_names, + .num_bus_clks = ARRAY_SIZE(dsi_sdm845_bus_clk_names), + .io_start = { 0xae94000, 0xae96000 }, + .num_dsi = 2, +}; + static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = { {MSM_DSI_VER_MAJOR_V2, MSM_DSI_V2_VER_MINOR_8064, &apq8064_dsi_cfg}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_0, @@ -131,6 +149,7 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = { {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_3, &msm8994_dsi_cfg}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_3_1, &msm8916_dsi_cfg}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_4_1, &msm8996_dsi_cfg}, + {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_2_1, &sdm845_dsi_cfg}, };
const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor) diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h index 00a5da2663c6..9cfdcf1c95d5 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h @@ -25,6 +25,7 @@ #define MSM_DSI_6G_VER_MINOR_V1_3 0x10030000 #define MSM_DSI_6G_VER_MINOR_V1_3_1 0x10030001 #define MSM_DSI_6G_VER_MINOR_V1_4_1 0x10040001 +#define MSM_DSI_6G_VER_MINOR_V2_2_1 0x20020001
#define MSM_DSI_V2_VER_MINOR_8064 0x0
DSI6G v2.0+ blocks have a new clock input to them called byte_intf_clk. It's rate is to be set as byte_clk / 2.
Within the clock controller (CC) subsystem, this clock is a child/descendant of the byte_clk.
Set it up as an optional clock in the DSI host driver. Make sure that we enable/set its rate only after we configure byte_clk. This is required for the ancestor clocks in the CC to be configured correctly.
Signed-off-by: Archit Taneja architt@codeaurora.org --- drivers/gpu/drm/msm/dsi/dsi_host.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 7611fe014036..f675975c2655 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -115,6 +115,7 @@ struct msm_dsi_host { struct clk *pixel_clk; struct clk *byte_clk_src; struct clk *pixel_clk_src; + struct clk *byte_intf_clk;
u32 byte_clk_rate; u32 esc_clk_rate; @@ -377,6 +378,14 @@ static int dsi_clk_init(struct msm_dsi_host *msm_host) goto exit; }
+ msm_host->byte_intf_clk = msm_clk_get(pdev, "byte_intf"); + if (IS_ERR(msm_host->byte_intf_clk)) { + ret = PTR_ERR(msm_host->byte_intf_clk); + pr_debug("%s: can't find byte_intf clock. ret=%d\n", + __func__, ret); + msm_host->byte_intf_clk = NULL; + } + msm_host->byte_clk_src = clk_get_parent(msm_host->byte_clk); if (!msm_host->byte_clk_src) { ret = -ENODEV; @@ -502,6 +511,16 @@ static int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) goto error; }
+ if (msm_host->byte_intf_clk) { + ret = clk_set_rate(msm_host->byte_intf_clk, + msm_host->byte_clk_rate / 2); + if (ret) { + pr_err("%s: Failed to set rate byte intf clk, %d\n", + __func__, ret); + goto error; + } + } + ret = clk_prepare_enable(msm_host->esc_clk); if (ret) { pr_err("%s: Failed to enable dsi esc clk\n", __func__); @@ -520,8 +539,19 @@ static int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) goto pixel_clk_err; }
+ if (msm_host->byte_intf_clk) { + ret = clk_prepare_enable(msm_host->byte_intf_clk); + if (ret) { + pr_err("%s: Failed to enable byte intf clk\n", + __func__); + goto byte_intf_clk_err; + } + } + return 0;
+byte_intf_clk_err: + clk_disable_unprepare(msm_host->pixel_clk); pixel_clk_err: clk_disable_unprepare(msm_host->byte_clk); byte_clk_err: @@ -615,6 +645,8 @@ static void dsi_link_clk_disable(struct msm_dsi_host *msm_host) if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) { clk_disable_unprepare(msm_host->esc_clk); clk_disable_unprepare(msm_host->pixel_clk); + if (msm_host->byte_intf_clk) + clk_disable_unprepare(msm_host->byte_intf_clk); clk_disable_unprepare(msm_host->byte_clk); } else { clk_disable_unprepare(msm_host->pixel_clk);
"qcom,dsi-host-index" and "qcom,dsi-phy-index" DT props aren't acceptable and have never been used in any DT files. Remove them.
Cc: Rob Herring robh@kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Archit Taneja architt@codeaurora.org --- Documentation/devicetree/bindings/display/msm/dsi.txt | 4 ---- 1 file changed, 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt index a6671bd2c85a..457c688736be 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi.txt +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt @@ -7,8 +7,6 @@ Required properties: - reg: Physical base address and length of the registers of controller - reg-names: The names of register regions. The following regions are required: * "dsi_ctrl" -- qcom,dsi-host-index: The ID of DSI controller hardware instance. This should - be 0 or 1, since we have 2 DSI controllers at most for now. - interrupts: The interrupt signal from the DSI block. - power-domains: Should be <&mmcc MDSS_GDSC>. - clocks: Phandles to device clocks. @@ -96,8 +94,6 @@ Required properties: * "dsi_phy_regulator" - clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating 2 clocks: A byte clock (index 0), and a pixel clock (index 1). -- qcom,dsi-phy-index: The ID of DSI PHY hardware instance. This should - be 0 or 1, since we have 2 DSI PHYs at most for now. - power-domains: Should be <&mmcc MDSS_GDSC>. - clocks: Phandles to device clocks. See [1] for details on clock bindings. - clock-names: the following clocks are required:
On Wed, Jan 17, 2018 at 03:04:45PM +0530, Archit Taneja wrote:
"qcom,dsi-host-index" and "qcom,dsi-phy-index" DT props aren't acceptable and have never been used in any DT files. Remove them.
Cc: Rob Herring robh@kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Archit Taneja architt@codeaurora.org
Documentation/devicetree/bindings/display/msm/dsi.txt | 4 ---- 1 file changed, 4 deletions(-)
Reviewed-by: Rob Herring robh@kernel.org
The PHY regulator supply names vary across different PHY versions. Mention explicitly which PHYs require which supplies.
Cc: Rob Herring robh@kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Archit Taneja architt@codeaurora.org --- Documentation/devicetree/bindings/display/msm/dsi.txt | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt index 457c688736be..9c3ad6bbb9f0 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi.txt +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt @@ -98,7 +98,11 @@ Required properties: - clocks: Phandles to device clocks. See [1] for details on clock bindings. - clock-names: the following clocks are required: * "iface" + For 28nm HPM/LP, 28nm 8960 PHYs: - vddio-supply: phandle to vdd-io regulator device node + For 20nm PHY: +- vddio-supply: phandle to vdd-io regulator device node +- vcca-supply: phandle to vcca regulator device node
Optional properties: - qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
On Wed, Jan 17, 2018 at 03:04:46PM +0530, Archit Taneja wrote:
The PHY regulator supply names vary across different PHY versions. Mention explicitly which PHYs require which supplies.
Cc: Rob Herring robh@kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Archit Taneja architt@codeaurora.org
Documentation/devicetree/bindings/display/msm/dsi.txt | 4 ++++ 1 file changed, 4 insertions(+)
Reviewed-by: Rob Herring robh@kernel.org
Add the compatible string for 14nm DSI PHY (used in MSM8996/APQ8096).
From 14nm PHY onwards, the "dsi_phy_regulator" reg-name is not required,
but "dsi_phy_lane" reg-name is. Update the doc to specify the reg-names each PHY revision needs.
Cc: Rob Herring robh@kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Archit Taneja architt@codeaurora.org --- Documentation/devicetree/bindings/display/msm/dsi.txt | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt index 9c3ad6bbb9f0..26a1796b7145 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi.txt +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt @@ -86,12 +86,19 @@ Required properties: * "qcom,dsi-phy-28nm-lp" * "qcom,dsi-phy-20nm" * "qcom,dsi-phy-28nm-8960" -- reg: Physical base address and length of the registers of PLL, PHY and PHY - regulator + * "qcom,dsi-phy-14nm" +- reg: Physical base address and length of the registers of PLL, PHY. Some + revisions require the PHY regulator base address, whereas others require the + PHY lane base address. See below for each PHY revision. - reg-names: The names of register regions. The following regions are required: + For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY: * "dsi_pll" * "dsi_phy" * "dsi_phy_regulator" + For DSI 14nm PHY: + * "dsi_pll" + * "dsi_phy" + * "dsi_phy_lane" - clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating 2 clocks: A byte clock (index 0), and a pixel clock (index 1). - power-domains: Should be <&mmcc MDSS_GDSC>. @@ -102,6 +109,8 @@ Required properties: - vddio-supply: phandle to vdd-io regulator device node For 20nm PHY: - vddio-supply: phandle to vdd-io regulator device node +- vcca-supply: phandle to vcca regulator device node + For 14nm PHY: - vcca-supply: phandle to vcca regulator device node
Optional properties:
On Wed, Jan 17, 2018 at 03:04:47PM +0530, Archit Taneja wrote:
Add the compatible string for 14nm DSI PHY (used in MSM8996/APQ8096). From 14nm PHY onwards, the "dsi_phy_regulator" reg-name is not required, but "dsi_phy_lane" reg-name is. Update the doc to specify the reg-names each PHY revision needs.
Cc: Rob Herring robh@kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Archit Taneja architt@codeaurora.org
Documentation/devicetree/bindings/display/msm/dsi.txt | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt index 9c3ad6bbb9f0..26a1796b7145 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi.txt +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt @@ -86,12 +86,19 @@ Required properties:
- "qcom,dsi-phy-28nm-lp"
- "qcom,dsi-phy-20nm"
- "qcom,dsi-phy-28nm-8960"
-- reg: Physical base address and length of the registers of PLL, PHY and PHY
- regulator
- "qcom,dsi-phy-14nm"
+- reg: Physical base address and length of the registers of PLL, PHY. Some
- revisions require the PHY regulator base address, whereas others require the
- PHY lane base address. See below for each PHY revision.
- reg-names: The names of register regions. The following regions are required:
- For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY:
- "dsi_pll"
- "dsi_phy"
- "dsi_phy_regulator"
- For DSI 14nm PHY:
- "dsi_pll"
- "dsi_phy"
- "dsi_phy_lane"
- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating 2 clocks: A byte clock (index 0), and a pixel clock (index 1).
- power-domains: Should be <&mmcc MDSS_GDSC>.
@@ -102,6 +109,8 @@ Required properties:
- vddio-supply: phandle to vdd-io regulator device node For 20nm PHY:
- vddio-supply: phandle to vdd-io regulator device node
+- vcca-supply: phandle to vcca regulator device node
Did you mean to add this?
- For 14nm PHY:
- vcca-supply: phandle to vcca regulator device node
Optional properties:
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation
On 01/29/2018 10:45 PM, Rob Herring wrote:
On Wed, Jan 17, 2018 at 03:04:47PM +0530, Archit Taneja wrote:
Add the compatible string for 14nm DSI PHY (used in MSM8996/APQ8096). From 14nm PHY onwards, the "dsi_phy_regulator" reg-name is not required, but "dsi_phy_lane" reg-name is. Update the doc to specify the reg-names each PHY revision needs.
Cc: Rob Herring robh@kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Archit Taneja architt@codeaurora.org
Documentation/devicetree/bindings/display/msm/dsi.txt | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt index 9c3ad6bbb9f0..26a1796b7145 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi.txt +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt @@ -86,12 +86,19 @@ Required properties: * "qcom,dsi-phy-28nm-lp" * "qcom,dsi-phy-20nm" * "qcom,dsi-phy-28nm-8960" -- reg: Physical base address and length of the registers of PLL, PHY and PHY
- regulator
- "qcom,dsi-phy-14nm"
+- reg: Physical base address and length of the registers of PLL, PHY. Some
- revisions require the PHY regulator base address, whereas others require the
- PHY lane base address. See below for each PHY revision.
- reg-names: The names of register regions. The following regions are required:
- For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY:
- "dsi_pll"
- "dsi_phy"
- "dsi_phy_regulator"
- For DSI 14nm PHY:
- "dsi_pll"
- "dsi_phy"
- "dsi_phy_lane"
2 clocks: A byte clock (index 0), and a pixel clock (index 1).
- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating
- power-domains: Should be <&mmcc MDSS_GDSC>.
@@ -102,6 +109,8 @@ Required properties:
- vddio-supply: phandle to vdd-io regulator device node For 20nm PHY:
- vddio-supply: phandle to vdd-io regulator device node
+- vcca-supply: phandle to vcca regulator device node
Did you mean to add this?
Yes, I didn't intend it to be a part of this patch, but this supply is indeed needed for the 20nm PHY. I'll move this to a separate patch.
Thanks, Archit
For 14nm PHY:
- vcca-supply: phandle to vcca regulator device node
Optional properties:
-- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation
On Wed, Jan 31, 2018 at 1:40 AM, Archit Taneja architt@codeaurora.org wrote:
On 01/29/2018 10:45 PM, Rob Herring wrote:
On Wed, Jan 17, 2018 at 03:04:47PM +0530, Archit Taneja wrote:
Add the compatible string for 14nm DSI PHY (used in MSM8996/APQ8096). From 14nm PHY onwards, the "dsi_phy_regulator" reg-name is not required, but "dsi_phy_lane" reg-name is. Update the doc to specify the reg-names each PHY revision needs.
Cc: Rob Herring robh@kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Archit Taneja architt@codeaurora.org
Documentation/devicetree/bindings/display/msm/dsi.txt | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt index 9c3ad6bbb9f0..26a1796b7145 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi.txt +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt @@ -86,12 +86,19 @@ Required properties: * "qcom,dsi-phy-28nm-lp" * "qcom,dsi-phy-20nm" * "qcom,dsi-phy-28nm-8960" -- reg: Physical base address and length of the registers of PLL, PHY and PHY
- regulator
- "qcom,dsi-phy-14nm"
+- reg: Physical base address and length of the registers of PLL, PHY. Some
- revisions require the PHY regulator base address, whereas others
require the
- PHY lane base address. See below for each PHY revision.
- reg-names: The names of register regions. The following regions are
required:
- For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY:
- "dsi_pll"
- "dsi_phy"
- "dsi_phy_regulator"
- For DSI 14nm PHY:
- "dsi_pll"
- "dsi_phy"
- "dsi_phy_lane"
- clock-cells: Must be 1. The DSI PHY block acts as a clock provider,
creating 2 clocks: A byte clock (index 0), and a pixel clock (index 1).
- power-domains: Should be <&mmcc MDSS_GDSC>.
@@ -102,6 +109,8 @@ Required properties:
- vddio-supply: phandle to vdd-io regulator device node For 20nm PHY:
- vddio-supply: phandle to vdd-io regulator device node
+- vcca-supply: phandle to vcca regulator device node
Did you mean to add this?
Yes, I didn't intend it to be a part of this patch, but this supply is indeed needed for the 20nm PHY. I'll move this to a separate patch.
actually, this looks correct, just formatted counter-intuitively by git-format-patch..
vcca-supply for 20nm was introduced by "dt-bindings: display: msm/dsi: Fix the PHY regulator supply props", but when 14nm phy is added in this patch, it shows the addition of same line beneath 14nm PHY as an addition above the line.
So I don't think it needs to be split up.
BR, -R
Thanks, Archit
- For 14nm PHY:
Optional properties:
- vcca-supply: phandle to vcca regulator device node
-- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation
-- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
On 01/31/2018 09:50 PM, Rob Clark wrote:
On Wed, Jan 31, 2018 at 1:40 AM, Archit Taneja architt@codeaurora.org wrote:
On 01/29/2018 10:45 PM, Rob Herring wrote:
On Wed, Jan 17, 2018 at 03:04:47PM +0530, Archit Taneja wrote:
Add the compatible string for 14nm DSI PHY (used in MSM8996/APQ8096). From 14nm PHY onwards, the "dsi_phy_regulator" reg-name is not required, but "dsi_phy_lane" reg-name is. Update the doc to specify the reg-names each PHY revision needs.
Cc: Rob Herring robh@kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Archit Taneja architt@codeaurora.org
Documentation/devicetree/bindings/display/msm/dsi.txt | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt index 9c3ad6bbb9f0..26a1796b7145 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi.txt +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt @@ -86,12 +86,19 @@ Required properties: * "qcom,dsi-phy-28nm-lp" * "qcom,dsi-phy-20nm" * "qcom,dsi-phy-28nm-8960" -- reg: Physical base address and length of the registers of PLL, PHY and PHY
- regulator
- "qcom,dsi-phy-14nm"
+- reg: Physical base address and length of the registers of PLL, PHY. Some
- revisions require the PHY regulator base address, whereas others
require the
- PHY lane base address. See below for each PHY revision.
- reg-names: The names of register regions. The following regions are
required:
- For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY:
- "dsi_pll"
- "dsi_phy"
- "dsi_phy_regulator"
- For DSI 14nm PHY:
- "dsi_pll"
- "dsi_phy"
- "dsi_phy_lane"
- clock-cells: Must be 1. The DSI PHY block acts as a clock provider,
creating 2 clocks: A byte clock (index 0), and a pixel clock (index 1).
- power-domains: Should be <&mmcc MDSS_GDSC>.
@@ -102,6 +109,8 @@ Required properties:
- vddio-supply: phandle to vdd-io regulator device node For 20nm PHY:
- vddio-supply: phandle to vdd-io regulator device node
+- vcca-supply: phandle to vcca regulator device node
Did you mean to add this?
Yes, I didn't intend it to be a part of this patch, but this supply is indeed needed for the 20nm PHY. I'll move this to a separate patch.
actually, this looks correct, just formatted counter-intuitively by git-format-patch..
vcca-supply for 20nm was introduced by "dt-bindings: display: msm/dsi: Fix the PHY regulator supply props", but when 14nm phy is added in this patch, it shows the addition of same line beneath 14nm PHY as an addition above the line.
So I don't think it needs to be split up.
Oh yeah, you're right. I guess this is okay as is, then.
Thanks, Archit
BR, -R
Thanks, Archit
- For 14nm PHY:
- vcca-supply: phandle to vcca regulator device node Optional properties:
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On Wed, Jan 31, 2018 at 11:29 PM, Archit Taneja architt@codeaurora.org wrote:
On 01/31/2018 09:50 PM, Rob Clark wrote:
On Wed, Jan 31, 2018 at 1:40 AM, Archit Taneja architt@codeaurora.org wrote:
On 01/29/2018 10:45 PM, Rob Herring wrote:
On Wed, Jan 17, 2018 at 03:04:47PM +0530, Archit Taneja wrote:
Add the compatible string for 14nm DSI PHY (used in MSM8996/APQ8096). From 14nm PHY onwards, the "dsi_phy_regulator" reg-name is not required, but "dsi_phy_lane" reg-name is. Update the doc to specify the reg-names each PHY revision needs.
Cc: Rob Herring robh@kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Archit Taneja architt@codeaurora.org
Documentation/devicetree/bindings/display/msm/dsi.txt | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt index 9c3ad6bbb9f0..26a1796b7145 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi.txt +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt @@ -86,12 +86,19 @@ Required properties: * "qcom,dsi-phy-28nm-lp" * "qcom,dsi-phy-20nm" * "qcom,dsi-phy-28nm-8960" -- reg: Physical base address and length of the registers of PLL, PHY and PHY
- regulator
- "qcom,dsi-phy-14nm"
+- reg: Physical base address and length of the registers of PLL, PHY. Some
- revisions require the PHY regulator base address, whereas others
require the
- PHY lane base address. See below for each PHY revision.
- reg-names: The names of register regions. The following regions
are required:
- For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY:
- "dsi_pll"
- "dsi_phy"
- "dsi_phy_regulator"
- For DSI 14nm PHY:
- "dsi_pll"
- "dsi_phy"
- "dsi_phy_lane"
- clock-cells: Must be 1. The DSI PHY block acts as a clock
provider, creating 2 clocks: A byte clock (index 0), and a pixel clock (index 1).
- power-domains: Should be <&mmcc MDSS_GDSC>.
@@ -102,6 +109,8 @@ Required properties:
- vddio-supply: phandle to vdd-io regulator device node For 20nm PHY:
- vddio-supply: phandle to vdd-io regulator device node
+- vcca-supply: phandle to vcca regulator device node
Did you mean to add this?
Yes, I didn't intend it to be a part of this patch, but this supply is indeed needed for the 20nm PHY. I'll move this to a separate patch.
actually, this looks correct, just formatted counter-intuitively by git-format-patch..
vcca-supply for 20nm was introduced by "dt-bindings: display: msm/dsi: Fix the PHY regulator supply props", but when 14nm phy is added in this patch, it shows the addition of same line beneath 14nm PHY as an addition above the line.
So I don't think it needs to be split up.
Oh yeah, you're right. I guess this is okay as is, then.
Doh!
Reviewed-by: Rob Herring robh@kernel.org
SDM845 uses a newer revision (v2.0+) of the 6G DSI controller. This revision has another clock input at the block boundary called the byte interface clock. Specify this new clock in the binding.
A 10nm DSI PHY is used along with the controller. Add a compatible string for it and specify its base address/regulator supply needs.
Cc: Rob Herring robh@kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Archit Taneja architt@codeaurora.org --- Documentation/devicetree/bindings/display/msm/dsi.txt | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt index 26a1796b7145..518e9cdf0d4b 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi.txt +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt @@ -20,6 +20,8 @@ Required properties: * "core" For DSIv2, we need an additional clock: * "src" + For DSI6G v2.0 onwards, we need also need the clock: + * "byte_intf" - assigned-clocks: Parents of "byte" and "pixel" for the given platform. - assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block. See [1] for details on clock bindings. @@ -87,6 +89,7 @@ Required properties: * "qcom,dsi-phy-20nm" * "qcom,dsi-phy-28nm-8960" * "qcom,dsi-phy-14nm" + * "qcom,dsi-phy-10nm" - reg: Physical base address and length of the registers of PLL, PHY. Some revisions require the PHY regulator base address, whereas others require the PHY lane base address. See below for each PHY revision. @@ -95,7 +98,7 @@ Required properties: * "dsi_pll" * "dsi_phy" * "dsi_phy_regulator" - For DSI 14nm PHY: + For DSI 14nm and 10nm PHYs: * "dsi_pll" * "dsi_phy" * "dsi_phy_lane" @@ -112,6 +115,8 @@ Required properties: - vcca-supply: phandle to vcca regulator device node For 14nm PHY: - vcca-supply: phandle to vcca regulator device node + For 10nm PHY: +- vdds-supply: phandle to vdds regulator device node
Optional properties: - qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
On Wed, Jan 17, 2018 at 03:04:48PM +0530, Archit Taneja wrote:
SDM845 uses a newer revision (v2.0+) of the 6G DSI controller. This revision has another clock input at the block boundary called the byte interface clock. Specify this new clock in the binding.
A 10nm DSI PHY is used along with the controller. Add a compatible string for it and specify its base address/regulator supply needs.
Cc: Rob Herring robh@kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Archit Taneja architt@codeaurora.org
Documentation/devicetree/bindings/display/msm/dsi.txt | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)
Reviewed-by: Rob Herring robh@kernel.org
dri-devel@lists.freedesktop.org
-
Archit Taneja -
Rob Clark -
Rob Herring