As vendor document indicate, when REF_CLK bit set 0, then DP phy's REF_CLK should switch to 24M source clock.

But due to IC PHY layout mistaken, some chips need to flip this bit(like RK3288), and unfortunately they didn't indicate in the DP version register. That's why we have to make this little hack.

Signed-off-by: Yakir Yang ykk@rock-chips.com Reviewed-by: Tomasz Figa tomasz.figa@chromium.com Tested-by: Javier Martinez Canillas javier@osg.samsung.com --- Changes in v4: - Remove subdev_type number, and add 'is_rockchip(type)' helper function (Sean) - Add reviewed flag from Tomasz.

Changes in v3: - Make this hack code more clear (Tomasz, reviewed at Google Gerrit) reg = ~reg & REF_CLK_MASK; ---> reg ^= REF_CLK_MASK; [https://chromium-review.googlesource.com/#/c/346852/7/drivers/gpu/drm/bridge...] - Add tested flag from Javier

drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 12 ++++++++---- drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h | 1 + include/drm/bridge/analogix_dp.h | 5 +++++ 3 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c index 49205ef..48030f0 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c @@ -74,8 +74,12 @@ void analogix_dp_init_analog_param(struct analogix_dp_device *dp) reg = SEL_24M | TX_DVDD_BIT_1_0625V; writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2);

- if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP)) { - writel(REF_CLK_24M, dp->reg_base + ANALOGIX_DP_PLL_REG_1); + if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) { + reg = REF_CLK_24M; + if (dp->plat_data->dev_type == RK3288_DP) + reg ^= REF_CLK_MASK; + + writel(reg, dp->reg_base + ANALOGIX_DP_PLL_REG_1); writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2); writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3); writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4); @@ -244,7 +248,7 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp, u32 reg; u32 phy_pd_addr = ANALOGIX_DP_PHY_PD;

- if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP)) + if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) phy_pd_addr = ANALOGIX_DP_PD;

switch (block) { @@ -448,7 +452,7 @@ void analogix_dp_init_aux(struct analogix_dp_device *dp) analogix_dp_reset_aux(dp);

/* Disable AUX transaction H/W retry */ - if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP)) + if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) | AUX_HW_RETRY_COUNT_SEL(3) | AUX_HW_RETRY_INTERVAL_600_MICROSECONDS; diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h index 88d56ad..cdcc6c5 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h @@ -165,6 +165,7 @@ /* ANALOGIX_DP_PLL_REG_1 */ #define REF_CLK_24M (0x1 << 0) #define REF_CLK_27M (0x0 << 0) +#define REF_CLK_MASK (0x1 << 0)

/* ANALOGIX_DP_LANE_MAP */ #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6) diff --git a/include/drm/bridge/analogix_dp.h b/include/drm/bridge/analogix_dp.h index 25afb31..790ab5d 100644 --- a/include/drm/bridge/analogix_dp.h +++ b/include/drm/bridge/analogix_dp.h @@ -18,6 +18,11 @@ enum analogix_dp_devtype { RK3288_DP, };

+static inline bool is_rockchip(enum analogix_dp_devtype type) +{ + return type == RK3288_DP; +} + struct analogix_dp_plat_data { enum analogix_dp_devtype dev_type; struct drm_panel *panel;

RK3399 and RK3288 shared the same eDP IP controller, only some light difference with VOP configure and GRF configure.

Signed-off-by: Yakir Yang ykk@rock-chips.com Acked-by: Mark Yao mark.yao@rock-chips.com Reviewed-by: Tomasz Figa tomasz.figa@chromium.com --- Changes in v4: - Improved the overly complicated .atomic_check function. (Sean) - Add reviewed flag from Tomasz

Changes in v3: - Give the "rk3399-edp" a separate line for clarity in document (Tomasz, reviewed at Google Gerrit) [https://chromium-review.googlesource.com/#/c/346314/10/Documentation/devicet...] - Move 'output_type' setting before the return statement (Tomasz, reviewed at Google Gerrit) [https://chromium-review.googlesource.com/#/c/346314/10/drivers/gpu/drm/rockc...] - Add the acked flag from Mark.

.../bindings/display/bridge/analogix_dp.txt | 1 + .../display/rockchip/analogix_dp-rockchip.txt | 3 ++- drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 23 ++++++++++++++++++++++ include/drm/bridge/analogix_dp.h | 3 ++- 4 files changed, 28 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt b/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt index 4f2ba8c..4a0f4f7 100644 --- a/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt +++ b/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt @@ -5,6 +5,7 @@ Required properties for dp-controller: platform specific such as: * "samsung,exynos5-dp" * "rockchip,rk3288-dp" + * "rockchip,rk3399-edp" -reg: physical base address of the controller and length of memory mapped region. diff --git a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt index e832ff9..726c945 100644 --- a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt +++ b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt @@ -2,7 +2,8 @@ Rockchip RK3288 specific extensions to the Analogix Display Port ================================

Required properties: -- compatible: "rockchip,rk3288-edp"; +- compatible: "rockchip,rk3288-edp", + "rockchip,rk3399-edp";

- reg: physical base address of the controller and length

diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c index 0a30931..8557a08 100644 --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c @@ -36,6 +36,8 @@

#define RK3288_GRF_SOC_CON6 0x25c #define RK3288_EDP_LCDC_SEL BIT(5) +#define RK3399_GRF_SOC_CON20 0x6250 +#define RK3399_EDP_LCDC_SEL BIT(5)

#define HIWORD_UPDATE(val, mask) (val | (mask) << 16)

@@ -159,6 +161,8 @@ rockchip_dp_drm_encoder_atomic_check(struct drm_encoder *encoder, struct drm_connector_state *conn_state) { struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); + struct rockchip_dp_device *dp = to_dp(encoder); + int ret;

/* * FIXME(Yakir): driver should configure the CRTC output video @@ -173,8 +177,19 @@ rockchip_dp_drm_encoder_atomic_check(struct drm_encoder *encoder, * But if I configure CTRC to RGBaaa, and eDP driver still keep * RGB666 input video mode, then screen would works prefect. */ + s->output_mode = ROCKCHIP_OUT_MODE_AAAA; s->output_type = DRM_MODE_CONNECTOR_eDP; + if (dp->data->chip_type == RK3399_EDP) { + /* + * For RK3399, VOP Lit must code the out mode to RGB888, + * VOP Big must code the out mode to RGB10. + */ + ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node, + encoder); + if (ret > 0) + s->output_mode = ROCKCHIP_OUT_MODE_P888; + }

return 0; } @@ -378,6 +393,13 @@ static const struct dev_pm_ops rockchip_dp_pm_ops = { #endif };

+static const struct rockchip_dp_chip_data rk3399_edp = { + .lcdsel_grf_reg = RK3399_GRF_SOC_CON20, + .lcdsel_big = HIWORD_UPDATE(0, RK3399_EDP_LCDC_SEL), + .lcdsel_lit = HIWORD_UPDATE(RK3399_EDP_LCDC_SEL, RK3399_EDP_LCDC_SEL), + .chip_type = RK3399_EDP, +}; + static const struct rockchip_dp_chip_data rk3288_dp = { .lcdsel_grf_reg = RK3288_GRF_SOC_CON6, .lcdsel_big = HIWORD_UPDATE(0, RK3288_EDP_LCDC_SEL), @@ -387,6 +409,7 @@ static const struct rockchip_dp_chip_data rk3288_dp = {

static const struct of_device_id rockchip_dp_dt_ids[] = { {.compatible = "rockchip,rk3288-dp", .data = &rk3288_dp }, + {.compatible = "rockchip,rk3399-edp", .data = &rk3399_edp }, {} }; MODULE_DEVICE_TABLE(of, rockchip_dp_dt_ids); diff --git a/include/drm/bridge/analogix_dp.h b/include/drm/bridge/analogix_dp.h index 790ab5d..fc4aea3 100644 --- a/include/drm/bridge/analogix_dp.h +++ b/include/drm/bridge/analogix_dp.h @@ -16,11 +16,12 @@ enum analogix_dp_devtype { EXYNOS_DP, RK3288_DP, + RK3399_EDP, };

static inline bool is_rockchip(enum analogix_dp_devtype type) { - return type == RK3288_DP; + return type == RK3288_DP || type == RK3399_EDP; }

struct analogix_dp_plat_data {

Some boards don't need to declare a panel device node, like the display interface is DP monitors, so it's necessary to make the panel detect to an optional action.

Signed-off-by: Yakir Yang ykk@rock-chips.com Acked-by: Mark Yao mark.yao@rock-chips.com Reviewed-by: Tomasz Figa tomasz.figa@chromium.com --- Changes in v4: - Move of_node_put(panel_node) directly below of_drm_find_panel (Sean) - Add reviewed flag from Tomasz

Changes in v3: - Add the acked flag from Mark.

drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 47 +++++++++++-------------- 1 file changed, 21 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c index 8557a08..0755573 100644 --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c @@ -329,38 +329,33 @@ static int rockchip_dp_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct device_node *panel_node, *port, *endpoint; + struct drm_panel *panel = NULL; struct rockchip_dp_device *dp; - struct drm_panel *panel;

port = of_graph_get_port_by_id(dev->of_node, 1); - if (!port) { - dev_err(dev, "can't find output port\n"); - return -EINVAL; - } - - endpoint = of_get_child_by_name(port, "endpoint"); - of_node_put(port); - if (!endpoint) { - dev_err(dev, "no output endpoint found\n"); - return -EINVAL; - } - - panel_node = of_graph_get_remote_port_parent(endpoint); - of_node_put(endpoint); - if (!panel_node) { - dev_err(dev, "no output node found\n"); - return -EINVAL; - } - - panel = of_drm_find_panel(panel_node); - if (!panel) { - DRM_ERROR("failed to find panel\n"); + if (port) { + endpoint = of_get_child_by_name(port, "endpoint"); + of_node_put(port); + if (!endpoint) { + dev_err(dev, "no output endpoint found\n"); + return -EINVAL; + } + + panel_node = of_graph_get_remote_port_parent(endpoint); + of_node_put(endpoint); + if (!panel_node) { + dev_err(dev, "no output node found\n"); + return -EINVAL; + } + + panel = of_drm_find_panel(panel_node); of_node_put(panel_node); - return -EPROBE_DEFER; + if (!panel) { + DRM_ERROR("failed to find panel\n"); + return -EPROBE_DEFER; + } }

- of_node_put(panel_node); - dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL); if (!dp) return -ENOMEM;

It's better to pass the connector to platform driver in .get_modes() callback, just like what the .get_modes() helper function designed.

Signed-off-by: Yakir Yang ykk@rock-chips.com Reviewed-by: Sean Paul seanpaul@chromium.org Reviewed-by: Tomasz Figa tomasz.figa@chromium.com --- Changes in v4: - Add reviewed flag from Sean. - Add reviewed flag from Tomasz.

Changes in v3: - Avoid to change any internal driver state in .mode_valid interface. (Tomasz, reviewed at Google Gerrit) [https://chromium-review.googlesource.com/#/c/346318/10/drivers/gpu/drm/rockc...]

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 2 +- drivers/gpu/drm/exynos/exynos_dp.c | 4 ++-- include/drm/bridge/analogix_dp.h | 3 ++- 3 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c index 7699597..a5e5ae4 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c @@ -938,7 +938,7 @@ int analogix_dp_get_modes(struct drm_connector *connector) num_modes += drm_panel_get_modes(dp->plat_data->panel);

if (dp->plat_data->get_modes) - num_modes += dp->plat_data->get_modes(dp->plat_data); + num_modes += dp->plat_data->get_modes(dp->plat_data, connector);

return num_modes; } diff --git a/drivers/gpu/drm/exynos/exynos_dp.c b/drivers/gpu/drm/exynos/exynos_dp.c index 468498e..8a555ed 100644 --- a/drivers/gpu/drm/exynos/exynos_dp.c +++ b/drivers/gpu/drm/exynos/exynos_dp.c @@ -67,10 +67,10 @@ static int exynos_dp_poweroff(struct analogix_dp_plat_data *plat_data) return exynos_dp_crtc_clock_enable(plat_data, false); }

-static int exynos_dp_get_modes(struct analogix_dp_plat_data *plat_data) +static int exynos_dp_get_modes(struct analogix_dp_plat_data *plat_data, + struct drm_connector *connector) { struct exynos_dp_device *dp = to_dp(plat_data); - struct drm_connector *connector = &dp->connector; struct drm_display_mode *mode; int num_modes = 0;

diff --git a/include/drm/bridge/analogix_dp.h b/include/drm/bridge/analogix_dp.h index fc4aea3..261b86d 100644 --- a/include/drm/bridge/analogix_dp.h +++ b/include/drm/bridge/analogix_dp.h @@ -34,7 +34,8 @@ struct analogix_dp_plat_data { int (*power_off)(struct analogix_dp_plat_data *); int (*attach)(struct analogix_dp_plat_data *, struct drm_bridge *, struct drm_connector *); - int (*get_modes)(struct analogix_dp_plat_data *); + int (*get_modes)(struct analogix_dp_plat_data *, + struct drm_connector *); };

int analogix_dp_resume(struct device *dev);

For RK3399's GRF module, if we want to operate the graphic related grf registers, we need to enable the pclk_vio_grf which supply power for VIO GRF IOs, so it's better to introduce an optional grf clock in driver.

Signed-off-by: Yakir Yang ykk@rock-chips.com Reviewed-by: Douglas Anderson dianders@chromium.org Reviewed-by: Tomasz Figa tomasz.figa@chromium.com --- Changes in v4: - Add reviewed flag from Doug. - Add reviewed flag from Tomasz. - Fix compiled error, sorry. "dp->cgfclk" --> 'dp->grfclk' - Check the the error code properly, 'EPROBE_DEFER' should be returned, 'ENOENT' should assign a NULL point to grfclk, other errors should be regarded as failed. (Tomasz, Doug, reviewed at Google Gerrit) [https://chromium-review.googlesource.com/#/c/351821/20/drivers/gpu/drm/rockc...] - Add the document about optional 'grf' clock (Tomasz, Doug, reviewed at Google Gerrit) [https://chromium-review.googlesource.com/#/c/351821/]

Changes in v3: - Add this patch in v3

.../display/rockchip/analogix_dp-rockchip.txt | 6 ++++++ drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 23 +++++++++++++++++++--- 2 files changed, 26 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt index 726c945..0b39256 100644 --- a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt +++ b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt @@ -28,6 +28,12 @@ Required properties: Port 0: contained 2 endpoints, connecting to the output of vop. Port 1: contained 1 endpoint, connecting to the input of panel.

+Optional property for different chips: +- clocks: from common clock binding: handle to grf_vio clock. + +- clock-names: from common clock binding: + Required elements: "grf" + For the below properties, please refer to Analogix DP binding document: * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt - phys (required) diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c index 850edc4..e81e19a 100644 --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c @@ -64,6 +64,7 @@ struct rockchip_dp_device { struct drm_display_mode mode;

struct clk *pclk; + struct clk *grfclk; struct regmap *grf; struct reset_control *rst;

@@ -160,11 +161,17 @@ static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder)

dev_dbg(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");

- ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val); - if (ret != 0) { - dev_err(dp->dev, "Could not write to GRF: %d\n", ret); + ret = clk_prepare_enable(dp->grfclk); + if (ret < 0) { + dev_err(dp->dev, "failed to enable grfclk %d\n", ret); return; } + + ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val); + if (ret != 0) + dev_err(dp->dev, "Could not write to GRF: %d\n", ret); + + clk_disable_unprepare(dp->grfclk); }

static void rockchip_dp_drm_encoder_nop(struct drm_encoder *encoder) @@ -234,6 +241,16 @@ static int rockchip_dp_init(struct rockchip_dp_device *dp) return PTR_ERR(dp->grf); }

+ dp->grfclk = devm_clk_get(dev, "grf"); + if (PTR_ERR(dp->grfclk) == -ENOENT) { + dp->grfclk = NULL; + } else if (PTR_ERR(dp->grfclk) == -EPROBE_DEFER) { + return -EPROBE_DEFER; + } else if (IS_ERR(dp->grfclk)) { + dev_err(dev, "failed to get grf clock\n"); + return PTR_ERR(dp->grfclk); + } + dp->pclk = devm_clk_get(dev, "pclk"); if (IS_ERR(dp->pclk)) { dev_err(dev, "failed to get pclk property\n");