Add ADE display controller binding doc. Add DesignWare DSI Host Controller v1.20a binding doc.

v4: - Describe more specific of clocks and ports. - Fix indentation. v3: - Make ade as the drm master node. - Use assigned-clocks to set clock rate. - Use ports to connect display relavant nodes. v2: - Move dt binding docs to bindings/display/hisilicon directory.

Signed-off-by: Xinwei Kong kong.kongxinwei@hisilicon.com Signed-off-by: Xinliang Liu xinliang.liu@linaro.org --- .../bindings/display/hisilicon/dw-dsi.txt | 77 ++++++++++++++++++++++ .../bindings/display/hisilicon/hisi-ade.txt | 69 +++++++++++++++++++ 2 files changed, 146 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/hisilicon/dw-dsi.txt create mode 100644 Documentation/devicetree/bindings/display/hisilicon/hisi-ade.txt

diff --git a/Documentation/devicetree/bindings/display/hisilicon/dw-dsi.txt b/Documentation/devicetree/bindings/display/hisilicon/dw-dsi.txt new file mode 100644 index 000000000000..af6d702f3282 --- /dev/null +++ b/Documentation/devicetree/bindings/display/hisilicon/dw-dsi.txt @@ -0,0 +1,77 @@ +Device-Tree bindings for DesignWare DSI Host Controller v1.20a driver + +A DSI Host Controller resides in the middle of display controller and external +HDMI converter. + +Required properties: +- compatible: value should be "hisilicon,hi6220-dsi". +- reg: physical base address and length of dsi controller's registers. +- clocks: the clocks needed. +- clock-names: the name of the clocks. +- ports: contains DSI controller input and output sub port. + The input port connects to ADE output port with the reg value "0". + The output port with the reg value "1", it could connect to panel or + any other bridge endpoints. And the reg value for bridge endpoint is "0", + other values for panel endpoint. + See Documentation/devicetree/bindings/graph.txt for more device graph info. + +A example of HiKey board hi6220 SoC and board specific DT entry: +Example: + +SoC specific: + dsi: dsi@f4107800 { + compatible = "hisilicon,hi6220-dsi"; + reg = <0x0 0xf4107800 0x0 0x100>; + clocks = <&media_ctrl HI6220_DSI_PCLK>; + clock-names = "pclk_dsi"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* 0 for input port */ + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <&ade_out>; + }; + }; + }; + }; + + +Board specific: + &dsi { + status = "ok"; + + ports { + /* 1 for output port */ + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + /* 0 for bridge, other value for panel */ + dsi_out0: endpoint@0 { + reg = <0>; + remote-endpoint = <&adv7533_in>; + }; + }; + }; + }; + + &i2c2 { + ... + + adv7533: adv7533@39 { + ... + + port { + adv7533_in: endpoint { + remote-endpoint = <&dsi_out0>; + }; + }; + }; + }; + diff --git a/Documentation/devicetree/bindings/display/hisilicon/hisi-ade.txt b/Documentation/devicetree/bindings/display/hisilicon/hisi-ade.txt new file mode 100644 index 000000000000..1eff5a41b98d --- /dev/null +++ b/Documentation/devicetree/bindings/display/hisilicon/hisi-ade.txt @@ -0,0 +1,69 @@ +Device-Tree bindings for hisilicon ADE display controller driver + +ADE (Advanced Display Engine) is the display controller which grab image +data from memory, do composition, do post image processing, generate RGB +timing stream and transfer to DSI. + +Required properties: +- compatible: value should be "hisilicon,hi6220-ade". +- reg: physical base address and length of the controller's registers. + Three reg ranges are used in ADE driver: + ADE reg range, value should be "<0x0 0xf4100000 0x0 0x7800>"; + media subsystem reg range, value should be "<0x0 0xf4410000 0x0 0x1000>"; + media subsystem NOC QoS reg range, value should be "<0x0 0xf4520000 0x0 + 0x1000>". +- reg-names: name of physical base.Valuse should be "ade_base", "media_base" + and "media_noc_base". +- interrupt: the ldi vblank interrupt number used. +- clocks: the clocks needed. Three clocks are used in ADE driver: + ADE core clock, value should be "<&media_ctrl HI6220_ADE_CORE>"; + ADE pixel clok, value should be "<&media_ctrl HI6220_ADE_PIX_SRC>"; + media NOC QoS clock, value should be "<&media_ctrl HI6220_CODEC_JPEG>". +- clock-names: the name of the clocks. Values should be "clk_ade_core", + "clk_codec_jpeg" and "clk_ade_pix". +- assigned-clocks: clocks to be assigned rate. +- assigned-clock-rates: clock rates which are assigned to assigned-clocks. + The rate of <&media_ctrl HI6220_ADE_CORE> could be "360000000" or + "180000000"; + The rate of <&media_ctrl HI6220_CODEC_JPEG> could be less than "1440000000". +- port: the output port. This contains one endpoint subnode, with its + remote-endpoint set to the phandle of the connected DSI input endpoint. + See Documentation/devicetree/bindings/graph.txt for more device graph info. + +Optional properties: +- dma-coherent: Present if dma operations are coherent. + + +A example of HiKey board hi6220 SoC specific DT entry: +Example: + + ade: ade@f4100000 { + compatible = "hisilicon,hi6220-ade"; + reg = <0x0 0xf4100000 0x0 0x7800>, + <0x0 0xf4410000 0x0 0x1000>, + <0x0 0xf4520000 0x0 0x1000>; + reg-names = "ade_base", + "media_base", + "media_noc_base"; + + interrupts = <0 115 4>; /* ldi interrupt */ + + clocks = <&media_ctrl HI6220_ADE_CORE>, + <&media_ctrl HI6220_CODEC_JPEG>, + <&media_ctrl HI6220_ADE_PIX_SRC>; + /*clock name*/ + clock-names = "clk_ade_core", + "clk_codec_jpeg", + "clk_ade_pix"; + + assigned-clocks = <&media_ctrl HI6220_ADE_CORE>, + <&media_ctrl HI6220_CODEC_JPEG>; + assigned-clock-rates = <360000000>, <288000000>; + dma-coherent; + + port { + ade_out: endpoint { + remote-endpoint = <&dsi_in>; + }; + }; + };

Add crtc funcs and helper funcs for ADE.

v4: None. v3: - Make ade as the master driver. - Use port to connect with encoder. - A few cleanup. v2: - Remove abtraction layer.

Signed-off-by: Xinliang Liu xinliang.liu@linaro.org --- drivers/gpu/drm/hisilicon/kirin/Makefile | 3 +- drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h | 280 +++++++++++++++ drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c | 458 ++++++++++++++++++++++++ drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c | 15 + drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h | 8 + 5 files changed, 763 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h create mode 100644 drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c

diff --git a/drivers/gpu/drm/hisilicon/kirin/Makefile b/drivers/gpu/drm/hisilicon/kirin/Makefile index cb346de47d48..2a61ab006ddb 100644 --- a/drivers/gpu/drm/hisilicon/kirin/Makefile +++ b/drivers/gpu/drm/hisilicon/kirin/Makefile @@ -1,3 +1,4 @@ -kirin-drm-y := kirin_drm_drv.o +kirin-drm-y := kirin_drm_drv.o \ + kirin_drm_ade.o

obj-$(CONFIG_DRM_HISI_KIRIN) += kirin-drm.o diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h b/drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h new file mode 100644 index 000000000000..78020747abfe --- /dev/null +++ b/drivers/gpu/drm/hisilicon/kirin/kirin_ade_reg.h @@ -0,0 +1,280 @@ +/* + * Copyright (c) 2016 Linaro Limited. + * Copyright (c) 2014-2016 Hisilicon Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __KIRIN_ADE_REG_H__ +#define __KIRIN_ADE_REG_H__ + +/* + * ADE Registers + */ +#define MASK(x) (BIT(x) - 1) + +#define ADE_CTRL 0x0004 +#define FRM_END_START_OFST 0 +#define FRM_END_START_MASK MASK(2) +#define ADE_CTRL1 0x008C +#define AUTO_CLK_GATE_EN_OFST 0 +#define AUTO_CLK_GATE_EN BIT(0) +#define ADE_ROT_SRC_CFG 0x0010 +#define ADE_DISP_SRC_CFG 0x0018 +#define ADE_WDMA2_SRC_CFG 0x001C +#define ADE_SEC_OVLY_SRC_CFG 0x0020 +#define ADE_WDMA3_SRC_CFG 0x0024 +#define ADE_OVLY1_TRANS_CFG 0x002C +#define ADE_EN 0x0100 +#define ADE_DISABLE 0 +#define ADE_ENABLE 1 +#define INTR_MASK_CPU(x) (0x0C10 + (x) * 0x4) +#define ADE_FRM_DISGARD_CTRL 0x00A4 +/* reset and reload regs */ +#define ADE_SOFT_RST_SEL(x) (0x0078 + (x) * 0x4) +#define ADE_RELOAD_DIS(x) (0x00AC + (x) * 0x4) +#define RDMA_OFST 0 +#define CLIP_OFST 15 +#define SCL_OFST 21 +#define CTRAN_OFST 24 +#define OVLY_OFST 37 /* 32+5 */ +/* channel regs */ +#define RD_CH_PE(x) (0x1000 + (x) * 0x80) +#define RD_CH_CTRL(x) (0x1004 + (x) * 0x80) +#define RD_CH_ADDR(x) (0x1008 + (x) * 0x80) +#define RD_CH_SIZE(x) (0x100C + (x) * 0x80) +#define RD_CH_STRIDE(x) (0x1010 + (x) * 0x80) +#define RD_CH_SPACE(x) (0x1014 + (x) * 0x80) +#define RD_CH_PARTIAL_SIZE(x) (0x1018 + (x) * 0x80) +#define RD_CH_PARTIAL_SPACE(x) (0x101C + (x) * 0x80) +#define RD_CH_EN(x) (0x1020 + (x) * 0x80) +#define RD_CH_STATUS(x) (0x1024 + (x) * 0x80) +#define RD_CH_DISP_CTRL 0x1404 +#define RD_CH_DISP_ADDR 0x1408 +#define RD_CH_DISP_SIZE 0x140C +#define RD_CH_DISP_STRIDE 0x1410 +#define RD_CH_DISP_SPACE 0x1414 +#define RD_CH_DISP_EN 0x142C +/* clip regs */ +#define ADE_CLIP_DISABLE(x) (0x6800 + (x) * 0x100) +#define ADE_CLIP_SIZE0(x) (0x6804 + (x) * 0x100) +#define ADE_CLIP_SIZE1(x) (0x6808 + (x) * 0x100) +#define ADE_CLIP_SIZE2(x) (0x680C + (x) * 0x100) +#define ADE_CLIP_CFG_OK(x) (0x6810 + (x) * 0x100) +/* scale regs */ +#define ADE_SCL1_MUX_CFG 0x000C +#define ADE_SCL2_SRC_CFG 0x0014 +#define ADE_SCL3_MUX_CFG 0x0008 +#define ADE_SCL_CTRL(x) (0x3000 + (x) * 0x800) +#define ADE_SCL_HSP(x) (0x3004 + (x) * 0x800) +#define ADE_SCL_UV_HSP(x) (0x3008 + (x) * 0x800) +#define ADE_SCL_VSP(x) (0x300C + (x) * 0x800) +#define ADE_SCL_UV_VSP(x) (0x3010 + (x) * 0x800) +#define ADE_SCL_ORES(x) (0x3014 + (x) * 0x800) +#define ADE_SCL_IRES(x) (0x3018 + (x) * 0x800) +#define ADE_SCL_START(x) (0x301C + (x) * 0x800) +#define ADE_SCL_ERR(x) (0x3020 + (x) * 0x800) +#define ADE_SCL_PIX_OFST(x) (0x3024 + (x) * 0x800) +#define ADE_SCL_UV_PIX_OFST(x) (0x3028 + (x) * 0x800) +#define ADE_SCL_COEF_CLR(x) (0x3030 + (x) * 0x800) +#define ADE_SCL_HCOEF(x, m, n) (0x3100 + (x) * 0x800 + \ + 12 * (m) + 4 * (n)) +#define ADE_SCL_VCOEF(x, i, j) (0x340C + (x) * 0x800 + \ + 12 * (i) + 4 * (j)) +/* ctran regs */ +#define ADE_CTRAN5_TRANS_CFG 0x0040 +#define ADE_CTRAN_DIS(x) (0x5004 + (x) * 0x100) +#define CTRAN_BYPASS_ON 1 +#define CTRAN_BYPASS_OFF 0 +#define ADE_CTRAN_MODE_CHOOSE(x) (0x5008 + (x) * 0x100) +#define ADE_CTRAN_STAT(x) (0x500C + (x) * 0x100) +#define ADE_CTRAN_CHDC0(x) (0x5010 + (x) * 0x100) +#define ADE_CTRAN_CHDC1(x) (0x5014 + (x) * 0x100) +#define ADE_CTRAN_CHDC2(x) (0x5018 + (x) * 0x100) +#define ADE_CTRAN_CHDC3(x) (0x501C + (x) * 0x100) +#define ADE_CTRAN_CHDC4(x) (0x5020 + (x) * 0x100) +#define ADE_CTRAN_CHDC5(x) (0x5024 + (x) * 0x100) +#define ADE_CTRAN_CSC0(x) (0x5028 + (x) * 0x100) +#define ADE_CTRAN_CSC1(x) (0x502C + (x) * 0x100) +#define ADE_CTRAN_CSC2(x) (0x5030 + (x) * 0x100) +#define ADE_CTRAN_CSC3(x) (0x5034 + (x) * 0x100) +#define ADE_CTRAN_CSC4(x) (0x5038 + (x) * 0x100) +#define ADE_CTRAN_IMAGE_SIZE(x) (0x503C + (x) * 0x100) +#define ADE_CTRAN_CFG_OK(x) (0x5040 + (x) * 0x100) +/* overlay regs */ +#define ADE_OVLY_ALPHA_ST 0x2000 +#define ADE_OVLY_CH_XY0(x) (0x2004 + (x) * 4) +#define ADE_OVLY_CH_XY1(x) (0x2024 + (x) * 4) +#define ADE_OVLY_CH_CTL(x) (0x204C + (x) * 4) +#define ADE_OVLY_OUTPUT_SIZE(x) (0x2070 + (x) * 8) +#define OUTPUT_XSIZE_OFST 16 +#define ADE_OVLY_BASE_COLOR(x) (0x2074 + (x) * 8) +#define ADE_OVLYX_CTL(x) (0x209C + (x) * 4) +#define ADE_OVLY_CTL 0x0098 +#define CH_OVLY_SEL_OFST(x) ((x) * 4) +#define CH_OVLY_SEL_MASK MASK(2) +#define CH_OVLY_SEL_VAL(x) ((x) + 1) +#define CH_ALP_MODE_OFST 0 +#define CH_ALP_SEL_OFST 2 +#define CH_UNDER_ALP_SEL_OFST 4 +#define CH_EN_OFST 6 +#define CH_ALP_GBL_OFST 15 +#define CH_SEL_OFST 28 + +/* + * LDI Registers + */ +#define LDI_HRZ_CTRL0 0x7400 +#define HBP_OFST 20 +#define LDI_HRZ_CTRL1 0x7404 +#define LDI_VRT_CTRL0 0x7408 +#define VBP_OFST 20 +#define LDI_VRT_CTRL1 0x740C +#define LDI_PLR_CTRL 0x7410 +#define FLAG_NVSYNC BIT(0) +#define FLAG_NHSYNC BIT(1) +#define FLAG_NPIXCLK BIT(2) +#define FLAG_NDE BIT(3) +#define LDI_DSP_SIZE 0x7414 +#define VSIZE_OFST 20 +#define LDI_INT_EN 0x741C +#define FRAME_END_INT_EN_OFST 1 +#define LDI_CTRL 0x7420 +#define BPP_OFST 3 +#define DATA_GATE_EN BIT(2) +#define LDI_EN BIT(0) +#define LDI_ORG_INT 0x7424 +#define LDI_MSK_INT 0x7428 +#define LDI_INT_CLR 0x742C +#define LDI_WORK_MODE 0x7430 +#define LDI_DE_SPACE_LOW 0x7438 +#define LDI_MCU_INTS 0x7450 +#define LDI_MCU_INTE 0x7454 +#define LDI_MCU_INTC 0x7458 +#define LDI_HDMI_DSI_GT 0x7434 + +/* + * media regs + */ +#define SC_MEDIA_RSTDIS 0x0530 +#define SC_MEDIA_RSTEN 0x052C +#define NOC_ADE0_QOSGENERATOR_MODE 0x010C +#define NOC_ADE0_QOSGENERATOR_EXTCONTROL 0x0118 +#define NOC_ADE1_QOSGENERATOR_MODE 0x020C +#define NOC_ADE1_QOSGENERATOR_EXTCONTROL 0x0218 + +/* + * ADE regs relevant enums + */ +enum frame_end_start { + /* regs take effective in every vsync */ + REG_EFFECTIVE_IN_VSYNC = 0, + /* regs take effective in fist ade en and every frame end */ + REG_EFFECTIVE_IN_ADEEN_FRMEND, + /* regs take effective in ade en immediately */ + REG_EFFECTIVE_IN_ADEEN, + /* regs take effective in first vsync and every frame end */ + REG_EFFECTIVE_IN_VSYNC_FRMEND +}; + +enum ade_fb_format { + ADE_RGB_565 = 0, + ADE_BGR_565, + ADE_XRGB_8888, + ADE_XBGR_8888, + ADE_ARGB_8888, + ADE_ABGR_8888, + ADE_RGBA_8888, + ADE_BGRA_8888, + ADE_RGB_888, + ADE_BGR_888 = 9, + ADE_FORMAT_NOT_SUPPORT = 800 +}; + +enum ade_channel { + ADE_CH1 = 0, /* channel 1 for primary plane */ + ADE_CH_NUM +}; + +enum ade_scale { + ADE_SCL1 = 0, + ADE_SCL2, + ADE_SCL3, + ADE_SCL_NUM +}; + +enum ade_ctran { + ADE_CTRAN1 = 0, + ADE_CTRAN2, + ADE_CTRAN3, + ADE_CTRAN4, + ADE_CTRAN5, + ADE_CTRAN6, + ADE_CTRAN_NUM +}; + +enum ade_overlay { + ADE_OVLY1 = 0, + ADE_OVLY2, + ADE_OVLY3, + ADE_OVLY_NUM +}; + +enum ade_alpha_mode { + ADE_ALP_GLOBAL = 0, + ADE_ALP_PIXEL, + ADE_ALP_PIXEL_AND_GLB +}; + +enum ade_alpha_blending_mode { + ADE_ALP_MUL_COEFF_0 = 0, /* alpha */ + ADE_ALP_MUL_COEFF_1, /* 1-alpha */ + ADE_ALP_MUL_COEFF_2, /* 0 */ + ADE_ALP_MUL_COEFF_3 /* 1 */ +}; + +/* + * LDI regs relevant enums + */ +enum dsi_pclk_en { + DSI_PCLK_ON = 0, + DSI_PCLK_OFF +}; + +enum ldi_output_format { + LDI_OUT_RGB_565 = 0, + LDI_OUT_RGB_666, + LDI_OUT_RGB_888 +}; + +enum ldi_work_mode { + TEST_MODE = 0, + NORMAL_MODE +}; + +enum ldi_input_source { + DISP_SRC_NONE = 0, + DISP_SRC_OVLY2, + DISP_SRC_DISP, + DISP_SRC_ROT, + DISP_SRC_SCL2 +}; + +/* + * Register Write/Read Helper functions + */ +static inline void ade_update_bits(void __iomem *addr, u32 bit_start, + u32 mask, u32 val) +{ + u32 tmp, orig; + + orig = readl(addr); + tmp = orig & ~(mask << bit_start); + tmp |= (val & mask) << bit_start; + writel(tmp, addr); +} + +#endif diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c new file mode 100644 index 000000000000..b45149616716 --- /dev/null +++ b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c @@ -0,0 +1,458 @@ +/* + * Hisilicon Hi6220 SoC ADE(Advanced Display Engine)'s crtc&plane driver + * + * Copyright (c) 2016 Linaro Limited. + * Copyright (c) 2014-2016 Hisilicon Limited. + * + * Author: + * Xinliang Liu z.liuxinliang@hisilicon.com + * Xinliang Liu xinliang.liu@linaro.org + * Xinwei Kong kong.kongxinwei@hisilicon.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <linux/bitops.h> +#include <linux/clk.h> +#include <video/display_timing.h> + +#include <drm/drmP.h> +#include <drm/drm_crtc.h> +#include <drm/drm_crtc_helper.h> +#include <drm/drm_atomic.h> +#include <drm/drm_atomic_helper.h> + +#include "kirin_drm_drv.h" +#include "kirin_ade_reg.h" + +#define to_ade_crtc(crtc) \ + container_of(crtc, struct ade_crtc, base) + +struct ade_hw_ctx { + void __iomem *base; + void __iomem *media_base; + void __iomem *media_noc_base; + int irq; + struct clk *ade_core_clk; + struct clk *media_noc_clk; + struct clk *ade_pix_clk; + bool power_on; +}; + +struct ade_crtc { + struct drm_crtc base; + struct ade_hw_ctx *ctx; + bool enable; + u32 out_format; +}; + +struct ade_data { + struct ade_crtc acrtc; + struct ade_hw_ctx ctx; +}; + +static void ade_update_reload_bit(void __iomem *base, u32 bit_num, u32 val) +{ + u32 bit_ofst, reg_num; + + bit_ofst = bit_num % 32; + reg_num = bit_num / 32; + + ade_update_bits(base + ADE_RELOAD_DIS(reg_num), bit_ofst, + MASK(1), !!val); +} + +static u32 ade_read_reload_bit(void __iomem *base, u32 bit_num) +{ + u32 tmp, bit_ofst, reg_num; + + bit_ofst = bit_num % 32; + reg_num = bit_num / 32; + + tmp = readl(base + ADE_RELOAD_DIS(reg_num)); + return !!(BIT(bit_ofst) & tmp); +} + +static void ade_init(struct ade_hw_ctx *ctx) +{ + void __iomem *base = ctx->base; + + /* enable clk gate */ + ade_update_bits(base + ADE_CTRL1, AUTO_CLK_GATE_EN_OFST, + AUTO_CLK_GATE_EN, ADE_ENABLE); + /* clear overlay */ + writel(0, base + ADE_OVLY1_TRANS_CFG); + writel(0, base + ADE_OVLY_CTL); + writel(0, base + ADE_OVLYX_CTL(ADE_OVLY2)); + /* clear reset and reload regs */ + writel(MASK(32), base + ADE_SOFT_RST_SEL(0)); + writel(MASK(32), base + ADE_SOFT_RST_SEL(1)); + writel(MASK(32), base + ADE_RELOAD_DIS(0)); + writel(MASK(32), base + ADE_RELOAD_DIS(1)); + /* for video mode, that ade registers + * became effective at frame end + */ + ade_update_bits(base + ADE_CTRL, FRM_END_START_OFST, + FRM_END_START_MASK, REG_EFFECTIVE_IN_ADEEN_FRMEND); +} + +static void ade_ldi_set_mode(struct ade_crtc *acrtc, + struct drm_display_mode *mode, + struct drm_display_mode *adj_mode) +{ + struct ade_hw_ctx *ctx = acrtc->ctx; + void __iomem *base = ctx->base; + u32 width = mode->hdisplay; + u32 height = mode->vdisplay; + u32 hfp, hbp, hsw, vfp, vbp, vsw; + u32 plr_flags; + int ret; + + plr_flags = (mode->flags & DRM_MODE_FLAG_NVSYNC) ? FLAG_NVSYNC : 0; + plr_flags |= (mode->flags & DRM_MODE_FLAG_NHSYNC) ? FLAG_NHSYNC : 0; + hfp = mode->hsync_start - mode->hdisplay; + hbp = mode->htotal - mode->hsync_end; + hsw = mode->hsync_end - mode->hsync_start; + vfp = mode->vsync_start - mode->vdisplay; + vbp = mode->vtotal - mode->vsync_end; + vsw = mode->vsync_end - mode->vsync_start; + if (vsw > 15) { + DRM_DEBUG_DRIVER("vsw exceeded 15\n"); + vsw = 15; + } + + writel((hbp << HBP_OFST) | hfp, base + LDI_HRZ_CTRL0); + /* the configured value is actual value - 1 */ + writel(hsw - 1, base + LDI_HRZ_CTRL1); + writel((vbp << VBP_OFST) | vfp, base + LDI_VRT_CTRL0); + /* the configured value is actual value - 1 */ + writel(vsw - 1, base + LDI_VRT_CTRL1); + /* the configured value is actual value - 1 */ + writel(((height - 1) << VSIZE_OFST) | (width - 1), + base + LDI_DSP_SIZE); + writel(plr_flags, base + LDI_PLR_CTRL); + + /* Success should be guaranteed in mode_valid call back, + * so failer shouldn't happen here + */ + ret = clk_set_rate(ctx->ade_pix_clk, mode->clock * 1000); + if (ret) + DRM_ERROR("failed to set pixel clk %dHz (%d)\n", + mode->clock * 1000, ret); + adj_mode->clock = clk_get_rate(ctx->ade_pix_clk) / 1000; + + /* ctran6 setting */ + writel(CTRAN_BYPASS_ON, base + ADE_CTRAN_DIS(ADE_CTRAN6)); + /* the configured value is actual value - 1 */ + writel(width * height - 1, base + ADE_CTRAN_IMAGE_SIZE(ADE_CTRAN6)); + ade_update_reload_bit(base, CTRAN_OFST + ADE_CTRAN6, 0); + + DRM_DEBUG_DRIVER("set mode: %dx%d\n", width, height); +} + +static int ade_power_up(struct ade_hw_ctx *ctx) +{ + void __iomem *media_base = ctx->media_base; + int ret; + + ret = clk_prepare_enable(ctx->media_noc_clk); + if (ret) { + DRM_ERROR("failed to enable media_noc_clk (%d)\n", ret); + return ret; + } + + writel(0x20, media_base + SC_MEDIA_RSTDIS); + + ret = clk_prepare_enable(ctx->ade_core_clk); + if (ret) { + DRM_ERROR("failed to enable ade_core_clk (%d)\n", ret); + return ret; + } + + ade_init(ctx); + ctx->power_on = true; + return 0; +} + +static void ade_power_down(struct ade_hw_ctx *ctx) +{ + void __iomem *base = ctx->base; + void __iomem *media_base = ctx->media_base; + + writel(ADE_DISABLE, base + LDI_CTRL); + /* dsi pixel off */ + writel(DSI_PCLK_OFF, base + LDI_HDMI_DSI_GT); + + clk_disable_unprepare(ctx->ade_core_clk); + writel(0x20, media_base + SC_MEDIA_RSTEN); + clk_disable_unprepare(ctx->media_noc_clk); + ctx->power_on = false; +} + +static void ade_set_medianoc_qos(struct ade_crtc *acrtc) +{ + struct ade_hw_ctx *ctx = acrtc->ctx; + void __iomem *base = ctx->media_noc_base; + void __iomem *reg; + u32 val; + + reg = base + NOC_ADE0_QOSGENERATOR_MODE; + val = (readl(reg) & 0xfffffffc) | 0x2; + writel(val, reg); + + reg = base + NOC_ADE0_QOSGENERATOR_EXTCONTROL; + val = readl(reg) | 0x1; + writel(val, reg); + + reg = base + NOC_ADE1_QOSGENERATOR_MODE; + val = (readl(reg) & 0xfffffffc) | 0x2; + writel(val, reg); + + reg = base + NOC_ADE1_QOSGENERATOR_EXTCONTROL; + val = readl(reg) | 0x1; + writel(val, reg); +} + +static void ade_display_enable(struct ade_crtc *acrtc) +{ + struct ade_hw_ctx *ctx = acrtc->ctx; + void __iomem *base = ctx->base; + u32 out_fmt = acrtc->out_format; + + /* display source setting */ + writel(DISP_SRC_OVLY2, base + ADE_DISP_SRC_CFG); + + /* enable ade */ + writel(ADE_ENABLE, base + ADE_EN); + /* enable ldi */ + writel(NORMAL_MODE, base + LDI_WORK_MODE); + writel((out_fmt << BPP_OFST) | DATA_GATE_EN | LDI_EN, + base + LDI_CTRL); + /* dsi pixel on */ + writel(DSI_PCLK_ON, base + LDI_HDMI_DSI_GT); +} + +static void ade_crtc_enable(struct drm_crtc *crtc) +{ + struct ade_crtc *acrtc = to_ade_crtc(crtc); + struct ade_hw_ctx *ctx = acrtc->ctx; + int ret; + + if (acrtc->enable) + return; + + if (!ctx->power_on) { + ret = ade_power_up(ctx); + if (ret) + return; + } + + ade_set_medianoc_qos(acrtc); + ade_display_enable(acrtc); + acrtc->enable = true; +} + +static void ade_crtc_disable(struct drm_crtc *crtc) +{ + struct ade_crtc *acrtc = to_ade_crtc(crtc); + struct ade_hw_ctx *ctx = acrtc->ctx; + + if (!acrtc->enable) + return; + + ade_power_down(ctx); + acrtc->enable = false; +} + +static int ade_crtc_atomic_check(struct drm_crtc *crtc, + struct drm_crtc_state *state) +{ + /* do nothing */ + return 0; +} + +static void ade_crtc_mode_set_nofb(struct drm_crtc *crtc) +{ + struct ade_crtc *acrtc = to_ade_crtc(crtc); + struct ade_hw_ctx *ctx = acrtc->ctx; + struct drm_display_mode *mode = &crtc->state->mode; + struct drm_display_mode *adj_mode = &crtc->state->adjusted_mode; + + if (!ctx->power_on) + (void)ade_power_up(ctx); + ade_ldi_set_mode(acrtc, mode, adj_mode); +} + +static void ade_crtc_atomic_begin(struct drm_crtc *crtc, + struct drm_crtc_state *old_state) +{ + struct ade_crtc *acrtc = to_ade_crtc(crtc); + struct ade_hw_ctx *ctx = acrtc->ctx; + + if (!ctx->power_on) + (void)ade_power_up(ctx); +} + +static void ade_crtc_atomic_flush(struct drm_crtc *crtc, + struct drm_crtc_state *old_state) + +{ + struct ade_crtc *acrtc = to_ade_crtc(crtc); + struct ade_hw_ctx *ctx = acrtc->ctx; + void __iomem *base = ctx->base; + + /* only crtc is eanbled regs take effect */ + if (acrtc->enable) { + /* flush ade regitsters */ + writel(ADE_ENABLE, base + ADE_EN); + } +} + +static const struct drm_crtc_helper_funcs ade_crtc_helper_funcs = { + .enable = ade_crtc_enable, + .disable = ade_crtc_disable, + .atomic_check = ade_crtc_atomic_check, + .mode_set_nofb = ade_crtc_mode_set_nofb, + .atomic_begin = ade_crtc_atomic_begin, + .atomic_flush = ade_crtc_atomic_flush, +}; + +static const struct drm_crtc_funcs ade_crtc_funcs = { + .destroy = drm_crtc_cleanup, + .set_config = drm_atomic_helper_set_config, + .page_flip = drm_atomic_helper_page_flip, + .reset = drm_atomic_helper_crtc_reset, + .set_property = drm_atomic_helper_crtc_set_property, + .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, +}; + +static int ade_crtc_init(struct drm_device *dev, struct drm_crtc *crtc, + struct drm_plane *plane) +{ + struct kirin_drm_private *priv = dev->dev_private; + struct device_node *port; + int ret; + + /* set crtc port so that + * drm_of_find_possible_crtcs call works + */ + port = of_get_child_by_name(dev->dev->of_node, "port"); + if (!port) { + DRM_ERROR("no port node found in %s\n", + dev->dev->of_node->full_name); + return -EINVAL; + } + of_node_put(port); + crtc->port = port; + + ret = drm_crtc_init_with_planes(dev, crtc, plane, NULL, + &ade_crtc_funcs, NULL); + if (ret) { + DRM_ERROR("failed to init crtc.\n"); + return ret; + } + + drm_crtc_helper_add(crtc, &ade_crtc_helper_funcs); + priv->crtc[drm_crtc_index(crtc)] = crtc; + + return 0; +} + +static int ade_dts_parse(struct platform_device *pdev, struct ade_hw_ctx *ctx) +{ + struct resource *res; + struct device *dev = &pdev->dev; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ade_base"); + ctx->base = devm_ioremap_resource(dev, res); + if (IS_ERR(ctx->base)) { + DRM_ERROR("failed to remap ade io base\n"); + return PTR_ERR(ctx->base); + } + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "media_base"); + ctx->media_base = devm_ioremap_resource(dev, res); + if (IS_ERR(ctx->media_base)) { + DRM_ERROR("failed to remap media io base\n"); + return PTR_ERR(ctx->media_base); + } + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "media_noc_base"); + ctx->media_noc_base = devm_ioremap_resource(dev, res); + if (IS_ERR(ctx->media_noc_base)) { + DRM_ERROR("failed to remap media noc base\n"); + return PTR_ERR(ctx->media_noc_base); + } + + ctx->irq = platform_get_irq(pdev, 0); + if (ctx->irq < 0) { + DRM_ERROR("failed to get irq\n"); + return -ENODEV; + } + + ctx->ade_core_clk = devm_clk_get(dev, "clk_ade_core"); + if (!ctx->ade_core_clk) { + DRM_ERROR("failed to parse clk ADE_CORE\n"); + return -ENODEV; + } + + ctx->media_noc_clk = devm_clk_get(dev, "clk_codec_jpeg"); + if (!ctx->media_noc_clk) { + DRM_ERROR("failed to parse clk CODEC_JPEG\n"); + return -ENODEV; + } + + ctx->ade_pix_clk = devm_clk_get(dev, "clk_ade_pix"); + if (!ctx->ade_pix_clk) { + DRM_ERROR("failed to parse clk ADE_PIX\n"); + return -ENODEV; + } + + return 0; +} + +int ade_drm_init(struct drm_device *dev) +{ + struct platform_device *pdev = dev->platformdev; + struct ade_data *ade; + struct ade_hw_ctx *ctx; + struct ade_crtc *acrtc; + int ret; + + ade = devm_kzalloc(dev->dev, sizeof(*ade), GFP_KERNEL); + if (!ade) { + DRM_ERROR("failed to alloc ade_data\n"); + return -ENOMEM; + } + platform_set_drvdata(pdev, ade); + + ctx = &ade->ctx; + acrtc = &ade->acrtc; + acrtc->ctx = ctx; + acrtc->out_format = LDI_OUT_RGB_888; + + ret = ade_dts_parse(pdev, ctx); + if (ret) + return ret; + + return 0; +} + +void ade_drm_cleanup(struct drm_device *dev) +{ + struct platform_device *pdev = dev->platformdev; + struct ade_data *ade = platform_get_drvdata(pdev); + struct drm_crtc *crtc = &ade->acrtc.base; + + drm_crtc_cleanup(crtc); +} + +const struct kirin_dc_ops ade_dc_ops = { + .init = ade_drm_init, + .cleanup = ade_drm_cleanup +}; diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c index 789ebd1f5922..055729c1889c 100644 --- a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c +++ b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c @@ -30,8 +30,12 @@ static struct kirin_dc_ops *dc_ops;

static int kirin_drm_kms_cleanup(struct drm_device *dev) { + struct kirin_drm_private *priv = dev->dev_private; + dc_ops->cleanup(dev); drm_mode_config_cleanup(dev); + devm_kfree(dev->dev, priv); + dev->dev_private = NULL;

return 0; } @@ -55,8 +59,14 @@ static void kirin_drm_mode_config_init(struct drm_device *dev)

static int kirin_drm_kms_init(struct drm_device *dev) { + struct kirin_drm_private *priv; int ret;

+ priv = devm_kzalloc(dev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + dev->dev_private = priv; dev_set_drvdata(dev->dev, dev);

/* dev->mode_config initialization */ @@ -84,6 +94,8 @@ err_dc_cleanup: dc_ops->cleanup(dev); err_mode_config_cleanup: drm_mode_config_cleanup(dev); + devm_kfree(dev->dev, priv); + dev->dev_private = NULL;

return ret; } @@ -221,6 +233,9 @@ static const struct component_master_ops kirin_drm_ops = { };

static const struct of_device_id kirin_drm_dt_ids[] = { + { .compatible = "hisilicon,hi6220-ade", + .data = &ade_dc_ops, + }, { /* end node */ }, }; MODULE_DEVICE_TABLE(of, kirin_drm_dt_ids); diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h index 75e9d82356d4..5a05ad6a81db 100644 --- a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h +++ b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.h @@ -11,10 +11,18 @@ #ifndef __KIRIN_DRM_DRV_H__ #define __KIRIN_DRM_DRV_H__

+#define MAX_CRTC 2 + /* display controller init/cleanup ops */ struct kirin_dc_ops { int (*init)(struct drm_device *dev); void (*cleanup)(struct drm_device *dev); };

+struct kirin_drm_private { + struct drm_crtc *crtc[MAX_CRTC]; +}; + +extern const struct kirin_dc_ops ade_dc_ops; + #endif /* __KIRIN_DRM_DRV_H__ */

Add vblank irq handle.

v4: None. v3: - Remove hisi_get_crtc_from_index func. - A few cleanup. v2: - Remove abtraction layer.

Signed-off-by: Xinliang Liu xinliang.liu@linaro.org --- drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c | 62 +++++++++++++++++++++++++ drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c | 14 +++++- 2 files changed, 75 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c index ff70f1c3dd78..2a12e14ea6ab 100644 --- a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c +++ b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c @@ -295,6 +295,59 @@ static void ade_set_medianoc_qos(struct ade_crtc *acrtc) writel(val, reg); }

+static int ade_enable_vblank(struct drm_device *dev, unsigned int pipe) +{ + struct kirin_drm_private *priv = dev->dev_private; + struct ade_crtc *acrtc = to_ade_crtc(priv->crtc[pipe]); + struct ade_hw_ctx *ctx = acrtc->ctx; + void __iomem *base = ctx->base; + + if (!ctx->power_on) + (void)ade_power_up(ctx); + + ade_update_bits(base + LDI_INT_EN, FRAME_END_INT_EN_OFST, + MASK(1), 1); + + return 0; +} + +static void ade_disable_vblank(struct drm_device *dev, unsigned int pipe) +{ + struct kirin_drm_private *priv = dev->dev_private; + struct ade_crtc *acrtc = to_ade_crtc(priv->crtc[pipe]); + struct ade_hw_ctx *ctx = acrtc->ctx; + void __iomem *base = ctx->base; + + if (!ctx->power_on) { + DRM_ERROR("power is down! vblank disable fail\n"); + return; + } + + ade_update_bits(base + LDI_INT_EN, FRAME_END_INT_EN_OFST, + MASK(1), 0); +} + +static irqreturn_t ade_irq_handler(int irq, void *data) +{ + struct ade_crtc *acrtc = data; + struct ade_hw_ctx *ctx = acrtc->ctx; + struct drm_crtc *crtc = &acrtc->base; + void __iomem *base = ctx->base; + u32 status; + + status = readl(base + LDI_MSK_INT); + DRM_DEBUG_VBL("LDI IRQ: status=0x%X\n", status); + + /* vblank irq */ + if (status & BIT(FRAME_END_INT_EN_OFST)) { + ade_update_bits(base + LDI_INT_CLR, FRAME_END_INT_EN_OFST, + MASK(1), 1); + drm_crtc_handle_vblank(crtc); + } + + return IRQ_HANDLED; +} + static void ade_display_enable(struct ade_crtc *acrtc) { struct ade_hw_ctx *ctx = acrtc->ctx; @@ -973,6 +1026,15 @@ int ade_drm_init(struct drm_device *dev) if (ret) return ret;

+ /* vblank irq init */ + ret = devm_request_irq(dev->dev, ctx->irq, ade_irq_handler, + DRIVER_IRQ_SHARED, dev->driver->name, acrtc); + if (ret) + return ret; + dev->driver->get_vblank_counter = drm_vblank_no_hw_counter; + dev->driver->enable_vblank = ade_enable_vblank; + dev->driver->disable_vblank = ade_disable_vblank; + return 0; }

diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c index 055729c1889c..723888feb760 100644 --- a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c +++ b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_drv.c @@ -32,6 +32,7 @@ static int kirin_drm_kms_cleanup(struct drm_device *dev) { struct kirin_drm_private *priv = dev->dev_private;

+ drm_vblank_cleanup(dev); dc_ops->cleanup(dev); drm_mode_config_cleanup(dev); devm_kfree(dev->dev, priv); @@ -85,11 +86,22 @@ static int kirin_drm_kms_init(struct drm_device *dev) goto err_dc_cleanup; }

+ /* vblank init */ + ret = drm_vblank_init(dev, dev->mode_config.num_crtc); + if (ret) { + DRM_ERROR("failed to initialize vblank.\n"); + goto err_unbind_all; + } + /* with irq_enabled = true, we can use the vblank feature. */ + dev->irq_enabled = true; + /* reset all the states of crtc/plane/encoder/connector */ drm_mode_config_reset(dev);

return 0;

+err_unbind_all: + component_unbind_all(dev->dev, dev); err_dc_cleanup: dc_ops->cleanup(dev); err_mode_config_cleanup: @@ -123,7 +135,7 @@ static int kirin_gem_cma_dumb_create(struct drm_file *file,

static struct drm_driver kirin_drm_driver = { .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME | - DRIVER_ATOMIC, + DRIVER_ATOMIC | DRIVER_HAVE_IRQ, .fops = &kirin_drm_fops, .set_busid = drm_platform_set_busid,

Add DesignWare MIPI DSI Host Controller v1.02 encoder driver for hi6220 SoC.

v4: None. v3: - Rename file name to dw_drm_dsi.c - Make encoder type as DRM_MODE_ENCODER_DSI. - A few cleanup. v2: - Remove abtraction layer.

Signed-off-by: Xinliang Liu xinliang.liu@linaro.org Signed-off-by: Xinwei Kong kong.kongxinwei@hisilicon.com Signed-off-by: Andy Green andy.green@linaro.org --- drivers/gpu/drm/hisilicon/kirin/Kconfig | 1 + drivers/gpu/drm/hisilicon/kirin/Makefile | 3 +- drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c | 743 +++++++++++++++++++++++++++ drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h | 83 +++ 4 files changed, 829 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c create mode 100644 drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h

diff --git a/drivers/gpu/drm/hisilicon/kirin/Kconfig b/drivers/gpu/drm/hisilicon/kirin/Kconfig index 3ac4b8edeac1..de0d454c5c13 100644 --- a/drivers/gpu/drm/hisilicon/kirin/Kconfig +++ b/drivers/gpu/drm/hisilicon/kirin/Kconfig @@ -4,6 +4,7 @@ config DRM_HISI_KIRIN select DRM_KMS_HELPER select DRM_GEM_CMA_HELPER select DRM_KMS_CMA_HELPER + select DRM_MIPI_DSI help Choose this option if you have a hisilicon Kirin chipsets(hi6220). If M is selected the module will be called kirin-drm. diff --git a/drivers/gpu/drm/hisilicon/kirin/Makefile b/drivers/gpu/drm/hisilicon/kirin/Makefile index 2a61ab006ddb..5dcd0d4328b6 100644 --- a/drivers/gpu/drm/hisilicon/kirin/Makefile +++ b/drivers/gpu/drm/hisilicon/kirin/Makefile @@ -1,4 +1,5 @@ kirin-drm-y := kirin_drm_drv.o \ - kirin_drm_ade.o + kirin_drm_ade.o \ + dw_drm_dsi.o

obj-$(CONFIG_DRM_HISI_KIRIN) += kirin-drm.o diff --git a/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c new file mode 100644 index 000000000000..7c9423537b71 --- /dev/null +++ b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c @@ -0,0 +1,743 @@ +/* + * DesignWare MIPI DSI Host Controller v1.02 driver + * + * Copyright (c) 2016 Linaro Limited. + * Copyright (c) 2014-2016 Hisilicon Limited. + * + * Author: + * Xinliang Liu z.liuxinliang@hisilicon.com + * Xinliang Liu xinliang.liu@linaro.org + * Xinwei Kong kong.kongxinwei@hisilicon.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <linux/clk.h> +#include <linux/component.h> +#include <linux/of_graph.h> + +#include <drm/drm_of.h> +#include <drm/drm_crtc_helper.h> +#include <drm/drm_mipi_dsi.h> +#include <drm/drm_encoder_slave.h> +#include <drm/drm_atomic_helper.h> + +#include "dw_dsi_reg.h" + +#define MAX_TX_ESC_CLK (10) +#define ROUND(x, y) ((x) / (y) + ((x) % (y) * 10 / (y) >= 5 ? 1 : 0)) +#define PHY_REF_CLK_RATE 19200000 +#define PHY_REF_CLK_PERIOD_PS (1000000000 / (PHY_REF_CLK_RATE / 1000)) + +#define encoder_to_dsi(encoder) \ + container_of(encoder, struct dw_dsi, encoder) +#define host_to_dsi(host) \ + container_of(host, struct dw_dsi, host) + +struct mipi_phy_params { + u32 clk_t_lpx; + u32 clk_t_hs_prepare; + u32 clk_t_hs_zero; + u32 clk_t_hs_trial; + u32 clk_t_wakeup; + u32 data_t_lpx; + u32 data_t_hs_prepare; + u32 data_t_hs_zero; + u32 data_t_hs_trial; + u32 data_t_ta_go; + u32 data_t_ta_get; + u32 data_t_wakeup; + u32 hstx_ckg_sel; + u32 pll_fbd_div5f; + u32 pll_fbd_div1f; + u32 pll_fbd_2p; + u32 pll_enbwt; + u32 pll_fbd_p; + u32 pll_fbd_s; + u32 pll_pre_div1p; + u32 pll_pre_p; + u32 pll_vco_750M; + u32 pll_lpf_rs; + u32 pll_lpf_cs; + u32 clklp2hs_time; + u32 clkhs2lp_time; + u32 lp2hs_time; + u32 hs2lp_time; + u32 clk_to_data_delay; + u32 data_to_clk_delay; + u32 lane_byte_clk_kHz; + u32 clk_division; +}; + +struct dsi_hw_ctx { + void __iomem *base; + struct clk *dsi_cfg_clk; +}; + +struct dw_dsi { + struct drm_encoder encoder; + struct drm_display_mode cur_mode; + struct dsi_hw_ctx *ctx; + struct mipi_phy_params phy; + + u32 lanes; + enum mipi_dsi_pixel_format format; + unsigned long mode_flags; + bool enable; +}; + +struct dsi_data { + struct dw_dsi dsi; + struct dsi_hw_ctx ctx; +}; + +struct dsi_phy_range { + u32 min_range_kHz; + u32 max_range_kHz; + u32 pll_vco_750M; + u32 hstx_ckg_sel; +}; + +static const struct dsi_phy_range dphy_range_info[] = { + { 46875, 62500, 1, 7 }, + { 62500, 93750, 0, 7 }, + { 93750, 125000, 1, 6 }, + { 125000, 187500, 0, 6 }, + { 187500, 250000, 1, 5 }, + { 250000, 375000, 0, 5 }, + { 375000, 500000, 1, 4 }, + { 500000, 750000, 0, 4 }, + { 750000, 1000000, 1, 0 }, + { 1000000, 1500000, 0, 0 } +}; + +static void dsi_get_phy_params(u32 phy_freq_kHz, + struct mipi_phy_params *phy) +{ + u32 ui = 0; + u32 cfg_clk_ps = PHY_REF_CLK_PERIOD_PS; + u32 i = 0; + u32 q_pll = 1; + u32 m_pll = 0; + u32 n_pll = 0; + u32 r_pll = 1; + u32 m_n = 0; + u32 m_n_int = 0; + u64 f_kHz; + u64 temp; + u64 tmp_kHz = phy_freq_kHz; + + do { + f_kHz = tmp_kHz; + + /* Find the PLL clock range from the table */ + for (i = 0; i < ARRAY_SIZE(dphy_range_info); i++) + if (f_kHz >= dphy_range_info[i].min_range_kHz && + f_kHz <= dphy_range_info[i].max_range_kHz) + break; + + if (i == ARRAY_SIZE(dphy_range_info)) { + DRM_ERROR("%lldkHz out of range\n", f_kHz); + return; + } + + phy->pll_vco_750M = dphy_range_info[i].pll_vco_750M; + phy->hstx_ckg_sel = dphy_range_info[i].hstx_ckg_sel; + + if (phy->hstx_ckg_sel <= 7 && + phy->hstx_ckg_sel >= 4) + q_pll = 0x10 >> (7 - phy->hstx_ckg_sel); + + temp = f_kHz * (u64)q_pll * (u64)cfg_clk_ps; + m_n_int = temp / (u64)1000000000; + m_n = (temp % (u64)1000000000) / (u64)100000000; + + if (m_n_int % 2 == 0) { + if (m_n * 6 >= 50) { + n_pll = 2; + m_pll = (m_n_int + 1) * n_pll; + } else if (m_n * 6 >= 30) { + n_pll = 3; + m_pll = m_n_int * n_pll + 2; + } else { + n_pll = 1; + m_pll = m_n_int * n_pll; + } + } else { + if (m_n * 6 >= 50) { + n_pll = 1; + m_pll = (m_n_int + 1) * n_pll; + } else if (m_n * 6 >= 30) { + n_pll = 1; + m_pll = (m_n_int + 1) * n_pll; + } else if (m_n * 6 >= 10) { + n_pll = 3; + m_pll = m_n_int * n_pll + 1; + } else { + n_pll = 2; + m_pll = m_n_int * n_pll; + } + } + + if (n_pll == 1) { + phy->pll_fbd_p = 0; + phy->pll_pre_div1p = 1; + } else { + phy->pll_fbd_p = n_pll; + phy->pll_pre_div1p = 0; + } + + if (phy->pll_fbd_2p <= 7 && phy->pll_fbd_2p >= 4) + r_pll = 0x10 >> (7 - phy->pll_fbd_2p); + + if (m_pll == 2) { + phy->pll_pre_p = 0; + phy->pll_fbd_s = 0; + phy->pll_fbd_div1f = 0; + phy->pll_fbd_div5f = 1; + } else if (m_pll >= 2 * 2 * r_pll && m_pll <= 2 * 4 * r_pll) { + phy->pll_pre_p = m_pll / (2 * r_pll); + phy->pll_fbd_s = 0; + phy->pll_fbd_div1f = 1; + phy->pll_fbd_div5f = 0; + } else if (m_pll >= 2 * 5 * r_pll && m_pll <= 2 * 150 * r_pll) { + if (((m_pll / (2 * r_pll)) % 2) == 0) { + phy->pll_pre_p = + (m_pll / (2 * r_pll)) / 2 - 1; + phy->pll_fbd_s = + (m_pll / (2 * r_pll)) % 2 + 2; + } else { + phy->pll_pre_p = + (m_pll / (2 * r_pll)) / 2; + phy->pll_fbd_s = + (m_pll / (2 * r_pll)) % 2; + } + phy->pll_fbd_div1f = 0; + phy->pll_fbd_div5f = 0; + } else { + phy->pll_pre_p = 0; + phy->pll_fbd_s = 0; + phy->pll_fbd_div1f = 0; + phy->pll_fbd_div5f = 1; + } + + f_kHz = (u64)1000000000 * (u64)m_pll / + ((u64)cfg_clk_ps * (u64)n_pll * (u64)q_pll); + + if (f_kHz >= phy_freq_kHz) + break; + + tmp_kHz += 10; + + } while (1); + + ui = 1000000 / f_kHz; + + phy->clk_t_lpx = ROUND(50, 8 * ui); + phy->clk_t_hs_prepare = ROUND(133, 16 * ui) - 1; + + phy->clk_t_hs_zero = ROUND(262, 8 * ui); + phy->clk_t_hs_trial = 2 * (ROUND(60, 8 * ui) - 1); + phy->clk_t_wakeup = ROUND(1000000, (cfg_clk_ps / 1000) - 1); + if (phy->clk_t_wakeup > 0xff) + phy->clk_t_wakeup = 0xff; + phy->data_t_wakeup = phy->clk_t_wakeup; + phy->data_t_lpx = phy->clk_t_lpx; + phy->data_t_hs_prepare = ROUND(125 + 10 * ui, 16 * ui) - 1; + phy->data_t_hs_zero = ROUND(105 + 6 * ui, 8 * ui); + phy->data_t_hs_trial = 2 * (ROUND(60 + 4 * ui, 8 * ui) - 1); + phy->data_t_ta_go = 3; + phy->data_t_ta_get = 4; + + phy->pll_enbwt = 1; + phy->clklp2hs_time = ROUND(407, 8 * ui) + 12; + phy->clkhs2lp_time = ROUND(105 + 12 * ui, 8 * ui); + phy->lp2hs_time = ROUND(240 + 12 * ui, 8 * ui) + 1; + phy->hs2lp_time = phy->clkhs2lp_time; + phy->clk_to_data_delay = 1 + phy->clklp2hs_time; + phy->data_to_clk_delay = ROUND(60 + 52 * ui, 8 * ui) + + phy->clkhs2lp_time; + + phy->lane_byte_clk_kHz = f_kHz / 8; + phy->clk_division = phy->lane_byte_clk_kHz / MAX_TX_ESC_CLK; + if (phy->lane_byte_clk_kHz % MAX_TX_ESC_CLK) + phy->clk_division++; +} + +static u32 dsi_get_dpi_color_coding(enum mipi_dsi_pixel_format format) +{ + u32 val; + + /* TODO: only support RGB888 now, to support more */ + switch (format) { + case MIPI_DSI_FMT_RGB888: + val = DSI_24BITS_1; + break; + default: + val = DSI_24BITS_1; + break; + } + + return val; +} + +/* + * dsi phy reg write function + */ +static void dsi_phy_tst_set(void __iomem *base, u32 reg, u32 val) +{ + writel(reg, base + PHY_TST_CTRL1); + /* reg addr written at first */ + wmb(); + writel(0x02, base + PHY_TST_CTRL0); + /* cmd1 sent for write */ + wmb(); + writel(0x00, base + PHY_TST_CTRL0); + /* cmd2 sent for write */ + wmb(); + writel(val, base + PHY_TST_CTRL1); + /* Then write data */ + wmb(); + writel(0x02, base + PHY_TST_CTRL0); + /* cmd2 sent for write */ + wmb(); + writel(0x00, base + PHY_TST_CTRL0); +} + +static void dsi_set_mipi_phy(void __iomem *base, + struct mipi_phy_params *phy, + u32 lanes) +{ + u32 delay_count; + u32 val; + u32 i; + + /* set lanes value */ + val = (lanes - 1) | (PHY_STOP_WAIT_TIME << 8); + writel(val, base + PHY_IF_CFG); + + /* set phy clk division */ + val = readl(base + CLKMGR_CFG) | phy->clk_division; + writel(val, base + CLKMGR_CFG); + + /* clean up phy set param */ + writel(0, base + PHY_RSTZ); + writel(0, base + PHY_TST_CTRL0); + writel(1, base + PHY_TST_CTRL0); + writel(0, base + PHY_TST_CTRL0); + + /* clock lane Timing control - TLPX */ + dsi_phy_tst_set(base, 0x10010, phy->clk_t_lpx); + + /* clock lane Timing control - THS-PREPARE */ + dsi_phy_tst_set(base, 0x10011, phy->clk_t_hs_prepare); + + /* clock lane Timing control - THS-ZERO */ + dsi_phy_tst_set(base, 0x10012, phy->clk_t_hs_zero); + + /* clock lane Timing control - THS-TRAIL */ + dsi_phy_tst_set(base, 0x10013, phy->clk_t_hs_trial); + + /* clock lane Timing control - TWAKEUP */ + dsi_phy_tst_set(base, 0x10014, phy->clk_t_wakeup); + + /* data lane */ + for (i = 0; i < lanes; i++) { + /* Timing control - TLPX */ + dsi_phy_tst_set(base, 0x10020 + (i << 4), phy->data_t_lpx); + + /* Timing control - THS-PREPARE */ + dsi_phy_tst_set(base, 0x10021 + (i << 4), + phy->data_t_hs_prepare); + + /* Timing control - THS-ZERO */ + dsi_phy_tst_set(base, 0x10022 + (i << 4), phy->data_t_hs_zero); + + /* Timing control - THS-TRAIL */ + dsi_phy_tst_set(base, 0x10023 + (i << 4), phy->data_t_hs_trial); + + /* Timing control - TTA-GO */ + dsi_phy_tst_set(base, 0x10024 + (i << 4), phy->data_t_ta_go); + + /* Timing control - TTA-GET */ + dsi_phy_tst_set(base, 0x10025 + (i << 4), phy->data_t_ta_get); + + /* Timing control - TWAKEUP */ + dsi_phy_tst_set(base, 0x10026 + (i << 4), phy->data_t_wakeup); + } + + /* physical configuration I */ + dsi_phy_tst_set(base, 0x10060, phy->hstx_ckg_sel); + + /* physical configuration pll II */ + val = (phy->pll_fbd_div5f << 5) + (phy->pll_fbd_div1f << 4) + + (phy->pll_fbd_2p << 1) + phy->pll_enbwt; + dsi_phy_tst_set(base, 0x10063, val); + + /* physical configuration pll II */ + dsi_phy_tst_set(base, 0x10064, phy->pll_fbd_p); + + /* physical configuration pll III */ + dsi_phy_tst_set(base, 0x10065, phy->pll_fbd_s); + + /* physical configuration pll IV */ + val = (phy->pll_pre_div1p << 7) + phy->pll_pre_p; + dsi_phy_tst_set(base, 0x10066, val); + + /* physical configuration pll V */ + val = (phy->pll_vco_750M << 4) + (phy->pll_lpf_rs << 2) + + phy->pll_lpf_cs + BIT(5); + dsi_phy_tst_set(base, 0x10067, val); + + writel(BIT(2), base + PHY_RSTZ); + udelay(1); + writel(BIT(2) | BIT(0), base + PHY_RSTZ); + udelay(1); + writel(BIT(2) | BIT(1) | BIT(0), base + PHY_RSTZ); + usleep_range(1000, 1500); + + /* wait for phy's clock ready */ + delay_count = 100; + while (delay_count--) { + val = readl(base + PHY_STATUS); + if ((BIT(0) | BIT(2)) & val) + break; + + udelay(1); + } + + if (!delay_count) + DRM_INFO("phylock and phystopstateclklane is not ready.\n"); + + /* set lp and hs switching params + */ + dw_update_bits(base + PHY_TMR_CFG, 24, MASK(8), phy->hs2lp_time); + dw_update_bits(base + PHY_TMR_CFG, 16, MASK(8), phy->lp2hs_time); + dw_update_bits(base + PHY_TMR_LPCLK_CFG, 16, MASK(10), + phy->clkhs2lp_time); + dw_update_bits(base + PHY_TMR_LPCLK_CFG, 0, MASK(10), + phy->clklp2hs_time); + dw_update_bits(base + CLK_DATA_TMR_CFG, 8, MASK(8), + phy->data_to_clk_delay); + dw_update_bits(base + CLK_DATA_TMR_CFG, 0, MASK(8), + phy->clk_to_data_delay); +} + +static void dsi_set_mode_timing(void __iomem *base, + u32 lane_byte_clk_kHz, + struct drm_display_mode *mode, + enum mipi_dsi_pixel_format format) +{ + u32 hfp, hbp, hsw, vfp, vbp, vsw; + u32 hline_time; + u32 hsa_time; + u32 hbp_time; + u32 pixel_clk_kHz; + int htot, vtot; + u32 val; + u64 tmp; + + /* DSI color coding setting */ + val = dsi_get_dpi_color_coding(format); + writel(val, base + DPI_COLOR_CODING); + + /* DSI format and pol setting */ + val = (mode->flags & DRM_MODE_FLAG_NHSYNC ? 1 : 0) << 2; + val |= (mode->flags & DRM_MODE_FLAG_NVSYNC ? 1 : 0) << 1; + writel(val, base + DPI_CFG_POL); + + /* + * The DSI IP accepts vertical timing using lines as normal, + * but horizontal timing is a mixture of pixel-clocks for the + * active region and byte-lane clocks for the blanking-related + * timings. hfp is specified as the total hline_time in byte- + * lane clocks minus hsa, hbp and active. + */ + pixel_clk_kHz = mode->clock; + htot = mode->htotal; + vtot = mode->vtotal; + hfp = mode->hsync_start - mode->hdisplay; + hbp = mode->htotal - mode->hsync_end; + hsw = mode->hsync_end - mode->hsync_start; + vfp = mode->vsync_start - mode->vdisplay; + vbp = mode->vtotal - mode->vsync_end; + vsw = mode->vsync_end - mode->vsync_start; + if (vsw > 15) { + DRM_DEBUG_DRIVER("vsw exceeded 15\n"); + vsw = 15; + } + + hsa_time = (hsw * lane_byte_clk_kHz) / pixel_clk_kHz; + hbp_time = (hbp * lane_byte_clk_kHz) / pixel_clk_kHz; + tmp = (u64)htot * (u64)lane_byte_clk_kHz; + hline_time = DIV_ROUND_UP(tmp, pixel_clk_kHz); + + /* all specified in byte-lane clocks */ + writel(hsa_time, base + VID_HSA_TIME); + writel(hbp_time, base + VID_HBP_TIME); + writel(hline_time, base + VID_HLINE_TIME); + + writel(vsw, base + VID_VSA_LINES); + writel(vbp, base + VID_VBP_LINES); + writel(vfp, base + VID_VFP_LINES); + writel(mode->vdisplay, base + VID_VACTIVE_LINES); + writel(mode->hdisplay, base + VID_PKT_SIZE); + + DRM_DEBUG_DRIVER("htot=%d, hfp=%d, hbp=%d, hsw=%d\n", + htot, hfp, hbp, hsw); + DRM_DEBUG_DRIVER("vtol=%d, vfp=%d, vbp=%d, vsw=%d\n", + vtot, vfp, vbp, vsw); + DRM_DEBUG_DRIVER("hsa_time=%d, hbp_time=%d, hline_time=%d\n", + hsa_time, hbp_time, hline_time); +} + +static void dsi_set_video_mode_type(void __iomem *base, + unsigned long flags) +{ + u32 val; + u32 mode_mask = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_VIDEO_SYNC_PULSE; + u32 non_burst_sync_pulse = MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_SYNC_PULSE; + u32 non_burst_sync_event = MIPI_DSI_MODE_VIDEO; + + /* + * choose video type + */ + if ((flags & mode_mask) == non_burst_sync_pulse) + val = DSI_NON_BURST_SYNC_PULSES; + else if ((flags & mode_mask) == non_burst_sync_event) + val = DSI_NON_BURST_SYNC_EVENTS; + else + val = DSI_BURST_SYNC_PULSES_1; + + writel(val, base + VID_MODE_CFG); +} + +static void dsi_mipi_init(struct dw_dsi *dsi) +{ + struct dsi_hw_ctx *ctx = dsi->ctx; + struct mipi_phy_params *phy = &dsi->phy; + struct drm_display_mode *mode = &dsi->cur_mode; + u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); + void __iomem *base = ctx->base; + u32 dphy_freq_kHz; + + /* count phy params */ + dphy_freq_kHz = mode->clock * bpp / dsi->lanes; + dsi_get_phy_params(dphy_freq_kHz, phy); + + /* reset Core */ + writel(0, base + PWR_UP); + + /* set phy params */ + dsi_set_mipi_phy(base, phy, dsi->lanes); + + /* set dsi mode */ + dsi_set_mode_timing(base, phy->lane_byte_clk_kHz, mode, dsi->format); + + /* set video mode type and lp */ + dsi_set_video_mode_type(base, dsi->mode_flags); + + /* dsi wake up */ + writel(DSI_VIDEO_MODE, base + MODE_CFG); + writel(BIT(0), base + LPCLK_CTRL); + writel(BIT(0), base + PWR_UP); + + DRM_DEBUG_DRIVER("lanes=%d, pixel_clk=%d kHz, bytes_freq=%d kHz\n", + dsi->lanes, mode->clock, phy->lane_byte_clk_kHz); +} + +static void dsi_encoder_disable(struct drm_encoder *encoder) +{ + struct dw_dsi *dsi = encoder_to_dsi(encoder); + struct dsi_hw_ctx *ctx = dsi->ctx; + void __iomem *base = ctx->base; + + if (!dsi->enable) + return; + + writel(0, base + PWR_UP); + writel(0, base + LPCLK_CTRL); + writel(0, base + PHY_RSTZ); + clk_disable_unprepare(ctx->dsi_cfg_clk); + + dsi->enable = false; +} + +static void dsi_encoder_enable(struct drm_encoder *encoder) +{ + struct dw_dsi *dsi = encoder_to_dsi(encoder); + struct dsi_hw_ctx *ctx = dsi->ctx; + int ret; + + if (dsi->enable) + return; + + /* mipi dphy clock enable */ + ret = clk_prepare_enable(ctx->dsi_cfg_clk); + if (ret) { + DRM_ERROR("fail to enable dsi_cfg_clk: %d\n", ret); + return; + } + + dsi_mipi_init(dsi); + + dsi->enable = true; +} + +static void dsi_encoder_mode_set(struct drm_encoder *encoder, + struct drm_display_mode *mode, + struct drm_display_mode *adj_mode) +{ + struct dw_dsi *dsi = encoder_to_dsi(encoder); + + drm_mode_copy(&dsi->cur_mode, adj_mode); +} + +static int dsi_encoder_atomic_check(struct drm_encoder *encoder, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + /* do nothing */ + return 0; +} + +static const struct drm_encoder_helper_funcs dw_encoder_helper_funcs = { + .atomic_check = dsi_encoder_atomic_check, + .mode_set = dsi_encoder_mode_set, + .enable = dsi_encoder_enable, + .disable = dsi_encoder_disable +}; + +static const struct drm_encoder_funcs dw_encoder_funcs = { + .destroy = drm_encoder_cleanup, +}; + +static int dw_drm_encoder_init(struct device *dev, + struct drm_device *drm_dev, + struct drm_encoder *encoder) +{ + int ret; + u32 crtc_mask = drm_of_find_possible_crtcs(drm_dev, dev->of_node); + + if (!crtc_mask) { + DRM_ERROR("failed to find crtc mask\n"); + return -EINVAL; + } + + encoder->possible_crtcs = crtc_mask; + ret = drm_encoder_init(drm_dev, encoder, &dw_encoder_funcs, + DRM_MODE_ENCODER_DSI, NULL); + if (ret) { + DRM_ERROR("failed to init dsi encoder\n"); + return ret; + } + + drm_encoder_helper_add(encoder, &dw_encoder_helper_funcs); + + return 0; +} + +static int dsi_bind(struct device *dev, struct device *master, void *data) +{ + struct dsi_data *ddata = dev_get_drvdata(dev); + struct dw_dsi *dsi = &ddata->dsi; + struct drm_device *drm_dev = data; + int ret; + + ret = dw_drm_encoder_init(dev, drm_dev, &dsi->encoder); + if (ret) + return ret; + + return 0; +} + +static void dsi_unbind(struct device *dev, struct device *master, void *data) +{ + /* do nothing */ +} + +static const struct component_ops dsi_ops = { + .bind = dsi_bind, + .unbind = dsi_unbind, +}; + +static int dsi_parse_dt(struct platform_device *pdev, struct dw_dsi *dsi) +{ + struct dsi_hw_ctx *ctx = dsi->ctx; + struct resource *res; + + ctx->dsi_cfg_clk = devm_clk_get(&pdev->dev, "pclk_dsi"); + if (IS_ERR(ctx->dsi_cfg_clk)) { + DRM_ERROR("failed to get dsi plck clock\n"); + return PTR_ERR(ctx->dsi_cfg_clk); + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + ctx->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(ctx->base)) { + DRM_ERROR("failed to remap dsi io region\n"); + return PTR_ERR(ctx->base); + } + + return 0; +} + +static int dsi_probe(struct platform_device *pdev) +{ + struct dsi_data *data; + struct dw_dsi *dsi; + struct dsi_hw_ctx *ctx; + int ret; + + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) { + DRM_ERROR("failed to allocate dsi data.\n"); + return -ENOMEM; + } + dsi = &data->dsi; + ctx = &data->ctx; + dsi->ctx = ctx; + + ret = dsi_parse_dt(pdev, dsi); + if (ret) + return ret; + + platform_set_drvdata(pdev, data); + + return component_add(&pdev->dev, &dsi_ops); +} + +static int dsi_remove(struct platform_device *pdev) +{ + component_del(&pdev->dev, &dsi_ops); + + return 0; +} + +static const struct of_device_id dsi_of_match[] = { + {.compatible = "hisilicon,hi6220-dsi"}, + { } +}; +MODULE_DEVICE_TABLE(of, dsi_of_match); + +static struct platform_driver dsi_driver = { + .probe = dsi_probe, + .remove = dsi_remove, + .driver = { + .name = "dw-dsi", + .of_match_table = dsi_of_match, + }, +}; + +module_platform_driver(dsi_driver); + +MODULE_AUTHOR("Xinliang Liu xinliang.liu@linaro.org"); +MODULE_AUTHOR("Xinliang Liu z.liuxinliang@hisilicon.com"); +MODULE_AUTHOR("Xinwei Kong kong.kongxinwei@hisilicon.com"); +MODULE_DESCRIPTION("DesignWare MIPI DSI Host Controller v1.02 driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h b/drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h new file mode 100644 index 000000000000..d3d44b7d2098 --- /dev/null +++ b/drivers/gpu/drm/hisilicon/kirin/dw_dsi_reg.h @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2016 Linaro Limited. + * Copyright (c) 2014-2016 Hisilicon Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DW_DSI_REG_H__ +#define __DW_DSI_REG_H__ + +#define MASK(x) (BIT(x) - 1) + +/* + * regs + */ +#define PWR_UP 0x04 /* Core power-up */ +#define PHY_IF_CFG 0xA4 /* D-PHY interface configuration */ +#define CLKMGR_CFG 0x08 /* the internal clock dividers */ +#define PHY_RSTZ 0xA0 /* D-PHY reset control */ +#define PHY_TST_CTRL0 0xB4 /* D-PHY test interface control 0 */ +#define PHY_TST_CTRL1 0xB8 /* D-PHY test interface control 1 */ +#define DPI_VCID 0x0C /* DPI virtual channel id */ +#define DPI_COLOR_CODING 0x10 /* DPI color coding */ +#define DPI_CFG_POL 0x14 /* DPI polarity configuration */ +#define VID_HSA_TIME 0x48 /* Horizontal Sync Active time */ +#define VID_HBP_TIME 0x4C /* Horizontal Back Porch time */ +#define VID_HLINE_TIME 0x50 /* Line time */ +#define VID_VSA_LINES 0x54 /* Vertical Sync Active period */ +#define VID_VBP_LINES 0x58 /* Vertical Back Porch period */ +#define VID_VFP_LINES 0x5C /* Vertical Front Porch period */ +#define VID_VACTIVE_LINES 0x60 /* Vertical resolution */ +#define VID_PKT_SIZE 0x3C /* Video packet size */ +#define VID_MODE_CFG 0x38 /* Video mode configuration */ +#define DPI_LP_CMD_TIM 0x18 /* Low-power command timing config */ +#define PHY_TMR_CFG 0x9C /* Data lanes timing configuration */ +#define BTA_TO_CNT 0x8C /* Response timeout definition */ +#define PHY_TMR_LPCLK_CFG 0x98 /* clock lane timing configuration */ +#define CLK_DATA_TMR_CFG 0xCC +#define LPCLK_CTRL 0x94 /* Low-power in clock lane */ +#define PCKHDL_CFG 0x2C /* Packet handler configuration */ +#define EDPI_CMD_SIZE 0x64 /* Size for eDPI packets */ +#define MODE_CFG 0x34 /* Video or Command mode selection */ +#define PHY_STATUS 0xB0 /* D-PHY PPI status interface */ + +#define PHY_STOP_WAIT_TIME 0x30 + +/* + * regs relevant enum + */ +enum dpi_color_coding { + DSI_24BITS_1 = 5, +}; + +enum dsi_video_mode_type { + DSI_NON_BURST_SYNC_PULSES = 0, + DSI_NON_BURST_SYNC_EVENTS, + DSI_BURST_SYNC_PULSES_1, + DSI_BURST_SYNC_PULSES_2 +}; + +enum dsi_work_mode { + DSI_VIDEO_MODE = 0, + DSI_COMMAND_MODE +}; + +/* + * Register Write/Read Helper functions + */ +static inline void dw_update_bits(void __iomem *addr, u32 bit_start, + u32 mask, u32 val) +{ + u32 tmp, orig; + + orig = readl(addr); + tmp = orig & ~(mask << bit_start); + tmp |= (val & mask) << bit_start; + writel(tmp, addr); +} + +#endif /* __DW_DRM_DSI_H__ */

Add support for external HDMI bridge.

v4: None. v3: - Fix a typo: s/exteranl/external. v2: - Remove abtraction layer.

Signed-off-by: Xinliang Liu xinliang.liu@linaro.org --- drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c | 52 ++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+)

diff --git a/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c index 2837af01e935..1342d84d7c68 100644 --- a/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c +++ b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c @@ -79,6 +79,7 @@ struct dsi_hw_ctx {

struct dw_dsi { struct drm_encoder encoder; + struct drm_bridge *bridge; struct mipi_dsi_host host; struct drm_display_mode cur_mode; struct dsi_hw_ctx *ctx; @@ -688,6 +689,25 @@ static int dsi_host_init(struct device *dev, struct dw_dsi *dsi) return 0; }

+static int dsi_bridge_init(struct drm_device *dev, struct dw_dsi *dsi) +{ + struct drm_encoder *encoder = &dsi->encoder; + struct drm_bridge *bridge = dsi->bridge; + int ret; + + /* associate the bridge to dsi encoder */ + encoder->bridge = bridge; + bridge->encoder = encoder; + + ret = drm_bridge_attach(dev, bridge); + if (ret) { + DRM_ERROR("failed to attach external bridge\n"); + return ret; + } + + return 0; +} + static int dsi_bind(struct device *dev, struct device *master, void *data) { struct dsi_data *ddata = dev_get_drvdata(dev); @@ -703,6 +723,10 @@ static int dsi_bind(struct device *dev, struct device *master, void *data) if (ret) return ret;

+ ret = dsi_bridge_init(drm_dev, dsi); + if (ret) + return ret; + return 0; }

@@ -719,8 +743,36 @@ static const struct component_ops dsi_ops = { static int dsi_parse_dt(struct platform_device *pdev, struct dw_dsi *dsi) { struct dsi_hw_ctx *ctx = dsi->ctx; + struct device_node *np = pdev->dev.of_node; + struct device_node *endpoint, *bridge_node; + struct drm_bridge *bridge; struct resource *res;

+ /* + * Get the endpoint node. In our case, dsi has one output port1 + * to which the external HDMI bridge is connected. + */ + endpoint = of_graph_get_endpoint_by_regs(np, 1, -1); + if (!endpoint) { + DRM_ERROR("no valid endpoint node\n"); + return -ENODEV; + } + of_node_put(endpoint); + + bridge_node = of_graph_get_remote_port_parent(endpoint); + if (!bridge_node) { + DRM_ERROR("no valid bridge node\n"); + return -ENODEV; + } + of_node_put(bridge_node); + + bridge = of_drm_find_bridge(bridge_node); + if (!bridge) { + DRM_INFO("wait for external HDMI bridge driver.\n"); + return -EPROBE_DEFER; + } + dsi->bridge = bridge; + ctx->dsi_cfg_clk = devm_clk_get(&pdev->dev, "pclk_dsi"); if (IS_ERR(ctx->dsi_cfg_clk)) { DRM_ERROR("failed to get dsi plck clock\n");

Add ade, dsi and adv7533 DT nodes for hikey board.

Signed-off-by: Xinliang Liu xinliang.liu@linaro.org --- arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts | 44 +++++++++++++++++++++ arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 53 ++++++++++++++++++++++++++ 2 files changed, 97 insertions(+)

diff --git a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts index 818525197508..5c3557c8e59b 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts +++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts @@ -39,3 +39,47 @@ &uart3 { label = "LS-UART1"; }; + +&ade { + status = "okay"; +}; + +&dsi { + status = "ok"; + + ports { + /* 1 for output port */ + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + /* 0 for bridge, other value for panel */ + dsi_out0: endpoint@0 { + reg = <0>; + remote-endpoint = <&adv7533_in>; + }; + }; + }; +}; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + status = "ok"; + + adv7533: adv7533@39 { + compatible = "adi,adv7533"; + reg = <0x39>; + interrupt-parent = <&gpio1>; + interrupts = <1 2>; + pd-gpio = <&gpio0 4 0>; + adi,dsi-lanes = <4>; + + port { + adv7533_in: endpoint { + remote-endpoint = <&dsi_out0>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index ad1f1ebcb05c..e50e81cdd242 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -209,5 +209,58 @@ clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; + + ade: ade@f4100000 { + compatible = "hisilicon,hi6220-ade"; + reg = <0x0 0xf4100000 0x0 0x7800>, + <0x0 0xf4410000 0x0 0x1000>, + <0x0 0xf4520000 0x0 0x1000>; + reg-names = "ade_base", + "media_base", + "media_noc_base"; + + interrupts = <0 115 4>; /* ldi interrupt */ + + clocks = <&media_ctrl HI6220_ADE_CORE>, + <&media_ctrl HI6220_CODEC_JPEG>, + <&media_ctrl HI6220_ADE_PIX_SRC>; + /*clock name*/ + clock-names = "clk_ade_core", + "clk_codec_jpeg", + "clk_ade_pix"; + + assigned-clocks = <&media_ctrl HI6220_ADE_CORE>, + <&media_ctrl HI6220_CODEC_JPEG>; + assigned-clock-rates = <360000000>, <288000000>; + dma-coherent; + status = "disabled"; + + port { + ade_out: endpoint { + remote-endpoint = <&dsi_in>; + }; + }; + }; + + dsi: dsi@f4107800 { + compatible = "hisilicon,hi6220-dsi"; + reg = <0x0 0xf4107800 0x0 0x100>; + clocks = <&media_ctrl HI6220_DSI_PCLK>; + clock-names = "pclk_dsi"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* 0 for input port */ + port@0 { + reg = <0>; + dsi_in: endpoint { + remote-endpoint = <&ade_out>; + }; + }; + }; + }; }; };