Add DT nodes for the sdm845 GPU/GMU (graphics management unit) and the companion arm-smmu-v2 compatible SMMU.
This builds on the following dependencies - https://patchwork.kernel.org/patch/10286369/ - bindings for qcom,level https://patchwork.kernel.org/patch/10281599/ - qcom,smmu-v2 bindings
And requires these two changes for the driver:
https://patchwork.freedesktop.org/patch/243512/ - use new PDC sections https://patchwork.freedesktop.org/patch/243513/ - use qcom,gmu instead of gmu
I think we are still waiting for the dependencies to merge but this should at least be usable for anybody with a target that wants to get the GPU up and happy.
[v3 - Split GMU PDC region into two GPU specific sections, fix indentation, really use qcom,gmu for the phandle name] [v2 - changed qcom,arc-level to qcom,level following discussion with Viresh; change gmu phandle to qcom,gmu per Rob]
Jordan Crouse (2): dt-bindings: Document qcom,adreno-gmu arm64: dts: sdm845: Add gpu and gmu device nodes
.../devicetree/bindings/display/msm/gmu.txt | 54 ++++++++ .../devicetree/bindings/display/msm/gpu.txt | 10 +- arch/arm64/boot/dts/qcom/sdm845.dtsi | 121 ++++++++++++++++++ 3 files changed, 183 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/gmu.txt
Document the device tree bindings for the Adreno GMU device available on Adreno a6xx targets.
Reviewed-by: Rob Herring robh@kernel.org Signed-off-by: Jordan Crouse jcrouse@codeaurora.org --- .../devicetree/bindings/display/msm/gmu.txt | 54 +++++++++++++++++++ .../devicetree/bindings/display/msm/gpu.txt | 10 +++- 2 files changed, 62 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/msm/gmu.txt
diff --git a/Documentation/devicetree/bindings/display/msm/gmu.txt b/Documentation/devicetree/bindings/display/msm/gmu.txt new file mode 100644 index 000000000000..6ab3e2cf29e9 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/gmu.txt @@ -0,0 +1,54 @@ +Qualcomm adreno/snapdragon GMU (Graphics management unit) + +The GMU is a programmable power controller for the GPU. the CPU controls the +GMU which in turn handles power controls for the GPU. + +Required properties: +- compatible: + * "qcom,adreno-gmu" +- reg: Physical base address and length of the GMU registers. +- reg-names: Matching names for the register regions + * "gmu" + * "gmu_pdc" +- interrupts: The interrupt signals from the GMU. +- interrupt-names: Matching names for the interrupts + * "hfi" + * "gmu" +- clocks: phandles to the device clocks +- clock-names: Matching names for the clocks + * "gmu" + * "cxo" + * "axi" + * "mnoc" +- power-domains: should be <&clock_gpucc GPU_CX_GDSC> +- iommus: phandle to the adreno iommu +- operating-points-v2: phandle to the OPP operating points + +Example: + +/ { + ... + + gmu: gmu@506a000 { + compatible="qcom,adreno-gmu"; + + reg = <0x506a000 0x30000>, + <0xb200000 0x300000>; + reg-names = "gmu", "gmu_pdc"; + + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hfi", "gmu"; + + clocks = <&clock_gpucc GPU_CC_CX_GMU_CLK>, + <&clock_gpucc GPU_CC_CXO_CLK>, + <&clock_gcc GCC_DDRSS_GPU_AXI_CLK>, + <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "gmu", "cxo", "axi", "memnoc"; + + power-domains = <&clock_gpucc GPU_CX_GDSC>; + iommus = <&adreno_smmu 5>; + + operating-points-v2 = <&gmu_opp_table>; + }; +}; diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt b/Documentation/devicetree/bindings/display/msm/gpu.txt index 43fac0fe09bb..544a7510166b 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.txt +++ b/Documentation/devicetree/bindings/display/msm/gpu.txt @@ -8,12 +8,18 @@ Required properties: with the chip-id. - reg: Physical base address and length of the controller's registers. - interrupts: The interrupt signal from the gpu. -- clocks: device clocks + +Optional properties. +- clocks: device clocks. Required for a3xx, a4xx and a5xx targets. a6xx and + newer with a GMU attached do not have direct clock control from the CPU and + do not need to provide clock properties. See ../clocks/clock-bindings.txt for details. -- clock-names: the following clocks are required: +- clock-names: the following clocks can be provided: * "core" * "iface" * "mem_iface" +- qcom,gmu: For a6xx and newer targets a phandle to the GMU device that will + control the power for the GPU
Example:
Add the nodes to describe the Adreno GPU and GMU devices.
Signed-off-by: Jordan Crouse jcrouse@codeaurora.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 121 +++++++++++++++++++++++++++ 1 file changed, 121 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index cdaabeb3c995..9fb90bb4ea1f 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -323,5 +323,126 @@ status = "disabled"; }; }; + + adreno_smmu: arm,smmu-adreno@5040000 { + compatible = "qcom,msm8996-smmu-v2"; + reg = <0x5040000 0x10000>; + #iommu-cells = <1>; + #global-interrupts = <2>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; + clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&clock_gcc GCC_GPU_CFG_AHB_CLK>; + clock-names = "bus", "iface"; + + power-domains = <&clock_gpucc GPU_CX_GDSC>; + }; + + gpu_opp_table: adreno-opp-table { + compatible = "operating-points-v2"; + + opp-710000000 { + opp-hz = /bits/ 64 <710000000>; + qcom,level = <416>; + }; + + opp-675000000 { + opp-hz = /bits/ 64 <675000000>; + qcom,level = <384>; + }; + + opp-596000000 { + opp-hz = /bits/ 64 <596000000>; + qcom,level = <320>; + }; + + opp-520000000 { + opp-hz = /bits/ 64 <520000000>; + qcom,level = <256>; + }; + + opp-414000000 { + opp-hz = /bits/ 64 <414000000>; + qcom,level = <192>; + }; + + opp-342000000 { + opp-hz = /bits/ 64 <342000000>; + qcom,level = <128>; + }; + + opp-257000000 { + opp-hz = /bits/ 64 <257000000>; + qcom,level = <64>; + }; + }; + + gpu@5000000 { + compatible = "qcom,adreno-630.2", "qcom,adreno"; + #stream-id-cells = <16>; + + reg = <0x5000000 0x40000>; + reg-names = "kgsl_3d0_reg_memory"; + + /* + * Look ma, no clocks! The GPU clocks and power are + * controlled entirely by the GMU + */ + + interrupts = <0 300 0>; + interrupt-names = "kgsl_3d0_irq"; + + iommus = <&adreno_smmu 0>; + + operating-points-v2 = <&gpu_opp_table>; + + qcom,gmu = <&gmu>; + }; + + gmu_opp_table: adreno-gmu-opp-table { + compatible = "operating-points-v2"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + qcom,level = <128>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + qcom,level = <48>; + }; + }; + + gmu: gmu@506a000 { + compatible="qcom,adreno-gmu"; + + reg = <0x506a000 0x30000>, + <0xb280000 0x10000>, + <0xb480000 0x10000>; + reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; + + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hfi", "gmu"; + + clocks = <&clock_gpucc GPU_CC_CX_GMU_CLK>, + <&clock_gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "gmu", "cxo", "axi", "memnoc"; + + power-domains = <&clock_gpucc GPU_CX_GDSC>; + iommus = <&adreno_smmu 5>; + + operating-points-v2 = <&gmu_opp_table>; + }; }; };
On 08/08/18 23:47, Jordan Crouse wrote:
Add the nodes to describe the Adreno GPU and GMU devices.
Signed-off-by: Jordan Crouse jcrouse@codeaurora.org
arch/arm64/boot/dts/qcom/sdm845.dtsi | 121 +++++++++++++++++++++++++++ 1 file changed, 121 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index cdaabeb3c995..9fb90bb4ea1f 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -323,5 +323,126 @@ status = "disabled"; }; };
adreno_smmu: arm,smmu-adreno@5040000 {compatible = "qcom,msm8996-smmu-v2";
Per the binding, this should be:
compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
(note that even with Vivek's series the driver won't actually match the SoC-specific string until we find a real need to)
reg = <0x5040000 0x10000>;#iommu-cells = <1>;#global-interrupts = <2>;
Indentation?
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
And here?
Otherwise, assuming the table walk really isn't cache-coherent, and the global and CB interrupts really do have different triggers (yuck :P), the SMMU parts look fine to me.
Robin.
<GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,<GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,<GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,<GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,<GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,<GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,<GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,<GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,<&clock_gcc GCC_GPU_CFG_AHB_CLK>;clock-names = "bus", "iface";power-domains = <&clock_gpucc GPU_CX_GDSC>;};gpu_opp_table: adreno-opp-table {compatible = "operating-points-v2";opp-710000000 {opp-hz = /bits/ 64 <710000000>;qcom,level = <416>;};opp-675000000 {opp-hz = /bits/ 64 <675000000>;qcom,level = <384>;};opp-596000000 {opp-hz = /bits/ 64 <596000000>;qcom,level = <320>;};opp-520000000 {opp-hz = /bits/ 64 <520000000>;qcom,level = <256>;};opp-414000000 {opp-hz = /bits/ 64 <414000000>;qcom,level = <192>;};opp-342000000 {opp-hz = /bits/ 64 <342000000>;qcom,level = <128>;};opp-257000000 {opp-hz = /bits/ 64 <257000000>;qcom,level = <64>;};};gpu@5000000 {compatible = "qcom,adreno-630.2", "qcom,adreno";#stream-id-cells = <16>;reg = <0x5000000 0x40000>;reg-names = "kgsl_3d0_reg_memory";/** Look ma, no clocks! The GPU clocks and power are* controlled entirely by the GMU*/interrupts = <0 300 0>;interrupt-names = "kgsl_3d0_irq";iommus = <&adreno_smmu 0>;operating-points-v2 = <&gpu_opp_table>;qcom,gmu = <&gmu>;};gmu_opp_table: adreno-gmu-opp-table {compatible = "operating-points-v2";opp-400000000 {opp-hz = /bits/ 64 <400000000>;qcom,level = <128>;};opp-200000000 {opp-hz = /bits/ 64 <200000000>;qcom,level = <48>;};};gmu: gmu@506a000 {compatible="qcom,adreno-gmu";reg = <0x506a000 0x30000>,<0xb280000 0x10000>,<0xb480000 0x10000>;reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;interrupt-names = "hfi", "gmu";clocks = <&clock_gpucc GPU_CC_CX_GMU_CLK>,<&clock_gpucc GPU_CC_CXO_CLK>,<&gcc GCC_DDRSS_GPU_AXI_CLK>,<&gcc GCC_GPU_MEMNOC_GFX_CLK>;clock-names = "gmu", "cxo", "axi", "memnoc";power-domains = <&clock_gpucc GPU_CX_GDSC>;iommus = <&adreno_smmu 5>;operating-points-v2 = <&gmu_opp_table>;};
Quoting Jordan Crouse (2018-08-08 15:47:01)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index cdaabeb3c995..9fb90bb4ea1f 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -323,5 +323,126 @@ status = "disabled"; }; };
adreno_smmu: arm,smmu-adreno@5040000 {compatible = "qcom,msm8996-smmu-v2";reg = <0x5040000 0x10000>;#iommu-cells = <1>;#global-interrupts = <2>;interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,<GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,<GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,<GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,<GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,<GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,<GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,<GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,<&clock_gcc GCC_GPU_CFG_AHB_CLK>;clock-names = "bus", "iface";power-domains = <&clock_gpucc GPU_CX_GDSC>;};gpu_opp_table: adreno-opp-table {
The OPP tables should be moved into the root of the tree. Nothing should be under the SoC node without a reg property.
compatible = "operating-points-v2";opp-710000000 {opp-hz = /bits/ 64 <710000000>;qcom,level = <416>;
Hi Jordan,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on robclark/msm-next] [also build test ERROR on v4.18-rc8 next-20180810] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Jordan-Crouse/arm64-dts-Add-sdm845-... base: git://people.freedesktop.org/~robclark/linux msm-next config: arm64-defconfig (attached as .config) compiler: aarch64-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0 reproduce: wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # save the attached .config to linux build tree GCC_VERSION=7.2.0 make.cross ARCH=arm64
All errors (new ones prefixed by >>):
Error: arch/arm64/boot/dts/qcom/sdm845.dtsi:342.25-26 syntax error
FATAL ERROR: Unable to parse input tree
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