[radeon-alex:amd-20.45 1379/2427] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c:103:35: error: no member named 'bw_params' in 'struct clk_mgr' - dri-devel - freedesktop.org experimental mailing list

15 Dec 2020


      tree:   git://people.freedesktop.org/~agd5f/linux.git amd-20.45
head:   a3950d94b046fb206e58fd3ec717f071c0203ba3
commit: 470f4be73099cc46478d2c708411fecde8197ca3 [1379/2427] drm/amdkcl: update DRM_AMD_DC_DCN3_0 to depends on legacy display config
config: x86_64-randconfig-a001-20201214 (attached as .config)
compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project a29ecca7819a6ed4250d3689b12b1f664bb790d7)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # install x86_64 cross compiling tool for clang build
        # apt-get install binutils-x86-64-linux-gnu
        git remote add radeon-alex git://people.freedesktop.org/~agd5f/linux.git
        git fetch --no-tags radeon-alex amd-20.45
        git checkout 470f4be73099cc46478d2c708411fecde8197ca3
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot lkp@intel.com
All errors (new ones prefixed by >>):
...
...
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c:103:35: error: no member named 'bw_params' in 'struct clk_mgr'
entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]);
                                     ~~~~~~~~~~~~~ ^
   drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c:113:40: error: no member named 'bw_params' in 'struct clk_mgr'
           uint16_t min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz;
                                   ~~~~~~~~~~~~~ ^
   drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c:116:16: error: no member named 'bw_params' in 'struct clk_mgr'
           clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true;
           ~~~~~~~~~~~~~ ^
...
...
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c:116:47: error: use of undeclared identifier 'WM_A'
clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true;
                                                        ^
   drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c:117:16: error: no member named 'bw_params' in 'struct clk_mgr'
           clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us;
           ~~~~~~~~~~~~~ ^
   drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c:117:47: error: use of undeclared identifier 'WM_A'
           clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us;
                                                        ^
   drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c:118:16: error: no member named 'bw_params' in 'struct clk_mgr'
           clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us;
           ~~~~~~~~~~~~~ ^
   drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c:118:47: error: use of undeclared identifier 'WM_A'
           clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us;
                                                        ^
   drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c:119:16: error: no member named 'bw_params' in 'struct clk_mgr'
           clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
           ~~~~~~~~~~~~~ ^
   drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c:119:47: error: use of undeclared identifier 'WM_A'
           clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
                                                        ^
   drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c:120:16: error: no member named 'bw_params' in 'struct clk_mgr'
           clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
           ~~~~~~~~~~~~~ ^
   drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c:120:47: error: use of undeclared identifier 'WM_A'
           clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
                                                        ^
   drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c:121:16: error: no member named 'bw_params' in 'struct clk_mgr'
           clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = 0;
           ~~~~~~~~~~~~~ ^
   drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c:121:47: error: use of undeclared identifier 'WM_A'
           clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = 0;
                                                        ^
   drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c:122:16: error: no member named 'bw_params' in 'struct clk_mgr'
           clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF;
           ~~~~~~~~~~~~~ ^
   drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c:122:47: error: use of undeclared identifier 'WM_A'
           clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF;
                                                        ^
   drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c:123:16: error: no member named 'bw_params' in 'struct clk_mgr'
           clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz;
           ~~~~~~~~~~~~~ ^
   drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c:123:47: error: use of undeclared identifier 'WM_A'
           clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz;
                                                        ^
   drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c:124:16: error: no member named 'bw_params' in 'struct clk_mgr'
           clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF;
           ~~~~~~~~~~~~~ ^
   fatal error: too many errors emitted, stopping now [-ferror-limit=]
   20 errors generated.
--
   In file included from drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.c:26:
...
...
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:229:2: error: type name requires a specifier or qualifier
DCN30_HUBP_REG_COMMON_VARIABLE_LIST;
           ^
   drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:164:2: note: expanded from macro 'DCN30_HUBP_REG_COMMON_VARIABLE_LIST'
           DCN21_HUBP_REG_COMMON_VARIABLE_LIST;\
           ^
   drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:239:2: error: type name requires a specifier or qualifier
           DCN30_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t);
           ^
   drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:207:2: note: expanded from macro 'DCN30_HUBP_REG_FIELD_VARIABLE_LIST'
           DCN21_HUBP_REG_FIELD_VARIABLE_LIST(type);\
           ^
   drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:250:2: error: type name requires a specifier or qualifier
           DCN30_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t);
           ^
   drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.h:207:2: note: expanded from macro 'DCN30_HUBP_REG_FIELD_VARIABLE_LIST'
           DCN21_HUBP_REG_FIELD_VARIABLE_LIST(type);\
           ^
...
...
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.c:61:15: error: no member named 'DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB' in 'struct dcn_hubp2_registers'
REG_UPDATE_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
           ~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/amd/display/dc/inc/reg_helper.h:235:16: note: expanded from macro 'REG_UPDATE_2'
                   REG_UPDATE_N(reg, 2,\
                   ~~~~~~~~~~~~~^~~~~~~~
   drivers/gpu/drm/amd/display/dc/inc/reg_helper.h:227:9: note: expanded from macro 'REG_UPDATE_N'
                                   REG(reg_name), \
                                   ~~~~^~~~~~~~~
   drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.c:36:20: note: expanded from macro 'REG'
           hubp2->hubp_regs->reg
           ~~~~~~~~~~~~~~~~  ^
...
...
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.c:62:3: error: no member named 'DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM' in 'struct dcn_hubp2_shift'
DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, 1, /* 1 = system physical memory */
                   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/amd/display/dc/inc/reg_helper.h:236:13: note: expanded from macro 'REG_UPDATE_2'
                                   FN(reg, f1), v1,\
                                   ~~~~~~~~^~~
   drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.c:43:21: note: expanded from macro 'FN'
           hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name
           ~~~~~~~~~~~~~~~~~  ^
   drivers/gpu/drm/amd/display/dc/inc/reg_helper.h:228:8: note: expanded from macro 'REG_UPDATE_N'
                                   n, __VA_ARGS__)
                                      ^~~~~~~~~~~
...
...
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.c:62:3: error: no member named 'DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM' in 'struct dcn_hubp2_mask'
DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, 1, /* 1 = system physical memory */
                   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/amd/display/dc/inc/reg_helper.h:236:13: note: expanded from macro 'REG_UPDATE_2'
                                   FN(reg, f1), v1,\
                                   ~~~~~~~~^~~
   drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.c:43:51: note: expanded from macro 'FN'
           hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name
                                          ~~~~~~~~~~~~~~~~  ^
   drivers/gpu/drm/amd/display/dc/inc/reg_helper.h:228:8: note: expanded from macro 'REG_UPDATE_N'
                                   n, __VA_ARGS__)
                                      ^~~~~~~~~~~
...
...
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.c:63:3: error: no member named 'DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB' in 'struct dcn_hubp2_shift'
DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part);
                   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/amd/display/dc/inc/reg_helper.h:237:13: note: expanded from macro 'REG_UPDATE_2'
                                   FN(reg, f2), v2)
                                   ~~~~~~~~^~~
   drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.c:43:21: note: expanded from macro 'FN'
           hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name
           ~~~~~~~~~~~~~~~~~  ^
   drivers/gpu/drm/amd/display/dc/inc/reg_helper.h:228:8: note: expanded from macro 'REG_UPDATE_N'
                                   n, __VA_ARGS__)
                                      ^~~~~~~~~~~
...
...
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.c:63:3: error: no member named 'DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB' in 'struct dcn_hubp2_mask'
DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part);
                   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/amd/display/dc/inc/reg_helper.h:237:13: note: expanded from macro 'REG_UPDATE_2'
                                   FN(reg, f2), v2)
                                   ~~~~~~~~^~~
   drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.c:43:51: note: expanded from macro 'FN'
           hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name
                                          ~~~~~~~~~~~~~~~~  ^
   drivers/gpu/drm/amd/display/dc/inc/reg_helper.h:228:8: note: expanded from macro 'REG_UPDATE_N'
                                   n, __VA_ARGS__)
                                      ^~~~~~~~~~~
...
...
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.c:65:10: error: no member named 'DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB' in 'struct dcn_hubp2_registers'
REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0,
           ~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/amd/display/dc/inc/reg_helper.h:64:13: note: expanded from macro 'REG_SET'
                   REG_SET_N(reg_name, 1, initial_val, \
                   ~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/amd/display/dc/inc/reg_helper.h:56:9: note: expanded from macro 'REG_SET_N'
                                   REG(reg_name), \
                                   ~~~~^~~~~~~~~
   drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.c:36:20: note: expanded from macro 'REG'
           hubp2->hubp_regs->reg
           ~~~~~~~~~~~~~~~~  ^
...
...
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.c:66:4: error: no member named 'DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB' in 'struct dcn_hubp2_shift'
DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part);
                           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/amd/display/dc/inc/reg_helper.h:65:18: note: expanded from macro 'REG_SET'
                                   FN(reg_name, field), val)
                                   ~~~~~~~~~~~~~^~~~~~
   drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.c:43:21: note: expanded from macro 'FN'
           hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name
           ~~~~~~~~~~~~~~~~~  ^
   drivers/gpu/drm/amd/display/dc/inc/reg_helper.h:58:8: note: expanded from macro 'REG_SET_N'
                                   n, __VA_ARGS__)
                                      ^~~~~~~~~~~
...
...
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.c:66:4: error: no member named 'DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB' in 'struct dcn_hubp2_mask'
DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part);
                           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/amd/display/dc/inc/reg_helper.h:65:18: note: expanded from macro 'REG_SET'
                                   FN(reg_name, field), val)
                                   ~~~~~~~~~~~~~^~~~~~
   drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.c:43:51: note: expanded from macro 'FN'
           hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name
                                          ~~~~~~~~~~~~~~~~  ^
   drivers/gpu/drm/amd/display/dc/inc/reg_helper.h:58:8: note: expanded from macro 'REG_SET_N'
                                   n, __VA_ARGS__)
                                      ^~~~~~~~~~~
...
...
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.c:68:10: error: no member named 'DCN_VM_SYSTEM_APERTURE_LOW_ADDR' in 'struct dcn_hubp2_registers'
REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0,
           ~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/amd/display/dc/inc/reg_helper.h:64:13: note: expanded from macro 'REG_SET'
                   REG_SET_N(reg_name, 1, initial_val, \
                   ~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/amd/display/dc/inc/reg_helper.h:56:9: note: expanded from macro 'REG_SET_N'
                                   REG(reg_name), \
                                   ~~~~^~~~~~~~~
   drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.c:36:20: note: expanded from macro 'REG'
           hubp2->hubp_regs->reg
           ~~~~~~~~~~~~~~~~  ^
...
...
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.c:69:4: error: no member named 'MC_VM_SYSTEM_APERTURE_LOW_ADDR' in 'struct dcn_hubp2_shift'
MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part);
                           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/amd/display/dc/inc/reg_helper.h:65:18: note: expanded from macro 'REG_SET'
                                   FN(reg_name, field), val)
                                   ~~~~~~~~~~~~~^~~~~~
   drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.c:43:21: note: expanded from macro 'FN'
           hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name
           ~~~~~~~~~~~~~~~~~  ^
   drivers/gpu/drm/amd/display/dc/inc/reg_helper.h:58:8: note: expanded from macro 'REG_SET_N'
                                   n, __VA_ARGS__)
                                      ^~~~~~~~~~~
...
...
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.c:69:4: error: no member named 'MC_VM_SYSTEM_APERTURE_LOW_ADDR' in 'struct dcn_hubp2_mask'
MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part);
                           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/amd/display/dc/inc/reg_helper.h:65:18: note: expanded from macro 'REG_SET'
                                   FN(reg_name, field), val)
                                   ~~~~~~~~~~~~~^~~~~~
   drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.c:43:51: note: expanded from macro 'FN'
           hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name
                                          ~~~~~~~~~~~~~~~~  ^
   drivers/gpu/drm/amd/display/dc/inc/reg_helper.h:58:8: note: expanded from macro 'REG_SET_N'
                                   n, __VA_ARGS__)
                                      ^~~~~~~~~~~
...
...
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.c:71:10: error: no member named 'DCN_VM_SYSTEM_APERTURE_HIGH_ADDR' in 'struct dcn_hubp2_registers'
REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0,
           ~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/amd/display/dc/inc/reg_helper.h:64:13: note: expanded from macro 'REG_SET'
                   REG_SET_N(reg_name, 1, initial_val, \
                   ~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/amd/display/dc/inc/reg_helper.h:56:9: note: expanded from macro 'REG_SET_N'
                                   REG(reg_name), \
                                   ~~~~^~~~~~~~~
   drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.c:36:20: note: expanded from macro 'REG'
           hubp2->hubp_regs->reg
           ~~~~~~~~~~~~~~~~  ^
...
...
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.c:72:4: error: no member named 'MC_VM_SYSTEM_APERTURE_HIGH_ADDR' in 'struct dcn_hubp2_shift'
MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part);
                           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/amd/display/dc/inc/reg_helper.h:65:18: note: expanded from macro 'REG_SET'
                                   FN(reg_name, field), val)
                                   ~~~~~~~~~~~~~^~~~~~
   drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.c:43:21: note: expanded from macro 'FN'
           hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name
           ~~~~~~~~~~~~~~~~~  ^
   drivers/gpu/drm/amd/display/dc/inc/reg_helper.h:58:8: note: expanded from macro 'REG_SET_N'
                                   n, __VA_ARGS__)
                                      ^~~~~~~~~~~
...
...
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.c:72:4: error: no member named 'MC_VM_SYSTEM_APERTURE_HIGH_ADDR' in 'struct dcn_hubp2_mask'
MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part);
                           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/amd/display/dc/inc/reg_helper.h:65:18: note: expanded from macro 'REG_SET'
                                   FN(reg_name, field), val)
                                   ~~~~~~~~~~~~~^~~~~~
   drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.c:43:51: note: expanded from macro 'FN'
           hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name
                                          ~~~~~~~~~~~~~~~~  ^
   drivers/gpu/drm/amd/display/dc/inc/reg_helper.h:58:8: note: expanded from macro 'REG_SET_N'
                                   n, __VA_ARGS__)
                                      ^~~~~~~~~~~
...
...
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.c:74:12: error: no member named 'DCN_VM_MX_L1_TLB_CNTL' in 'struct dcn_hubp2_registers'
REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
           ~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/amd/display/dc/inc/reg_helper.h:68:13: note: expanded from macro 'REG_SET_2'
                   REG_SET_N(reg, 2, init_value, \
                   ~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~
   drivers/gpu/drm/amd/display/dc/inc/reg_helper.h:56:9: note: expanded from macro 'REG_SET_N'
                                   REG(reg_name), \
                                   ~~~~^~~~~~~~~
   drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.c:36:20: note: expanded from macro 'REG'
           hubp2->hubp_regs->reg
           ~~~~~~~~~~~~~~~~  ^
...
...
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.c:75:4: error: no member named 'ENABLE_L1_TLB' in 'struct dcn_hubp2_shift'
ENABLE_L1_TLB, 1,
                           ^~~~~~~~~~~~~~~~~
   drivers/gpu/drm/amd/display/dc/inc/reg_helper.h:69:13: note: expanded from macro 'REG_SET_2'
                                   FN(reg, f1), v1,\
                                   ~~~~~~~~^~~
   drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_hubp.c:43:21: note: expanded from macro 'FN'
           hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name
           ~~~~~~~~~~~~~~~~~  ^
   drivers/gpu/drm/amd/display/dc/inc/reg_helper.h:58:8: note: expanded from macro 'REG_SET_N'
                                   n, __VA_ARGS__)
                                      ^~~~~~~~~~~
   fatal error: too many errors emitted, stopping now [-ferror-limit=]
   20 errors generated.
--
...
...
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hubbub.c:384:4: error: no member named 'DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A' in 'struct dcn_hubbub_shift'; did you mean 'DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A'?
DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A, prog_wm_value);
                           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
                           DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A
   drivers/gpu/drm/amd/display/dc/inc/reg_helper.h:70:13: note: expanded from macro 'REG_SET_2'
                                   FN(reg, f2), v2)
                                           ^
   drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hubbub.c:41:19: note: expanded from macro 'FN'
           hubbub1->shifts->field_name, hubbub1->masks->field_name
                            ^
   drivers/gpu/drm/amd/display/dc/inc/reg_helper.h:58:8: note: expanded from macro 'REG_SET_N'
                                   n, __VA_ARGS__)
                                      ^
   drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h:284:2: note: 'DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A' declared here
           DCN_HUBBUB_REG_FIELD_LIST(uint8_t);
           ^
   drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h:214:8: note: expanded from macro 'DCN_HUBBUB_REG_FIELD_LIST'
                   type DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A;\
                        ^
...
...
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hubbub.c:384:4: error: no member named 'DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A' in 'struct dcn_hubbub_mask'; did you mean 'DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A'?
DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A, prog_wm_value);
                           ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
                           DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A
   drivers/gpu/drm/amd/display/dc/inc/reg_helper.h:70:13: note: expanded from macro 'REG_SET_2'
                                   FN(reg, f2), v2)
                                           ^
   drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_hubbub.c:41:47: note: expanded from macro 'FN'
           hubbub1->shifts->field_name, hubbub1->masks->field_name
                                                        ^
   drivers/gpu/drm/amd/display/dc/inc/reg_helper.h:58:8: note: expanded from macro 'REG_SET_N'
                                   n, __VA_ARGS__)
                                      ^
   drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h:292:2: note: 'DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A' declared here
           DCN_HUBBUB_REG_FIELD_LIST(uint32_t);
           ^
   drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h:214:8: note: expanded from macro 'DCN_HUBBUB_REG_FIELD_LIST'
                   type DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A;\
                        ^
   2 errors generated.
..
vim +103 drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21   83  
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21   84  
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21   85  /* Query SMU for all clock states for a particular clock */
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21   86  static void dcn3_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *entry_0, unsigned int *num_levels)
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21   87  {
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21   88  	unsigned int i;
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21   89  	char *entry_i = (char *)entry_0;
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21   90  	uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF);
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21   91  
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21   92  	if (ret & (1 << 31))
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21   93  		/* fine-grained, only min and max */
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21   94  		*num_levels = 2;
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21   95  	else
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21   96  		/* discrete, a number of fixed states */
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21   97  		/* will set num_levels to 0 on failure */
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21   98  		*num_levels = ret & 0xFF;
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21   99  
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  100  	/* if the initial message failed, num_levels will be 0 */
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  101  	for (i = 0; i < *num_levels; i++) {
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  102  		*((unsigned int *)entry_i) = (dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF);
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21 @103  		entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]);
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  104  	}
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  105  }
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  106  
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  107  static void dcn3_build_wm_range_table(struct clk_mgr_internal *clk_mgr)
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  108  {
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  109  	/* defaults */
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  110  	double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us;
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  111  	double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us;
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  112  	double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us;
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  113  	uint16_t min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz;
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  114  
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  115  	/* Set A - Normal - default values*/
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21 @116  	clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true;
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  117  	clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us;
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  118  	clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us;
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  119  	clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  120  	clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  121  	clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = 0;
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  122  	clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF;
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  123  	clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz;
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  124  	clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF;
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  125  
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  126  	/* Set B - Performance - higher minimum clocks */
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  127  //	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].valid = true;
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  128  //	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us = pstate_latency_us;
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  129  //	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us = sr_exit_time_us;
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  130  //	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  131  //	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  132  //	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = TUNED VALUE;
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  133  //	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_dcfclk = 0xFFFF;
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  134  //	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_uclk = TUNED VALUE;
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  135  //	clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_uclk = 0xFFFF;
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  136  
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  137  	/* Set C - Dummy P-State - P-State latency set to "dummy p-state" value */
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  138  	clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].valid = true;
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  139  	clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dummy_pstate_latency_us;
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  140  	clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = sr_exit_time_us;
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  141  	clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  142  	clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE;
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  143  	clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_dcfclk = 0;
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  144  	clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_dcfclk = 0xFFFF;
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  145  	clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_uclk = min_uclk_mhz;
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  146  	clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF;
652edbbbddcc8b1 Bhawanpreet Lakha 2020-05-21  147
:::::: The code at line 103 was first introduced by commit
:::::: 652edbbbddcc8b1470d8fe91e7dca0ceeab4aced drm/amd/display: Add DCN3 CLK_MGR
:::::: TO: Bhawanpreet Lakha Bhawanpreet.Lakha@amd.com
:::::: CC: Yang Xiong Yang.Xiong@amd.com
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org