This series patches are used for yuv image overlay display.
Rockchip vop support NV11, NV16, NV24 yuv format, and can scale the image scale 1/8 to 8.
Mark Yao (6): drm/rockchip: import dma_buf to gem drm/rockchip: vop: optimize virtual stride calculate drm/rockchip: vop: fix yuv plane support drm/rockchip: vop: support plane scale drm/rockchip: vop: switch cursor plane to window 3 drm/rockchip: vop: default enable win2/3 area0 bit
drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 1 + drivers/gpu/drm/rockchip/rockchip_drm_gem.c | 45 ++- drivers/gpu/drm/rockchip/rockchip_drm_gem.h | 5 +- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 445 ++++++++++++++++++++++++++- drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 96 ++++++ 5 files changed, 581 insertions(+), 11 deletions(-)
We want to display a buffer allocated by other driver, need import the buffer to gem.
Signed-off-by: Mark Yao mark.yao@rock-chips.com --- drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 1 + drivers/gpu/drm/rockchip/rockchip_drm_gem.c | 45 +++++++++++++++++++++++++-- drivers/gpu/drm/rockchip/rockchip_drm_gem.h | 5 ++- 3 files changed, 47 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c index 3962176..9001a90 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c @@ -287,6 +287,7 @@ static struct drm_driver rockchip_drm_driver = { .prime_handle_to_fd = drm_gem_prime_handle_to_fd, .prime_fd_to_handle = drm_gem_prime_fd_to_handle, .gem_prime_import = drm_gem_prime_import, + .gem_prime_import_sg_table = rockchip_gem_prime_import_sg_table, .gem_prime_export = drm_gem_prime_export, .gem_prime_get_sg_table = rockchip_gem_prime_get_sg_table, .gem_prime_vmap = rockchip_gem_prime_vmap, diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c index eb2282c..2e30e23 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c @@ -18,6 +18,7 @@ #include <drm/drm_vma_manager.h>
#include <linux/dma-attrs.h> +#include <linux/dma-buf.h>
#include "rockchip_drm_drv.h" #include "rockchip_drm_gem.h" @@ -105,6 +106,38 @@ int rockchip_gem_mmap(struct file *filp, struct vm_area_struct *vma) return ret; }
+struct drm_gem_object * +rockchip_gem_prime_import_sg_table(struct drm_device *drm, + struct dma_buf_attachment *attach, + struct sg_table *sgt) +{ + struct rockchip_gem_object *rk_obj; + struct drm_gem_object *obj; + int ret; + + rk_obj = kzalloc(sizeof(*rk_obj), GFP_KERNEL); + if (!rk_obj) + return ERR_PTR(-ENOMEM); + + obj = &rk_obj->base; + + drm_gem_private_object_init(drm, obj, attach->dmabuf->size); + + if (!dma_map_sg(drm->dev, sgt->sgl, sgt->nents, DMA_TO_DEVICE)) { + ret = -ENOMEM; + goto err_free_obj; + } + rk_obj->dma_addr = sg_dma_address(sgt->sgl); + rk_obj->sgt = sgt; + obj->size = sg_dma_len(sgt->sgl); + + return obj; + +err_free_obj: + kfree(rk_obj); + return ERR_PTR(ret); +} + struct rockchip_gem_object * rockchip_gem_create_object(struct drm_device *drm, unsigned int size, bool alloc_kmap) @@ -140,13 +173,19 @@ err_free_rk_obj: */ void rockchip_gem_free_object(struct drm_gem_object *obj) { + struct drm_device *drm = obj->dev; struct rockchip_gem_object *rk_obj;
- drm_gem_free_mmap_offset(obj); - rk_obj = to_rockchip_obj(obj);
- rockchip_gem_free_buf(rk_obj); + if (obj->import_attach) { + dma_unmap_sg(drm->dev, rk_obj->sgt->sgl, + rk_obj->sgt->nents, DMA_TO_DEVICE); + drm_prime_gem_destroy(obj, rk_obj->sgt); + } else { + drm_gem_free_mmap_offset(obj); + rockchip_gem_free_buf(rk_obj); + }
kfree(rk_obj); } diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_gem.h b/drivers/gpu/drm/rockchip/rockchip_drm_gem.h index ad22618..9fd58e3 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.h @@ -21,6 +21,7 @@ struct rockchip_gem_object { struct drm_gem_object base; unsigned int flags;
+ struct sg_table *sgt; void *kvaddr; dma_addr_t dma_addr; struct dma_attrs dma_attrs; @@ -28,8 +29,10 @@ struct rockchip_gem_object {
struct sg_table *rockchip_gem_prime_get_sg_table(struct drm_gem_object *obj); struct drm_gem_object * -rockchip_gem_prime_import_sg_table(struct drm_device *dev, size_t size, +rockchip_gem_prime_import_sg_table(struct drm_device *drm, + struct dma_buf_attachment *attach, struct sg_table *sgt); + void *rockchip_gem_prime_vmap(struct drm_gem_object *obj); void rockchip_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
On Thu, Jun 18, 2015 at 03:49:25PM +0800, Mark Yao wrote:
We want to display a buffer allocated by other driver, need import the buffer to gem.
Signed-off-by: Mark Yao mark.yao@rock-chips.com
drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 1 + drivers/gpu/drm/rockchip/rockchip_drm_gem.c | 45 +++++++++++++++++++++++++-- drivers/gpu/drm/rockchip/rockchip_drm_gem.h | 5 ++- 3 files changed, 47 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c index 3962176..9001a90 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c @@ -287,6 +287,7 @@ static struct drm_driver rockchip_drm_driver = { .prime_handle_to_fd = drm_gem_prime_handle_to_fd, .prime_fd_to_handle = drm_gem_prime_fd_to_handle, .gem_prime_import = drm_gem_prime_import,
- .gem_prime_import_sg_table = rockchip_gem_prime_import_sg_table, .gem_prime_export = drm_gem_prime_export, .gem_prime_get_sg_table = rockchip_gem_prime_get_sg_table, .gem_prime_vmap = rockchip_gem_prime_vmap,
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c index eb2282c..2e30e23 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c @@ -18,6 +18,7 @@ #include <drm/drm_vma_manager.h>
#include <linux/dma-attrs.h> +#include <linux/dma-buf.h>
#include "rockchip_drm_drv.h" #include "rockchip_drm_gem.h" @@ -105,6 +106,38 @@ int rockchip_gem_mmap(struct file *filp, struct vm_area_struct *vma) return ret; }
+struct drm_gem_object * +rockchip_gem_prime_import_sg_table(struct drm_device *drm,
struct dma_buf_attachment *attach,struct sg_table *sgt)+{
- struct rockchip_gem_object *rk_obj;
- struct drm_gem_object *obj;
- int ret;
- rk_obj = kzalloc(sizeof(*rk_obj), GFP_KERNEL);
- if (!rk_obj)
return ERR_PTR(-ENOMEM);- obj = &rk_obj->base;
- drm_gem_private_object_init(drm, obj, attach->dmabuf->size);
- if (!dma_map_sg(drm->dev, sgt->sgl, sgt->nents, DMA_TO_DEVICE)) {
ret = -ENOMEM;goto err_free_obj;- }
- rk_obj->dma_addr = sg_dma_address(sgt->sgl);
- rk_obj->sgt = sgt;
- obj->size = sg_dma_len(sgt->sgl);
This is wrong.
First, if you can only cope with a single scatterlist entry, you need to enforce that. You can do that in your gem_prime_import_sg_table() method by checking sgt->nents.
Secondly, you're mapping an already mapped scatterlist - scatterlists are mapped by the exporter inside dma_buf_map_attachment() for your device.
Thirdly, I hate drm_gem_prime_import() being used on ARM... it forces drivers to do something very buggy: the DMA buffer is mapped for DMA when the buffer is imported. If the buffer is a write-combine or cached buffer, writes to the buffer after the import will not become visible to the display hardware until sometime later (when they're evicted from the caches and/or pushed out of the bus structure.) The DMA mapping should be performed as close to the start of DMA as possible. However, this is a long-standing issue I have with dma_buf itself and is not something you should be too concerned with in your patch. Just bear it in mind if you start to see corruption of imported buffers - the answer is not more dma_map_sg() calls, but to get dma_buf fixed.
Thanks Russell On 2015年06月18日 18:57, Russell King - ARM Linux wrote:
This is wrong.
First, if you can only cope with a single scatterlist entry, you need to enforce that. You can do that in your gem_prime_import_sg_table() method by checking sgt->nents.
I'm confuse that how to get coherent iova address from nocoherent scatterlist with iommu. I saw the arm_iommu_map_sg, it says that: The scatter gather list elements are merged together (if possible) and tagged with the appropriate dma address and length.
I guess the map_sg maybe merge scatterlist into coherent iova address, but I don't know how to check the "if possible", and the sgt->nents not be 1 when already map to coherent iova address.
checking sgt-nents = 1 can sure that iova is coherent, but when coherent iova address from nocoherent scatterlist, I think sgt->nents maybe greater than 1, is there a method can deal it?
All above is my guess, maybe wrong, I only tested it with CMA buffer import.
Secondly, you're mapping an already mapped scatterlist - scatterlists are mapped by the exporter inside dma_buf_map_attachment() for your device.
Right, found the dma_map_sg on dma_buf_map_attachment().
Thirdly, I hate drm_gem_prime_import() being used on ARM... it forces drivers to do something very buggy: the DMA buffer is mapped for DMA when the buffer is imported. If the buffer is a write-combine or cached buffer, writes to the buffer after the import will not become visible to the display hardware until sometime later (when they're evicted from the caches and/or pushed out of the bus structure.) The DMA mapping should be performed as close to the start of DMA as possible. However, this is a long-standing issue I have with dma_buf itself and is not something you should be too concerned with in your patch. Just bear it in mind if you start to see corruption of imported buffers - the answer is not more dma_map_sg() calls, but to get dma_buf fixed.
Yeah, Got it.
vir_stride need number words of the virtual width, and fb->pitches save bytes_per_pixel, so just div 4 switch to stride.
Signed-off-by: Mark Yao mark.yao@rock-chips.com --- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 6188221..3c9f4f3 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -644,7 +644,7 @@ static int vop_update_plane_event(struct drm_plane *plane, offset += (src.y1 >> 16) * fb->pitches[0]; yrgb_mst = rk_obj->dma_addr + offset;
- y_vir_stride = fb->pitches[0] / (fb->bits_per_pixel >> 3); + y_vir_stride = fb->pitches[0] >> 2;
/* * If this plane update changes the plane's framebuffer, (or more
vop support yuv with NV12, NV16 and NV24, only 2 plane yuv.
Signed-off-by: Mark Yao mark.yao@rock-chips.com --- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 42 ++++++++++++++++++++++++++- 1 file changed, 41 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 3c9f4f3..7d84549 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -373,6 +373,18 @@ static enum vop_data_format vop_convert_format(uint32_t format) } }
+static bool is_yuv_support(uint32_t format) +{ + switch (format) { + case DRM_FORMAT_NV12: + case DRM_FORMAT_NV16: + case DRM_FORMAT_NV24: + return true; + default: + return false; + } +} + static bool is_alpha_support(uint32_t format) { switch (format) { @@ -577,16 +589,21 @@ static int vop_update_plane_event(struct drm_plane *plane, struct vop *vop = to_vop(crtc); struct drm_gem_object *obj; struct rockchip_gem_object *rk_obj; + struct drm_gem_object *uv_obj; + struct rockchip_gem_object *rk_uv_obj; unsigned long offset; unsigned int actual_w; unsigned int actual_h; unsigned int dsp_stx; unsigned int dsp_sty; unsigned int y_vir_stride; + unsigned int uv_vir_stride; dma_addr_t yrgb_mst; + dma_addr_t uv_mst; enum vop_data_format format; uint32_t val; bool is_alpha; + bool is_yuv; bool visible; int ret; struct drm_rect dest = { @@ -608,6 +625,12 @@ static int vop_update_plane_event(struct drm_plane *plane, }; bool can_position = plane->type != DRM_PLANE_TYPE_PRIMARY;
+ if (drm_format_num_planes(fb->pixel_format) > 2) { + DRM_ERROR("unsupport more than 2 plane format[%08x]\n", + fb->pixel_format); + return -EINVAL; + } + ret = drm_plane_helper_check_update(plane, crtc, fb, &src, &dest, &clip, DRM_PLANE_HELPER_NO_SCALING, @@ -624,6 +647,8 @@ static int vop_update_plane_event(struct drm_plane *plane, if (format < 0) return format;
+ is_yuv = is_yuv_support(fb->pixel_format); + obj = rockchip_fb_get_gem_obj(fb, 0); if (!obj) { DRM_ERROR("fail to get rockchip gem object from framebuffer\n"); @@ -642,10 +667,21 @@ static int vop_update_plane_event(struct drm_plane *plane,
offset = (src.x1 >> 16) * (fb->bits_per_pixel >> 3); offset += (src.y1 >> 16) * fb->pitches[0]; - yrgb_mst = rk_obj->dma_addr + offset;
+ yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0]; y_vir_stride = fb->pitches[0] >> 2;
+ if (is_yuv) { + uv_obj = rockchip_fb_get_gem_obj(fb, 1); + if (!uv_obj) { + DRM_ERROR("fail to get uv object from framebuffer\n"); + return -EINVAL; + } + rk_uv_obj = to_rockchip_obj(uv_obj); + uv_vir_stride = (fb->pitches[1] >> 2); + uv_mst = rk_uv_obj->dma_addr + fb->offsets[1]; + } + /* * If this plane update changes the plane's framebuffer, (or more * precisely, if this update has a different framebuffer than the last @@ -681,6 +717,10 @@ static int vop_update_plane_event(struct drm_plane *plane, VOP_WIN_SET(vop, win, format, format); VOP_WIN_SET(vop, win, yrgb_vir, y_vir_stride); VOP_WIN_SET(vop, win, yrgb_mst, yrgb_mst); + if (is_yuv) { + VOP_WIN_SET(vop, win, uv_vir, uv_vir_stride); + VOP_WIN_SET(vop, win, uv_mst, uv_mst); + } val = (actual_h - 1) << 16; val |= (actual_w - 1) & 0xffff; VOP_WIN_SET(vop, win, act_info, val);
Win_full support 1/8 to 8 scale down/up engine, support all format scale.
Signed-off-by: Mark Yao mark.yao@rock-chips.com --- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 390 ++++++++++++++++++++++++++- drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 96 +++++++ 2 files changed, 483 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 7d84549..f573459 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -49,6 +49,8 @@
#define VOP_WIN_SET(x, win, name, v) \ REG_SET(x, win->base, win->phy->name, v, RELAXED) +#define VOP_SCL_SET(x, win, name, v) \ + REG_SET(x, win->base, win->phy->scl->name, v, RELAXED) #define VOP_CTRL_SET(x, name, v) \ REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
@@ -163,7 +165,37 @@ struct vop_ctrl { struct vop_reg vpost_st_end; };
+struct vop_scl_regs { + struct vop_reg cbr_vsd_mode; + struct vop_reg cbr_vsu_mode; + struct vop_reg cbr_hsd_mode; + struct vop_reg cbr_ver_scl_mode; + struct vop_reg cbr_hor_scl_mode; + struct vop_reg yrgb_vsd_mode; + struct vop_reg yrgb_vsu_mode; + struct vop_reg yrgb_hsd_mode; + struct vop_reg yrgb_ver_scl_mode; + struct vop_reg yrgb_hor_scl_mode; + struct vop_reg line_load_mode; + struct vop_reg cbr_axi_gather_num; + struct vop_reg yrgb_axi_gather_num; + struct vop_reg vsd_cbr_gt2; + struct vop_reg vsd_cbr_gt4; + struct vop_reg vsd_yrgb_gt2; + struct vop_reg vsd_yrgb_gt4; + struct vop_reg bic_coe_sel; + struct vop_reg cbr_axi_gather_en; + struct vop_reg yrgb_axi_gather_en; + + struct vop_reg lb_mode; + struct vop_reg scale_yrgb_x; + struct vop_reg scale_yrgb_y; + struct vop_reg scale_cbcr_x; + struct vop_reg scale_cbcr_y; +}; + struct vop_win_phy { + const struct vop_scl_regs *scl; const uint32_t *data_formats; uint32_t nformats;
@@ -212,7 +244,36 @@ static const uint32_t formats_234[] = { DRM_FORMAT_RGB565, };
+static const struct vop_scl_regs win_full_scl = { + .cbr_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 31), + .cbr_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 30), + .cbr_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 28), + .cbr_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 26), + .cbr_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 24), + .yrgb_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 23), + .yrgb_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 22), + .yrgb_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 20), + .yrgb_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 18), + .yrgb_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 16), + .line_load_mode = VOP_REG(WIN0_CTRL1, 0x1, 15), + .cbr_axi_gather_num = VOP_REG(WIN0_CTRL1, 0x7, 12), + .yrgb_axi_gather_num = VOP_REG(WIN0_CTRL1, 0xf, 8), + .vsd_cbr_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 7), + .vsd_cbr_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 6), + .vsd_yrgb_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 5), + .vsd_yrgb_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 4), + .bic_coe_sel = VOP_REG(WIN0_CTRL1, 0x3, 2), + .cbr_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 1), + .yrgb_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 0), + .lb_mode = VOP_REG(WIN0_CTRL0, 0x7, 5), + .scale_yrgb_x = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), + .scale_yrgb_y = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0xffff, 16), + .scale_cbcr_x = VOP_REG(WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), + .scale_cbcr_y = VOP_REG(WIN0_SCL_FACTOR_CBR, 0xffff, 16), +}; + static const struct vop_win_phy win01_data = { + .scl = &win_full_scl, .data_formats = formats_01, .nformats = ARRAY_SIZE(formats_01), .enable = VOP_REG(WIN0_CTRL0, 0x1, 0), @@ -351,6 +412,15 @@ static inline void vop_mask_write_relaxed(struct vop *vop, uint32_t offset, } }
+static inline int _get_vskiplines(uint32_t srch, uint32_t dsth) +{ + if (srch >= (uint32_t)(4 * dsth * MIN_SCL_FT_AFTER_VSKIP)) + return 4; + else if (srch >= (uint32_t)(2 * dsth * MIN_SCL_FT_AFTER_VSKIP)) + return 2; + return 1; +} + static enum vop_data_format vop_convert_format(uint32_t format) { switch (format) { @@ -538,6 +608,310 @@ static void vop_disable(struct drm_crtc *crtc) pm_runtime_put(vop->dev); }
+static int _vop_cal_yrgb_lb_mode(int width) +{ + int lb_mode = LB_RGB_1920X5; + + if (width > 2560) + lb_mode = LB_RGB_3840X2; + else if (width > 1920) + lb_mode = LB_RGB_2560X4; + + return lb_mode; +} + +static int _vop_cal_cbcr_lb_mode(int width) +{ + int lb_mode = LB_YUV_2560X8; + + if (width > 2560) + lb_mode = LB_RGB_3840X2; + else if (width > 1920) + lb_mode = LB_RGB_2560X4; + else if (width > 1280) + lb_mode = LB_YUV_3840X5; + + return lb_mode; +} + +static void _vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win, + uint32_t src_w, uint32_t src_h, uint32_t dst_w, + uint32_t dst_h, uint32_t pixel_format) +{ + uint16_t yrgb_hor_scl_mode = SCALE_NONE; + uint16_t yrgb_ver_scl_mode = SCALE_NONE; + uint16_t cbr_hor_scl_mode = SCALE_NONE; + uint16_t cbr_ver_scl_mode = SCALE_NONE; + uint16_t yrgb_hsd_mode = SCALE_DOWN_BIL; + uint16_t cbr_hsd_mode = SCALE_DOWN_BIL; + uint16_t yrgb_vsd_mode = SCALE_DOWN_BIL; + uint16_t cbr_vsd_mode = SCALE_DOWN_BIL; + uint16_t yrgb_vsu_mode = SCALE_UP_BIL; + uint16_t cbr_vsu_mode = SCALE_UP_BIL; + uint16_t scale_yrgb_x = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; + uint16_t scale_yrgb_y = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; + uint16_t scale_cbcr_x = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; + uint16_t scale_cbcr_y = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; + int hsub = drm_format_horz_chroma_subsampling(pixel_format); + int vsub = drm_format_vert_chroma_subsampling(pixel_format); + bool is_yuv = is_yuv_support(pixel_format); + uint16_t vsd_yrgb_gt4 = 0; + uint16_t vsd_yrgb_gt2 = 0; + uint16_t vsd_cbr_gt4 = 0; + uint16_t vsd_cbr_gt2 = 0; + uint16_t yrgb_src_w = src_w; + uint16_t yrgb_src_h = src_h; + uint16_t yrgb_dst_w = dst_w; + uint16_t yrgb_dst_h = dst_h; + uint16_t cbcr_src_w; + uint16_t cbcr_src_h; + uint16_t cbcr_dst_w; + uint16_t cbcr_dst_h; + uint32_t vdmult; + uint16_t lb_mode; + + if (((yrgb_dst_w << 3) <= yrgb_src_w) || + ((yrgb_dst_h << 3) <= yrgb_src_h) || + yrgb_dst_w > 3840) { + DRM_ERROR("yrgb scale exceed 8,src[%dx%d] dst[%dx%d]\n", + yrgb_src_w, yrgb_src_h, yrgb_dst_w, yrgb_dst_h); + return; + } + + if (yrgb_src_w < yrgb_dst_w) + yrgb_hor_scl_mode = SCALE_UP; + else if (yrgb_src_w > yrgb_dst_w) + yrgb_hor_scl_mode = SCALE_DOWN; + else + yrgb_hor_scl_mode = SCALE_NONE; + + if (yrgb_src_h < yrgb_dst_h) + yrgb_ver_scl_mode = SCALE_UP; + else if (yrgb_src_h > yrgb_dst_h) + yrgb_ver_scl_mode = SCALE_DOWN; + else + yrgb_ver_scl_mode = SCALE_NONE; + + if (is_yuv) { + cbcr_src_w = src_w / hsub; + cbcr_src_h = src_h / vsub; + cbcr_dst_w = dst_w; + cbcr_dst_h = dst_h; + if ((cbcr_dst_w << 3) <= cbcr_src_w || + (cbcr_dst_h << 3) <= cbcr_src_h || + cbcr_src_w > 3840 || + cbcr_src_w == 0) + DRM_ERROR("cbcr scale failed,src[%dx%d] dst[%dx%d]\n", + cbcr_src_w, cbcr_src_h, + cbcr_dst_w, cbcr_dst_h); + if (cbcr_src_w < cbcr_dst_w) + cbr_hor_scl_mode = SCALE_UP; + else if (cbcr_src_w > cbcr_dst_w) + cbr_hor_scl_mode = SCALE_DOWN; + + if (cbcr_src_h < cbcr_dst_h) + cbr_ver_scl_mode = SCALE_UP; + else if (cbcr_src_h > cbcr_dst_h) + cbr_ver_scl_mode = SCALE_DOWN; + } + /* + * line buffer mode + */ + if (is_yuv) { + if (yrgb_hor_scl_mode == SCALE_DOWN && yrgb_dst_w > 2560) + lb_mode = LB_RGB_3840X2; + else if (cbr_hor_scl_mode == SCALE_DOWN) + lb_mode = _vop_cal_cbcr_lb_mode(cbcr_dst_w); + else + lb_mode = _vop_cal_cbcr_lb_mode(cbcr_src_w); + } else { + if (yrgb_hor_scl_mode == SCALE_DOWN) + lb_mode = _vop_cal_yrgb_lb_mode(yrgb_dst_w); + else + lb_mode = _vop_cal_yrgb_lb_mode(yrgb_src_w); + } + + switch (lb_mode) { + case LB_YUV_3840X5: + case LB_YUV_2560X8: + case LB_RGB_1920X5: + case LB_RGB_1280X8: + yrgb_vsu_mode = SCALE_UP_BIC; + cbr_vsu_mode = SCALE_UP_BIC; + break; + case LB_RGB_3840X2: + if (yrgb_ver_scl_mode != SCALE_NONE) + DRM_ERROR("ERROR : not allow yrgb ver scale\n"); + if (cbr_ver_scl_mode != SCALE_NONE) + DRM_ERROR("ERROR : not allow cbcr ver scale\n"); + break; + case LB_RGB_2560X4: + yrgb_vsu_mode = SCALE_UP_BIL; + cbr_vsu_mode = SCALE_UP_BIL; + break; + default: + DRM_ERROR("unsupport lb_mode:%d\n", lb_mode); + break; + } + /* + * (1.1)YRGB HOR SCALE FACTOR + */ + switch (yrgb_hor_scl_mode) { + case SCALE_UP: + scale_yrgb_x = GET_SCL_FT_BIC(yrgb_src_w, yrgb_dst_w); + break; + case SCALE_DOWN: + switch (yrgb_hsd_mode) { + case SCALE_DOWN_BIL: + scale_yrgb_x = GET_SCL_FT_BILI_DN(yrgb_src_w, + yrgb_dst_w); + break; + case SCALE_DOWN_AVG: + scale_yrgb_x = GET_SCL_FT_AVRG(yrgb_src_w, yrgb_dst_w); + break; + default: + DRM_ERROR("unsupport yrgb_hsd_mode:%d\n", + yrgb_hsd_mode); + break; + } + break; + } + + /* + * (1.2)YRGB VER SCALE FACTOR + */ + switch (yrgb_ver_scl_mode) { + case SCALE_UP: + switch (yrgb_vsu_mode) { + case SCALE_UP_BIL: + scale_yrgb_y = GET_SCL_FT_BILI_UP(yrgb_src_h, + yrgb_dst_h); + break; + case SCALE_UP_BIC: + if (yrgb_src_h < 3) + DRM_ERROR("yrgb_src_h should greater than 3\n"); + scale_yrgb_y = GET_SCL_FT_BIC(yrgb_src_h, yrgb_dst_h); + break; + default: + DRM_ERROR("unsupport yrgb_vsu_mode:%d\n", + yrgb_vsu_mode); + break; + } + break; + case SCALE_DOWN: + switch (yrgb_vsd_mode) { + case SCALE_DOWN_BIL: + vdmult = _get_vskiplines(yrgb_src_h, yrgb_dst_h); + scale_yrgb_y = GET_SCL_FT_BILI_DN_VSKIP(yrgb_src_h, + yrgb_dst_h, + vdmult); + if (vdmult == 4) { + vsd_yrgb_gt4 = 1; + vsd_yrgb_gt2 = 0; + } else if (vdmult == 2) { + vsd_yrgb_gt4 = 0; + vsd_yrgb_gt2 = 1; + } + break; + case SCALE_DOWN_AVG: + scale_yrgb_y = GET_SCL_FT_AVRG(yrgb_src_h, yrgb_dst_h); + break; + default: + DRM_ERROR("unsupport yrgb_vsd_mode:%d\n", + yrgb_vsd_mode); + break; + } + break; + } + /* + * (2.1)CBCR HOR SCALE FACTOR + */ + switch (cbr_hor_scl_mode) { + case SCALE_UP: + scale_cbcr_x = GET_SCL_FT_BIC(cbcr_src_w, cbcr_dst_w); + break; + case SCALE_DOWN: + switch (cbr_hsd_mode) { + case SCALE_DOWN_BIL: + scale_cbcr_x = GET_SCL_FT_BILI_DN(cbcr_src_w, + cbcr_dst_w); + break; + case SCALE_DOWN_AVG: + scale_cbcr_x = GET_SCL_FT_AVRG(cbcr_src_w, cbcr_dst_w); + break; + default: + DRM_ERROR("unsupport cbr_hsd_mode:%d\n", cbr_hsd_mode); + break; + } + break; + } + + /* + * (2.2)CBCR VER SCALE FACTOR + */ + switch (cbr_ver_scl_mode) { + case SCALE_UP: + switch (cbr_vsu_mode) { + case SCALE_UP_BIL: + scale_cbcr_y = GET_SCL_FT_BILI_UP(cbcr_src_h, + cbcr_dst_h); + break; + case SCALE_UP_BIC: + if (cbcr_src_h < 3) + DRM_ERROR("cbcr_src_h need greater than 3 !\n"); + scale_cbcr_y = GET_SCL_FT_BIC(cbcr_src_h, cbcr_dst_h); + break; + default: + DRM_ERROR("unsupport cbr_vsu_mode:%d\n", cbr_vsu_mode); + break; + } + break; + case SCALE_DOWN: + switch (cbr_vsd_mode) { + case SCALE_DOWN_BIL: + vdmult = _get_vskiplines(cbcr_src_h, cbcr_dst_h); + scale_cbcr_y = GET_SCL_FT_BILI_DN_VSKIP(cbcr_src_h, + cbcr_dst_h, + vdmult); + if (vdmult == 4) { + vsd_cbr_gt4 = 1; + vsd_cbr_gt2 = 0; + } else if (vdmult == 2) { + vsd_cbr_gt4 = 0; + vsd_cbr_gt2 = 1; + } + break; + case SCALE_DOWN_AVG: + scale_cbcr_y = GET_SCL_FT_AVRG(cbcr_src_h, cbcr_dst_h); + break; + default: + DRM_ERROR("unsupport cbr_vsd_mode:%d\n", cbr_vsd_mode); + break; + } + break; + } + + VOP_SCL_SET(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode); + VOP_SCL_SET(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode); + VOP_SCL_SET(vop, win, cbr_hor_scl_mode, cbr_hor_scl_mode); + VOP_SCL_SET(vop, win, cbr_ver_scl_mode, cbr_ver_scl_mode); + VOP_SCL_SET(vop, win, lb_mode, lb_mode); + VOP_SCL_SET(vop, win, yrgb_hsd_mode, yrgb_hsd_mode); + VOP_SCL_SET(vop, win, cbr_hsd_mode, cbr_hsd_mode); + VOP_SCL_SET(vop, win, yrgb_vsd_mode, yrgb_vsd_mode); + VOP_SCL_SET(vop, win, cbr_vsd_mode, cbr_vsd_mode); + VOP_SCL_SET(vop, win, yrgb_vsu_mode, yrgb_vsu_mode); + VOP_SCL_SET(vop, win, cbr_vsu_mode, cbr_vsu_mode); + VOP_SCL_SET(vop, win, scale_yrgb_x, scale_yrgb_x); + VOP_SCL_SET(vop, win, scale_yrgb_y, scale_yrgb_y); + VOP_SCL_SET(vop, win, vsd_yrgb_gt4, vsd_yrgb_gt4); + VOP_SCL_SET(vop, win, vsd_yrgb_gt2, vsd_yrgb_gt2); + VOP_SCL_SET(vop, win, scale_cbcr_x, scale_cbcr_x); + VOP_SCL_SET(vop, win, scale_cbcr_y, scale_cbcr_y); + VOP_SCL_SET(vop, win, vsd_cbr_gt4, vsd_cbr_gt4); + VOP_SCL_SET(vop, win, vsd_cbr_gt2, vsd_cbr_gt2); +} + /* * Caller must hold vsync_mutex. */ @@ -624,6 +998,8 @@ static int vop_update_plane_event(struct drm_plane *plane, .y2 = crtc->mode.vdisplay, }; bool can_position = plane->type != DRM_PLANE_TYPE_PRIMARY; + int min_scale = win->phy->scl ? 0x02000 : DRM_PLANE_HELPER_NO_SCALING; + int max_scale = win->phy->scl ? 0x80000 : DRM_PLANE_HELPER_NO_SCALING;
if (drm_format_num_planes(fb->pixel_format) > 2) { DRM_ERROR("unsupport more than 2 plane format[%08x]\n", @@ -633,8 +1009,8 @@ static int vop_update_plane_event(struct drm_plane *plane,
ret = drm_plane_helper_check_update(plane, crtc, fb, &src, &dest, &clip, - DRM_PLANE_HELPER_NO_SCALING, - DRM_PLANE_HELPER_NO_SCALING, + min_scale, + max_scale, can_position, false, &visible); if (ret) return ret; @@ -678,7 +1054,7 @@ static int vop_update_plane_event(struct drm_plane *plane, return -EINVAL; } rk_uv_obj = to_rockchip_obj(uv_obj); - uv_vir_stride = (fb->pitches[1] >> 2); + uv_vir_stride = fb->pitches[1] >> 2; uv_mst = rk_uv_obj->dma_addr + fb->offsets[1]; }
@@ -721,9 +1097,17 @@ static int vop_update_plane_event(struct drm_plane *plane, VOP_WIN_SET(vop, win, uv_vir, uv_vir_stride); VOP_WIN_SET(vop, win, uv_mst, uv_mst); } + + if (win->phy->scl) + _vop_cal_scl_fac(vop, win, actual_w, actual_h, + crtc_w, crtc_h, fb->pixel_format); + val = (actual_h - 1) << 16; val |= (actual_w - 1) & 0xffff; VOP_WIN_SET(vop, win, act_info, val); + + val = (crtc_h - 1) << 16; + val |= (crtc_w - 1) & 0xffff; VOP_WIN_SET(vop, win, dsp_info, val); val = (dsp_sty - 1) << 16; val |= (dsp_stx - 1) & 0xffff; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h index 63e9b3a..edacdee 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h @@ -198,4 +198,100 @@ enum factor_mode { ALPHA_SRC_GLOBAL, };
+enum scale_mode { + SCALE_NONE = 0x0, + SCALE_UP = 0x1, + SCALE_DOWN = 0x2 +}; + +enum lb_mode { + LB_YUV_3840X5 = 0x0, + LB_YUV_2560X8 = 0x1, + LB_RGB_3840X2 = 0x2, + LB_RGB_2560X4 = 0x3, + LB_RGB_1920X5 = 0x4, + LB_RGB_1280X8 = 0x5 +}; + +enum sacle_up_mode { + SCALE_UP_BIL = 0x0, + SCALE_UP_BIC = 0x1 +}; + +enum scale_down_mode { + SCALE_DOWN_BIL = 0x0, + SCALE_DOWN_AVG = 0x1 +}; + +#define CUBIC_PRECISE 0 +#define CUBIC_SPLINE 1 +#define CUBIC_CATROM 2 +#define CUBIC_MITCHELL 3 + +#define CUBIC_MODE_SELETION CUBIC_PRECISE + +#define SCL_FT_BILI_DN_FIXPOINT_SHIFT 12 +#define SCL_FT_BILI_DN_FIXPOINT(x) \ + ((INT32)((x)*(1 << SCL_FT_BILI_DN_FIXPOINT_SHIFT))) + +#define SCL_FT_BILI_UP_FIXPOINT_SHIFT 16 + +#define SCL_FT_AVRG_FIXPOINT_SHIFT 16 +#define SCL_FT_AVRG_FIXPOINT(x) \ + ((INT32)((x) * (1 << SCL_FT_AVRG_FIXPOINT_SHIFT))) + +#define SCL_FT_BIC_FIXPOINT_SHIFT 16 +#define SCL_FT_BIC_FIXPOINT(x) \ + ((INT32)((x)*(1 << SCL_FT_BIC_FIXPOINT_SHIFT))) + +#define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12 +#define SCL_FT_VSDBIL_FIXPOINT_SHIFT 12 + +#define SCL_CAL(src, dst, shift) \ + ((((src) * 2 - 3) << ((shift) - 1)) / ((dst) - 1)) +#define GET_SCL_FT_BILI_DN(src, dst) \ + SCL_CAL(src, dst, SCL_FT_BILI_DN_FIXPOINT_SHIFT) +#define GET_SCL_FT_BILI_UP(src, dst) \ + SCL_CAL(src, dst, SCL_FT_BILI_UP_FIXPOINT_SHIFT) +#define GET_SCL_FT_BIC(src, dst) \ + SCL_CAL(src, dst, SCL_FT_BIC_FIXPOINT_SHIFT) + +#define GET_SCL_DN_ACT_HEIGHT(src_h, vdmult) \ + (((src_h) + (vdmult) - 1) / (vdmult)) + +#define MIN_SCL_FT_AFTER_VSKIP 1 +#define GET_SCL_FT_BILI_DN_VSKIP(src_h, dst_h, vdmult) \ + ((GET_SCL_DN_ACT_HEIGHT((src_h), (vdmult)) == (dst_h)) \ + ? (GET_SCL_FT_BILI_DN((src_h), (dst_h))/(vdmult)) \ + : GET_SCL_FT_BILI_DN(GET_SCL_DN_ACT_HEIGHT((src_h), \ + (vdmult)), (dst_h))) + +#define GET_SCL_FT_AVRG(src, dst) \ + (((dst) << ((SCL_FT_AVRG_FIXPOINT_SHIFT) + 1)) \ + / (2 * (src) - 1)) + +#define SCL_COOR_ACC_FIXPOINT_SHIFT 16 +#define SCL_COOR_ACC_FIXPOINT_ONE (1 << SCL_COOR_ACC_FIXPOINT_SHIFT) +#define SCL_COOR_ACC_FIXPOINT(x) \ + ((INT32)((x)*(1 << SCL_COOR_ACC_FIXPOINT_SHIFT))) +#define SCL_COOR_ACC_FIXPOINT_REVERT(x) \ + ((((x) >> (SCL_COOR_ACC_FIXPOINT_SHIFT-1)) + 1) >> 1) + +#define SCL_GET_COOR_ACC_FIXPOINT(scale, shift) \ + ((scale) << (SCL_COOR_ACC_FIXPOINT_SHIFT - (shift))) +#define SCL_FILTER_FT_FIXPOINT_SHIFT 8 +#define SCL_FILTER_FT_FIXPOINT_ONE (1 << SCL_FILTER_FT_FIXPOINT_SHIFT) +#define SCL_FILTER_FT_FIXPOINT(x) \ + ((INT32)((x) * (1 << SCL_FILTER_FT_FIXPOINT_SHIFT))) +#define SCL_FILTER_FT_FIXPOINT_REVERT(x) \ + ((((x) >> (SCL_FILTER_FT_FIXPOINT_SHIFT - 1)) + 1) >> 1) + +#define SCL_GET_FILTER_FT_FIXPOINT(ca, shift) \ + (((ca) >> ((shift)-SCL_FILTER_FT_FIXPOINT_SHIFT)) & \ + (SCL_FILTER_FT_FIXPOINT_ONE - 1)) + +#define SCL_OFFSET_FIXPOINT_SHIFT 8 +#define SCL_OFFSET_FIXPOINT(x) \ + ((INT32)((x) * (1 << SCL_OFFSET_FIXPOINT_SHIFT))) + #endif /* _ROCKCHIP_DRM_VOP_H */
Window 1 support scale and yuv format, it's waste use it for a cursor, use window 3 is enough.
Signed-off-by: Mark Yao mark.yao@rock-chips.com --- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index f573459..ceac71f 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -342,13 +342,14 @@ static const struct vop_reg_data vop_init_reg_table[] = { /* * Note: rk3288 has a dedicated 'cursor' window, however, that window requires * special support to get alpha blending working. For now, just use overlay - * window 1 for the drm cursor. + * window 3 for the drm cursor. + * */ static const struct vop_win_data rk3288_vop_win_data[] = { { .base = 0x00, .phy = &win01_data, .type = DRM_PLANE_TYPE_PRIMARY }, - { .base = 0x40, .phy = &win01_data, .type = DRM_PLANE_TYPE_CURSOR }, + { .base = 0x40, .phy = &win01_data, .type = DRM_PLANE_TYPE_OVERLAY }, { .base = 0x00, .phy = &win23_data, .type = DRM_PLANE_TYPE_OVERLAY }, - { .base = 0x50, .phy = &win23_data, .type = DRM_PLANE_TYPE_OVERLAY }, + { .base = 0x50, .phy = &win23_data, .type = DRM_PLANE_TYPE_CURSOR }, { .base = 0x00, .phy = &cursor_data, .type = DRM_PLANE_TYPE_OVERLAY }, };
Win2/3 support 4 area display, but now havn't found a suitable way to use it, and it enable by win gate and area gate, so default enable area0 gate, so that its behaviour just like a win.
Signed-off-by: Mark Yao mark.yao@rock-chips.com --- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index ceac71f..1b70783 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -337,6 +337,12 @@ static const struct vop_reg_data vop_init_reg_table[] = { {DSP_CTRL0, 0x00000000}, {WIN0_CTRL0, 0x00000080}, {WIN1_CTRL0, 0x00000080}, + /* + * Todo: win2/3 support area func, but now havn't found a suitable + * way to use it, so default enable area0 as a win display. + */ + {WIN2_CTRL0, 0x00000010}, + {WIN3_CTRL0, 0x00000010}, };
/*
dri-devel@lists.freedesktop.org
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Mark Yao -
Mark yao
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Russell King - ARM Linux