RK3288 hdmi eye-diagram test would fail when pixel clock is 148.5MHz, and single-ended test would failed when display mode is 74.25MHz.
To fix such problems, we make those patch set: - Fix some code style, leave space for next patches. - For hdmi eye-diagram test, we turn on the Transmitter Trailer-B and improve slopeboost to 10%-20% decrease. - For hdmi single-ended test, set CKLVL to 18 and TXLVL to 19 when pixel clock is 74.25MHz. set CKLVL to 13 and TXLVL to 13 when pixel clock is 148.5MHz.
Changes in v3: - make commit message more readable - For pixel clock less than 148.5MHz, set txlvl to 20.
Changes in v2: - Set slopeboost back to 10%-20%, then rasing/falling time would pass. - For pixel clock less than 74.25MHz, set txlvl to 19 and set cklvl to 18.
Yakir Yang (3): drm: bridge/dw_hdmi: fixed codec style drm: bridge/dw_hdmi_rockchip: improve hdmi eye-diagram test drm: bridge/dw_hdmi: improve hdmi single-end test
drivers/gpu/drm/bridge/dw_hdmi.c | 20 ++++++++++---------- drivers/gpu/drm/imx/dw_hdmi-imx.c | 12 ++++++------ drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 14 +++++++------- include/drm/bridge/dw_hdmi.h | 5 +++-- 4 files changed, 26 insertions(+), 25 deletions(-)
Using a local struct pointer to reduce one level of indirection makes the code slightly more readable.
Signed-off-by: Yakir Yang ykk@rock-chips.com Reviewed-by: Daniel Kurtz djkurtz@chromium.org ---
Changes in v3: - make commit message more readable
Changes in v2: None
drivers/gpu/drm/bridge/dw_hdmi.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/bridge/dw_hdmi.c b/drivers/gpu/drm/bridge/dw_hdmi.c index 9ffc257..b9d8d8a 100644 --- a/drivers/gpu/drm/bridge/dw_hdmi.c +++ b/drivers/gpu/drm/bridge/dw_hdmi.c @@ -900,10 +900,10 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep, { unsigned res_idx, i; u8 val, msec; - const struct dw_hdmi_mpll_config *mpll_config = - hdmi->plat_data->mpll_cfg; - const struct dw_hdmi_curr_ctrl *curr_ctrl = hdmi->plat_data->cur_ctr; - const struct dw_hdmi_sym_term *sym_term = hdmi->plat_data->sym_term; + const struct dw_hdmi_plat_data *plat_data = hdmi->plat_data; + const struct dw_hdmi_mpll_config *mpll_config = plat_data->mpll_cfg; + const struct dw_hdmi_curr_ctrl *curr_ctrl = plat_data->cur_ctr; + const struct dw_hdmi_sym_term *sym_term = plat_data->sym_term;
if (prep) return -EINVAL;
As for 1920x1080 display resolution, we should turn on the Transmitter Trailer-B.
Signed-off-by: Yakir Yang ykk@rock-chips.com ---
Changes in v3: None Changes in v2: - Set slopeboost back to 10%-20%, then rasing/falling time would pass.
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index e46e1d9..be0371d 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -142,7 +142,7 @@ static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = { static const struct dw_hdmi_sym_term rockchip_sym_term[] = { /*pixelclk symbol term*/ { 74250000, 0x8009, 0x0004 }, - { 148500000, 0x8029, 0x0004 }, + { 148500000, 0x802b, 0x0004 }, { 297000000, 0x8039, 0x0005 }, { ~0UL, 0x0000, 0x0000 } };
On Mon, Mar 09, 2015 at 05:43:19PM +0800, Yakir Yang wrote:
As for 1920x1080 display resolution, we should turn on the Transmitter Trailer-B.
Signed-off-by: Yakir Yang ykk@rock-chips.com
BTW, one of:
drm/rockchip: dw_hdmi-rockchip: ... drm/rockchip: dw_hdmi: ... drm: rockchip: dw_hdmi-rockchip: ... drm: rockchip: dw_hdmi: ... drm: rockchip/dw_hdmi-rockchip: ... drm: rockchip/dw_hdmi: ...
might be a better subject line for patches which only touch the rockchip part of this driver. I'd also suggest one of:
drm/imx: dw_hdmi-imx: ... drm/imx: dw_hdmi: ... drm: imx: dw_hdmi-imx: ... drm: imx: dw_hdmi: ... drm: imx/dw_hdmi-imx: ... drm: imx/dw_hdmi: ...
for iMX-only patches. It doesn't really mater which as we already have a mixture of these formats already.
Hi Russell,
在 2015/4/1 0:57, Russell King - ARM Linux 写道:
On Mon, Mar 09, 2015 at 05:43:19PM +0800, Yakir Yang wrote:
As for 1920x1080 display resolution, we should turn on the Transmitter Trailer-B.
Signed-off-by: Yakir Yang ykk@rock-chips.com
BTW, one of:
drm/rockchip: dw_hdmi-rockchip: ... drm/rockchip: dw_hdmi: ... drm: rockchip: dw_hdmi-rockchip: ... drm: rockchip: dw_hdmi: ... drm: rockchip/dw_hdmi-rockchip: ... drm: rockchip/dw_hdmi: ...
might be a better subject line for patches which only touch the rockchip part of this driver. I'd also suggest one of:
Okay, I choose the "drm: rockchip/dw_hdmi-rockchip: ...", improve in v4
Thanks Yakir Yang
drm/imx: dw_hdmi-imx: ... drm/imx: dw_hdmi: ... drm: imx: dw_hdmi-imx: ... drm: imx: dw_hdmi: ... drm: imx/dw_hdmi-imx: ... drm: imx/dw_hdmi: ...
for iMX-only patches. It doesn't really mater which as we already have a mixture of these formats already.
Because of iMX6 & Rockchip have differnet mpll config parameter, than the cklvl & txlvl would be different, we also should seperate this parmeter.
When pixle clock less than 148.5MHz, the cklvl set to 13(2.79v), and txlvl set to 20(2.77v). When pixel clock less than 74.25MHz, the cklvl set to 18(2.80v), and txlvl set to 19(2.75v).
Signed-off-by: Yakir Yang ykk@rock-chips.com ---
Changes in v3: - For pixel clock less than 148.5MHz, set txlvl to 20.
Changes in v2: - For pixel clock less than 74.25MHz, set txlvl to 19 and set cklvl to 18.
drivers/gpu/drm/bridge/dw_hdmi.c | 14 +++++++------- drivers/gpu/drm/imx/dw_hdmi-imx.c | 12 ++++++------ drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 14 +++++++------- include/drm/bridge/dw_hdmi.h | 5 +++-- 4 files changed, 23 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/bridge/dw_hdmi.c b/drivers/gpu/drm/bridge/dw_hdmi.c index b9d8d8a..6edefdd 100644 --- a/drivers/gpu/drm/bridge/dw_hdmi.c +++ b/drivers/gpu/drm/bridge/dw_hdmi.c @@ -903,7 +903,7 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep, const struct dw_hdmi_plat_data *plat_data = hdmi->plat_data; const struct dw_hdmi_mpll_config *mpll_config = plat_data->mpll_cfg; const struct dw_hdmi_curr_ctrl *curr_ctrl = plat_data->cur_ctr; - const struct dw_hdmi_sym_term *sym_term = plat_data->sym_term; + const struct dw_hdmi_phy_config *phy_config = plat_data->phy_config;
if (prep) return -EINVAL; @@ -974,18 +974,18 @@ static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep, hdmi_phy_i2c_write(hdmi, 0x0000, 0x13); /* PLLPHBYCTRL */ hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
- for (i = 0; sym_term[i].mpixelclock != (~0UL); i++) + for (i = 0; phy_config[i].mpixelclock != (~0UL); i++) if (hdmi->hdmi_data.video_mode.mpixelclock <= - sym_term[i].mpixelclock) + phy_config[i].mpixelclock) break;
/* RESISTANCE TERM 133Ohm Cfg */ - hdmi_phy_i2c_write(hdmi, sym_term[i].term, 0x19); /* TXTERM */ + hdmi_phy_i2c_write(hdmi, phy_config[i].term, 0x19); /* TXTERM */ /* PREEMP Cgf 0.00 */ - hdmi_phy_i2c_write(hdmi, sym_term[i].sym_ctr, 0x09); /* CKSYMTXCTRL */ - + hdmi_phy_i2c_write(hdmi, phy_config[i].sym_ctr, 0x09); /* CKSYMTXCTRL */ /* TX/CK LVL 10 */ - hdmi_phy_i2c_write(hdmi, 0x01ad, 0x0E); /* VLEVCTRL */ + hdmi_phy_i2c_write(hdmi, phy_config[i].vlev_ctr, 0x0E); /* VLEVCTRL */ + /* REMOVE CLK TERM */ hdmi_phy_i2c_write(hdmi, 0x8000, 0x05); /* CKCALCTRL */
diff --git a/drivers/gpu/drm/imx/dw_hdmi-imx.c b/drivers/gpu/drm/imx/dw_hdmi-imx.c index 121d30c..d6095d2 100644 --- a/drivers/gpu/drm/imx/dw_hdmi-imx.c +++ b/drivers/gpu/drm/imx/dw_hdmi-imx.c @@ -73,10 +73,10 @@ static const struct dw_hdmi_curr_ctrl imx_cur_ctr[] = { } };
-static const struct dw_hdmi_sym_term imx_sym_term[] = { - /*pixelclk symbol term*/ - { 148500000, 0x800d, 0x0005 }, - { ~0UL, 0x0000, 0x0000 } +static const struct dw_hdmi_phy_config imx_phy_config[] = { + /*pixelclk symbol term vlev */ + { 148500000, 0x800d, 0x0005, 0x01ad}, + { ~0UL, 0x0000, 0x0000, 0x0000} };
static int dw_hdmi_imx_parse_dt(struct imx_hdmi *hdmi) @@ -139,14 +139,14 @@ static struct drm_encoder_funcs dw_hdmi_imx_encoder_funcs = { static struct dw_hdmi_plat_data imx6q_hdmi_drv_data = { .mpll_cfg = imx_mpll_cfg, .cur_ctr = imx_cur_ctr, - .sym_term = imx_sym_term, + .phy_config = imx_phy_config, .dev_type = IMX6Q_HDMI, };
static struct dw_hdmi_plat_data imx6dl_hdmi_drv_data = { .mpll_cfg = imx_mpll_cfg, .cur_ctr = imx_cur_ctr, - .sym_term = imx_sym_term, + .phy_config = imx_phy_config, .dev_type = IMX6DL_HDMI, };
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index be0371d..5a66c7f 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -139,12 +139,12 @@ static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = { } };
-static const struct dw_hdmi_sym_term rockchip_sym_term[] = { - /*pixelclk symbol term*/ - { 74250000, 0x8009, 0x0004 }, - { 148500000, 0x802b, 0x0004 }, - { 297000000, 0x8039, 0x0005 }, - { ~0UL, 0x0000, 0x0000 } +static const struct dw_hdmi_phy_config rockchip_phy_config[] = { + /*pixelclk symbol term vlev*/ + { 74250000, 0x8009, 0x0004, 0x0272}, + { 148500000, 0x802b, 0x0004, 0x028d}, + { 297000000, 0x8039, 0x0005, 0x028d}, + { ~0UL, 0x0000, 0x0000, 0x0000} };
static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) @@ -236,7 +236,7 @@ static const struct dw_hdmi_plat_data rockchip_hdmi_drv_data = { .mode_valid = dw_hdmi_rockchip_mode_valid, .mpll_cfg = rockchip_mpll_cfg, .cur_ctr = rockchip_cur_ctr, - .sym_term = rockchip_sym_term, + .phy_config = rockchip_phy_config, .dev_type = RK3288_HDMI, };
diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h index fb07a90..8e9885d 100644 --- a/include/drm/bridge/dw_hdmi.h +++ b/include/drm/bridge/dw_hdmi.h @@ -40,10 +40,11 @@ struct dw_hdmi_curr_ctrl { u16 curr[DW_HDMI_RES_MAX]; };
-struct dw_hdmi_sym_term { +struct dw_hdmi_phy_config { unsigned long mpixelclock; u16 sym_ctr; /*clock symbol and transmitter control*/ u16 term; /*transmission termination value*/ + u16 vlev_ctr; /* voltage level control */ };
struct dw_hdmi_audio_data { @@ -63,7 +64,7 @@ struct dw_hdmi_plat_data { enum dw_hdmi_devtype dev_type; const struct dw_hdmi_mpll_config *mpll_cfg; const struct dw_hdmi_curr_ctrl *cur_ctr; - const struct dw_hdmi_sym_term *sym_term; + const struct dw_hdmi_phy_config *phy_config; enum drm_mode_status (*mode_valid)(struct drm_connector *connector, struct drm_display_mode *mode); };
On Mon, Mar 09, 2015 at 05:42:21PM +0800, Yakir Yang wrote:
RK3288 hdmi eye-diagram test would fail when pixel clock is 148.5MHz, and single-ended test would failed when display mode is 74.25MHz.
Has anyone reviewed these changes yet? I don't see any replies, nor are they in David's git tree. To me, they look mostly fine - the only issue I get is that the final patch doesn't apply cleanly to dw_hdmi.h since they're generated against a tree which has audio support merged. I also see no regressions on iMX6, so I think they can be merged.
Unless anyone has any objections, I'll add these to my queue for David.
Thanks.
Hi Russell,
在 2015/4/1 0:25, Russell King - ARM Linux 写道:
On Mon, Mar 09, 2015 at 05:42:21PM +0800, Yakir Yang wrote:
RK3288 hdmi eye-diagram test would fail when pixel clock is 148.5MHz, and single-ended test would failed when display mode is 74.25MHz.
Has anyone reviewed these changes yet? I don't see any replies, nor are they in David's git tree. To me, they look mostly fine - the only issue I get is that the final patch doesn't apply cleanly to dw_hdmi.h since they're generated against a tree which has audio support merged. I also see no regressions on iMX6, so I think they can be merged.
Unless anyone has any objections, I'll add these to my queue for David.
Thanks.
Wooh, thanks, I will send v4 now to improve the "drm: dw_hdmi/dw_hdmi-rockchip".
Best regards, Yakir Yang
dri-devel@lists.freedesktop.org
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Russell King - ARM Linux -
Yakir -
Yakir Yang