From: Krishna Manikandan quic_mkrishn@quicinc.com

Add DSI controller and PHY nodes for sc7280.

Signed-off-by: Rajeev Nandan quic_rajeevny@quicinc.com Signed-off-by: Krishna Manikandan quic_mkrishn@quicinc.com Reviewed-by: Matthias Kaehlcke mka@chromium.org Reviewed-by: Stephen Boyd swboyd@chromium.org Signed-off-by: Sankeerth Billakanti quic_sbillaka@quicinc.com ---

Changes in v4: None

Changes in v3: - Add the dsi_phy clocks (Kuogee Hsieh) - One clock cell per line (Stephen Boyd)

Changes in v2: - Drop flags from interrupts (Stephen Boyd) - Rename dsi-opp-table (Stephen Boyd) - Rename dsi phy node (Stephen Boyd)

arch/arm64/boot/dts/qcom/sc7280.dtsi | 111 ++++++++++++++++++++++++++++++++++- 1 file changed, 109 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index a4536b6..12c4d32 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2691,8 +2691,14 @@ reg = <0 0xaf00000 0 0x20000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_DISP_GPLL0_CLK_SRC>, - <0>, <0>, <0>, <0>, <0>, <0>; - clock-names = "bi_tcxo", "gcc_disp_gpll0_clk", + <&dsi_phy 0>, + <&dsi_phy 1>, + <0>, + <0>, + <0>, + <0>; + clock-names = "bi_tcxo", + "gcc_disp_gpll0_clk", "dsi0_phy_pll_out_byteclk", "dsi0_phy_pll_out_dsiclk", "dp_phy_pll_link_clk", @@ -2768,6 +2774,18 @@

status = "disabled";

+ ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + mdp_opp_table: opp-table { compatible = "operating-points-v2";

@@ -2792,6 +2810,95 @@ }; }; }; + + dsi0: dsi@ae94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SC7280_CX>; + + phys = <&dsi_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + + dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + dsi_phy: phy@ae94400 { + compatible = "qcom,sc7280-dsi-phy-7nm"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94900 0 0x280>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; };

pdc: interrupt-controller@b220000 {

Add edp controller and phy DT nodes for sc7280.

Signed-off-by: Krishna Manikandan quic_mkrishn@quicinc.com Reviewed-by: Stephen Boyd swboyd@chromium.org Signed-off-by: Sankeerth Billakanti quic_sbillaka@quicinc.com ---

Changes in v4: None

Changes in v3: - Add one clock cell per line (Stephen Boyd) - Unit address should match first reg property (Stephen Boyd) - Remove new line (Stephen Boyd) - Add the dsi_phy clocks in dispcc (Kuogee Hsieh)

Changes in v2: - Move regulator definitions to board file (Matthias Kaehlcke) - Move the gpio definitions to board file (Matthias Kaehlcke) - Move the pinconf to board file (Matthias Kaehlcke) - Move status property (Stephen Boyd) - Drop flags from interrupts (Stephen Boyd) - Add clock names one per line for readability (Stephen Boyd) - Rename edp-opp-table (Stephen Boyd)

arch/arm64/boot/dts/qcom/sc7280.dtsi | 107 ++++++++++++++++++++++++++++++++++- 1 file changed, 105 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 12c4d32..5ad500e 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2695,8 +2695,8 @@ <&dsi_phy 1>, <0>, <0>, - <0>, - <0>; + <&edp_phy 0>, + <&edp_phy 1>; clock-names = "bi_tcxo", "gcc_disp_gpll0_clk", "dsi0_phy_pll_out_byteclk", @@ -2784,6 +2784,13 @@ remote-endpoint = <&dsi0_in>; }; }; + + port@1 { + reg = <1>; + dpu_intf5_out: endpoint { + remote-endpoint = <&edp_in>; + }; + }; };

mdp_opp_table: opp-table { @@ -2899,6 +2906,102 @@

status = "disabled"; }; + + msm_edp: edp@aea0000 { + compatible = "qcom,sc7280-edp"; + + reg = <0 0xaea0000 0 0x200>, + <0 0xaea0200 0 0x200>, + <0 0xaea0400 0 0xc00>, + <0 0xaea1000 0 0x400>; + + interrupt-parent = <&mdss>; + interrupts = <14>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_EDP_CLKREF_EN>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; + clock-names = "core_xo", + "core_ref", + "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + #clock-cells = <1>; + assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; + assigned-clock-parents = <&edp_phy 0>, <&edp_phy 1>; + + phys = <&edp_phy>; + phy-names = "dp"; + + operating-points-v2 = <&edp_opp_table>; + power-domains = <&rpmhpd SC7280_CX>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + edp_in: endpoint { + remote-endpoint = <&dpu_intf5_out>; + }; + }; + }; + + edp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + edp_phy: phy@aec2a00 { + compatible = "qcom,sc7280-edp-phy"; + + reg = <0 0xaec2a00 0 0x19c>, + <0 0xaec2200 0 0xa0>, + <0 0xaec2600 0 0xa0>, + <0 0xaec2000 0 0x1c0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_EDP_CLKREF_EN>; + clock-names = "aux", + "cfg_ahb"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; };

pdc: interrupt-controller@b220000 {

On Mon 22 Nov 05:26 CST 2021, Sankeerth Billakanti wrote:

From: Krishna Manikandan quic_mkrishn@quicinc.com

Add mdss and mdp DT nodes for sc7280.

Signed-off-by: Krishna Manikandan quic_mkrishn@quicinc.com Reported-by: kernel test robot lkp@intel.com Reviewed-by: Stephen Boyd swboyd@chromium.org Reported-by: kernel test robot lkp@intel.com Signed-off-by: Sankeerth Billakanti quic_sbillaka@quicinc.com

---

Changes in v4: None

Changes in v3: None

Changes in v2: - Rename display dt nodes (Stephen Boyd) - Add clock names one per line for readability (Stephen Boyd)

arch/arm64/boot/dts/qcom/sc7280.dtsi | 90 ++++++++++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 365a2e0..a4536b6 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2704,6 +2704,96 @@ #power-domain-cells = <1>; };

• mdss: display-subsystem@ae00000 {
  

• 	compatible = "qcom,sc7280-mdss";
  

• 	reg = <0 0x0ae00000 0 0x1000>;
  

• 	reg-names = "mdss";
  

• 	power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
  

• 	clocks = <&gcc GCC_DISP_AHB_CLK>,
  

• 		 <&dispcc DISP_CC_MDSS_AHB_CLK>,
  

• 		<&dispcc DISP_CC_MDSS_MDP_CLK>;
  

• 	clock-names = "iface",
  

• 		      "ahb",
  

• 		      "core";
  

• 	assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
  

• 	assigned-clock-rates = <300000000>;
  

• 	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
  

• 	interrupt-controller;
  

• 	#interrupt-cells = <1>;
  

• 	interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
  

• 	interconnect-names = "mdp0-mem";
  

• 	iommus = <&apps_smmu 0x900 0x402>;
  

• 	#address-cells = <2>;
  

• 	#size-cells = <2>;
  

• 	ranges;
  

• 	status = "disabled";
  

• 	mdp: display-controller@ae01000 {
  

I believe the only reason to give this a label is so that you can enable it in the dts. But I don't see the point of having it status disabled, given that it should always follow the mdss node's status.

• 		compatible = "qcom,sc7280-dpu";
  

• 		reg = <0 0x0ae01000 0 0x8f030>,
  

• 			<0 0x0aeb0000 0 0x2008>;
  

• 		reg-names = "mdp", "vbif";
  

• 		clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
  

• 			<&gcc GCC_DISP_SF_AXI_CLK>,
  

• 			<&dispcc DISP_CC_MDSS_AHB_CLK>,
  

• 			<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
  

• 			<&dispcc DISP_CC_MDSS_MDP_CLK>,
  

• 			<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
  

• 		clock-names = "bus",
  

• 			      "nrt_bus",
  

• 			      "iface",
  

• 			      "lut",
  

• 			      "core",
  

• 			      "vsync";
  

• 		assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
  

• 				<&dispcc DISP_CC_MDSS_VSYNC_CLK>,
  

• 				<&dispcc DISP_CC_MDSS_AHB_CLK>;
  

• 		assigned-clock-rates = <300000000>,
  

• 					<19200000>,
  

• 					<19200000>;
  

• 		operating-points-v2 = <&mdp_opp_table>;
  

• 		power-domains = <&rpmhpd SC7280_CX>;
  

• 		interrupt-parent = <&mdss>;
  

• 		interrupts = <0>;
  

• 		status = "disabled";
  

So my suggestion is to drop this and drop the label.

If not, please change the label of this node to mdss_mdp, for sorting purposes.

Thanks, Bjorn

• 		mdp_opp_table: opp-table {
  

• 			compatible = "operating-points-v2";
  

• 			opp-200000000 {
  

• 				opp-hz = /bits/ 64 <200000000>;
  

• 				required-opps = <&rpmhpd_opp_low_svs>;
  

• 			};
  

• 			opp-300000000 {
  

• 				opp-hz = /bits/ 64 <300000000>;
  

• 				required-opps = <&rpmhpd_opp_svs>;
  

• 			};
  

• 			opp-380000000 {
  

• 				opp-hz = /bits/ 64 <380000000>;
  

• 				required-opps = <&rpmhpd_opp_svs_l1>;
  

• 			};
  

• 			opp-506666667 {
  

• 				opp-hz = /bits/ 64 <506666667>;
  

• 				required-opps = <&rpmhpd_opp_nom>;
  

• 			};
  

• 		};
  

• 	};
  

• };
  

• pdc: interrupt-controller@b220000 { compatible = "qcom,sc7280-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>;

-- 2.7.4