Hey,

On 26-09-14 12:00, Lauri Peltonen wrote:

Do not attach fences automatically to buffers that are marked for explicit synchronization.

Signed-off-by: Lauri Peltonen lpeltonen@nvidia.com

drm/nouveau_bo.c | 8 ++++---- drm/nouveau_bo.h | 4 ++-- drm/nouveau_drm.c | 1 + drm/nouveau_gem.c | 47 +++++++++++++++++++++++++++++++++++++++------- drm/nouveau_gem.h | 6 ++++-- drm/nouveau_ttm.c | 8 ++++---- drm/nv50_display.c | 2 +- drm/uapi/drm/nouveau_drm.h | 5 ++++- 8 files changed, 60 insertions(+), 21 deletions(-)

Considering this will break on eviction, is it really needed? If a fence is waited on before starting an operation synchronization will be a noop.

~Maarten

On Mon, Sep 29, 2014 at 09:46:48AM +0200, Daniel Vetter wrote:

On Fri, Sep 26, 2014 at 01:00:12PM +0300, Lauri Peltonen wrote:

...

Allow user space to provide an explicit sync fence fd when exporting a dma-buf from gem handle. The fence will be stored as the explicit fence to the reservation object.

Signed-off-by: Lauri Peltonen lpeltonen@nvidia.com

All existing userspace treats dma_bufs as long-lived objects. Well, all the userspace that expects implicit syncing, afaik Android shovels lots of dma-bufs around all the time (since ion is using them as it's native buffer handles).

So adding an exclusive fence once at export time isn't going to be terribly useful.

So I think a better approach would be to add this as ioctls to the dma-buf fd itself. Then you can also add a "give me the fence(s) for this dma_buf" ioctl, which is useful for interop the other way round (i.e. implicit -> explicit).

Yes, I like this. I thought that one could support long-lived dma-bufs by doing a "re-export" when a new fence needs to be attached, but your model is indeed much nicer!

On Sat, Sep 27, 2014 at 08:49:39AM +0200, Maarten Lankhorst wrote:

This is never true. A default resv gets allocated, see dma_buf's create function.

Ah, ok. I'll keep that in mind when writing new versions. :-)

Thanks, Lauri

On Mon, Sep 29, 2014 at 09:43:02AM +0200, Daniel Vetter wrote:

On Fri, Sep 26, 2014 at 01:00:05PM +0300, Lauri Peltonen wrote:

...

Hi guys,

I'd like to start a new thread about explicit fence synchronization. This time with a Nouveau twist. :-)

First, let me define what I understand by implicit/explicit sync:

Implicit synchronization

• Fences are attached to buffers
• Kernel manages fences automatically based on buffer read/write access

Explicit synchronization

• Fences are passed around independently
• Kernel takes and emits fences to/from user space when submitting work

Implicit synchronization is already implemented in open source drivers, and works well for most use cases. I don't seek to change any of that. My proposal aims at allowing some drm drivers to operate in explicit sync mode to get maximal performance, while still remaining fully compatible with the implicit paradigm.

Yeah, pretty much what we have in mind on the i915 side too. I didn't look too closely at your patches, so just a few high level comments on your rfc here.

...

I will try to explain why I think we should support the explicit model as well.

1. Bindless graphics

Bindless graphics is a central concept when trying to reduce the OpenGL driver overhead. The idea is that the application can bind a large set of buffers to the working set up front using extensions such as GL_ARB_bindless_texture, and they remain resident until the application releases them (note that compute APIs have typically similar semantics). These working sets can be huge, hundreds or even thousands of buffers, so we would like to opt out from the per-submit overhead of acquiring locks, waiting for fences, and storing fences. Automatically synchronizing these working sets in kernel will also prevent parallelism between channels that are sharing the working set (in fact sharing just one buffer from the working set will cause the jobs of the two channels to be serialized).

2. Evolution of graphics APIs

The graphics API evolution seems to be going to a direction where game engine and middleware vendors demand more control over work submission and synchronization. We expect that this trend will continue, and more and more synchronization decisions will be pushed to the API level. OpenGL and EGL already provide good explicit command stream level synchronization primitives: glFenceSync and EGL_KHR_wait_sync. Their use is also encouraged - for example EGL_KHR_image_base spec clearly states that the application is responsible for synchronizing accesses to EGLImages. If the API that is exposed to developers gives the control over synchronization to the developer, then implicit waits that are inserted by the kernel are unnecessary and unexpected, and can severely hurt performance. It also makes it easy for the developer to write code that happens to work on Linux because of implicit sync, but will fail on other platforms.

3. Suballocation

Using user space suballocation can help reduce the overhead when a large number of small textures are used. Synchronizing suballocated surfaces implicitly in kernel doesn't make sense - many channels should be able to access the same kernel-level buffer object simultaneously.

4. Buffer sharing complications

This is not really an argument for explicit sync as such, but I'd like to point out that sharing buffers across SoC engines is often much more complex than just exporting and importing a dma-buf and waiting for the dma-buf fences. Sometimes we need to do color format or tiling layout conversion. Sometimes, at least on Tegra, we need to decompress buffers when we pass them from the GPU to an engine that doesn't support framebuffer compression. These things are not uncommon, particularly when we have SoC's that combine licensed IP blocks from different vendors. My point is that user space is already heavily involved when sharing buffers between drivers, and giving it some more control over synchronization is not adding that much complexity.

Because of the above arguments, I think it makes sense to let some user space drm drivers opt out from implicit synchronization, while allowing them to still remain fully compatible with the rest of the drm world that uses implicit synchronization. In practice, this would require three things:

(1) Support passing fences (that are not tied to buffer objects) between kernel and user space.

(2) Stop automatically storing fences to the buffers that user space wants to synchronize explicitly.

The problem with this approach is that you then need hw faulting to make sure the memory is there. Implicit fences aren't just used for syncing, but also to make sure that the gpu still has access to the buffer as long as it needs it. So you need at least a non-exclusive fence attached for each command submission.

Of course on Android you don't have swap (would kill the puny mmc within seconds) and you don't care for letting userspace pin most of memory for gfx. So you'll get away with no fences at all. But for upstream I don't see a good solution unfortunately. Ideas very much welcome.

Well i am gonna repeat myself. But yes you can do explicit without associating fence (at least no struct alloc) just associate a unique per command stream number and have it be global ie irrespective of different execution pipeline your hw have.

For non scheduling GPU, today generation roughly, you keep buffer on lru and you know you can not evict buffer to swap for those that have an active id (hw did not yet write the sequence number back). You update the lru with each command stream ioctl.

For binding to GPU GART you can do that as a preamble to the command stream which most hardware (AMD, Intel, NVidia) should be able to do.

For VRAM you have several choice that depends on how you want to manage VRAM. For instance you might want to use it more like a cache and have each command stream preamble with a bunch of copy to VRAM and posibly bunch of post copy back to RAM. Or you can hold to current scheme but buffer move now becomes preamble to command stream (ie buffer move are scheduled as a preamble to command stream).

So i do not see what you would consider rocket science about this ?

Cheers, Jérôme

...

(3) Allow user space to attach an explicit fence to dma-buf when exporting to another driver that uses implicit sync.

There are still some open issues beyond these. For example, can we skip acquiring the ww mutex for explicitly synchronized buffers? I think we could eventually, at least on unified memory systems where we don't need to migrate between heaps (our downstream Tegra GPU driver does not lock any buffers at submit, it just grabs refcounts for hw). Another quirk is that now Nouveau waits on the buffer fences when closing the gem object to ensure that it doesn't unmap too early. We need to rework that for explicit sync, but that shouldn't be difficult.

See above, but you can't avoid to attach fences as long as we still use a buffer-object based gfx memory management model. At least afaics. Which means you need the ordering guarantees imposed by ww mutexes to ensure that the oddball implicit ordered client can't deadlock the kernel's memory management code.

...

I have written a prototype that demonstrates (1) by adding explicit sync fd support to Nouveau. It's not a lot of code, because I only use a relatively small subset of the android sync driver functionality. Thanks to Maarten's rewrite, all I need to do is to allow creating a sync_fence from a drm fence in order to pass it to user space. I don't need to use sync_pt or sync_timeline, or fill in sync_timeline_ops.

I can see why the upstream has been reluctant to de-stage the android sync driver in its current form, since (even though it now builds on struct fence) it still duplicates some of the drm fence concepts. I'd like to think that my patches only use the parts of the android sync driver that genuinely are missing from the drm fence model: allowing user space to operate on fence objects that are independent of buffer objects.

Imo de-staging the android syncpt stuff needs to happen first, before drivers can use it. Since non-staging stuff really shouldn't depend upon code from staging.

...

The last two patches are mocks that show how (2) and (3) might work out. I haven't done any testing with them yet. Before going any further, I'd like to get your feedback. Can you see the benefits of explicit sync as an alternative synchronization model? Do you think we could use the android sync_fence for passing fences between user space? Or did you have something else in mind for explicit sync in the drm world?

I'm all for adding explicit syncing. Our plans are roughly.

• Add both an in and and out fence to execbuf to sync with other rendering and give userspace a fence back. Needs to different flags probably.

• Maybe add an ioctl to dma-bufs to get at the current implicit fences attached to them (both an exclusive and non-exclusive version). This should help with making explicit and implicit sync work together nicely.

• Add fence support to kms. Probably only worth it together with the new atomic stuff. Again we need an in fence to wait for (one for each buffer) and an out fence. The later can easily be implemented by extending struct drm_event, which means not a single driver code line needs to be changed for this.

• For de-staging android syncpts we need to de-clutter the internal interfaces and also review all the ioctls exposed. Like you say it should be just the userspace interface for struct drm_fence. Also, it needs testcases and preferrably manpages.

Unfortunately it looks like Intel won't do this all for you due to a bunch of hilarious internal reasons :( At least not anytime soon.

Cheers, Daniel

Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel

On 9/29/14 8:42 AM, Jerome Glisse wrote:

On Mon, Sep 29, 2014 at 09:43:02AM +0200, Daniel Vetter wrote:

...

On Fri, Sep 26, 2014 at 01:00:05PM +0300, Lauri Peltonen wrote:

...

Hi guys,

I'd like to start a new thread about explicit fence synchronization. This time with a Nouveau twist. :-)

First, let me define what I understand by implicit/explicit sync:

Implicit synchronization

• Fences are attached to buffers
• Kernel manages fences automatically based on buffer read/write access

Explicit synchronization

• Fences are passed around independently
• Kernel takes and emits fences to/from user space when submitting work

Implicit synchronization is already implemented in open source drivers, and works well for most use cases. I don't seek to change any of that. My proposal aims at allowing some drm drivers to operate in explicit sync mode to get maximal performance, while still remaining fully compatible with the implicit paradigm.

Yeah, pretty much what we have in mind on the i915 side too. I didn't look too closely at your patches, so just a few high level comments on your rfc here.

...

I will try to explain why I think we should support the explicit model as well.

1. Bindless graphics

Bindless graphics is a central concept when trying to reduce the OpenGL driver overhead. The idea is that the application can bind a large set of buffers to the working set up front using extensions such as GL_ARB_bindless_texture, and they remain resident until the application releases them (note that compute APIs have typically similar semantics). These working sets can be huge, hundreds or even thousands of buffers, so we would like to opt out from the per-submit overhead of acquiring locks, waiting for fences, and storing fences. Automatically synchronizing these working sets in kernel will also prevent parallelism between channels that are sharing the working set (in fact sharing just one buffer from the working set will cause the jobs of the two channels to be serialized).

2. Evolution of graphics APIs

The graphics API evolution seems to be going to a direction where game engine and middleware vendors demand more control over work submission and synchronization. We expect that this trend will continue, and more and more synchronization decisions will be pushed to the API level. OpenGL and EGL already provide good explicit command stream level synchronization primitives: glFenceSync and EGL_KHR_wait_sync. Their use is also encouraged - for example EGL_KHR_image_base spec clearly states that the application is responsible for synchronizing accesses to EGLImages. If the API that is exposed to developers gives the control over synchronization to the developer, then implicit waits that are inserted by the kernel are unnecessary and unexpected, and can severely hurt performance. It also makes it easy for the developer to write code that happens to work on Linux because of implicit sync, but will fail on other platforms.

3. Suballocation

Using user space suballocation can help reduce the overhead when a large number of small textures are used. Synchronizing suballocated surfaces implicitly in kernel doesn't make sense - many channels should be able to access the same kernel-level buffer object simultaneously.

4. Buffer sharing complications

This is not really an argument for explicit sync as such, but I'd like to point out that sharing buffers across SoC engines is often much more complex than just exporting and importing a dma-buf and waiting for the dma-buf fences. Sometimes we need to do color format or tiling layout conversion. Sometimes, at least on Tegra, we need to decompress buffers when we pass them from the GPU to an engine that doesn't support framebuffer compression. These things are not uncommon, particularly when we have SoC's that combine licensed IP blocks from different vendors. My point is that user space is already heavily involved when sharing buffers between drivers, and giving it some more control over synchronization is not adding that much complexity.

Because of the above arguments, I think it makes sense to let some user space drm drivers opt out from implicit synchronization, while allowing them to still remain fully compatible with the rest of the drm world that uses implicit synchronization. In practice, this would require three things:

(1) Support passing fences (that are not tied to buffer objects) between kernel and user space.

(2) Stop automatically storing fences to the buffers that user space wants to synchronize explicitly.

The problem with this approach is that you then need hw faulting to make sure the memory is there. Implicit fences aren't just used for syncing, but also to make sure that the gpu still has access to the buffer as long as it needs it. So you need at least a non-exclusive fence attached for each command submission.

Of course on Android you don't have swap (would kill the puny mmc within seconds) and you don't care for letting userspace pin most of memory for gfx. So you'll get away with no fences at all. But for upstream I don't see a good solution unfortunately. Ideas very much welcome.

Well i am gonna repeat myself. But yes you can do explicit without associating fence (at least no struct alloc) just associate a unique per command stream number and have it be global ie irrespective of different execution pipeline your hw have.

For non scheduling GPU, today generation roughly, you keep buffer on lru and you know you can not evict buffer to swap for those that have an active id (hw did not yet write the sequence number back). You update the lru with each command stream ioctl.

For binding to GPU GART you can do that as a preamble to the command stream which most hardware (AMD, Intel, NVidia) should be able to do.

For VRAM you have several choice that depends on how you want to manage VRAM. For instance you might want to use it more like a cache and have each command stream preamble with a bunch of copy to VRAM and posibly bunch of post copy back to RAM. Or you can hold to current scheme but buffer move now becomes preamble to command stream (ie buffer move are scheduled as a preamble to command stream).

Additionally, I think the goal is to move to a model where some higher-level object such as a working set, rather than individual buffers, are assigned counters or sync primitives on a per-submission basis. Versioning off tags for individual buffers then moves to working set modification time. This is more feasible if the only thing that needs precise fencing of individual surfaces is lifetime management.

The trend seems to be towards establishing a relatively large working set up front and then submitting many command buffers against it, perhaps with incremental modifications to the working set along the way. This may be what's referred to as the Android model above, but I view it as the "non-glitchy graphic" model going forward.

Thanks, -James

So i do not see what you would consider rocket science about this ?

Cheers, Jérôme

...

...

(3) Allow user space to attach an explicit fence to dma-buf when exporting to another driver that uses implicit sync.

There are still some open issues beyond these. For example, can we skip acquiring the ww mutex for explicitly synchronized buffers? I think we could eventually, at least on unified memory systems where we don't need to migrate between heaps (our downstream Tegra GPU driver does not lock any buffers at submit, it just grabs refcounts for hw). Another quirk is that now Nouveau waits on the buffer fences when closing the gem object to ensure that it doesn't unmap too early. We need to rework that for explicit sync, but that shouldn't be difficult.

See above, but you can't avoid to attach fences as long as we still use a buffer-object based gfx memory management model. At least afaics. Which means you need the ordering guarantees imposed by ww mutexes to ensure that the oddball implicit ordered client can't deadlock the kernel's memory management code.

...

I have written a prototype that demonstrates (1) by adding explicit sync fd support to Nouveau. It's not a lot of code, because I only use a relatively small subset of the android sync driver functionality. Thanks to Maarten's rewrite, all I need to do is to allow creating a sync_fence from a drm fence in order to pass it to user space. I don't need to use sync_pt or sync_timeline, or fill in sync_timeline_ops.

I can see why the upstream has been reluctant to de-stage the android sync driver in its current form, since (even though it now builds on struct fence) it still duplicates some of the drm fence concepts. I'd like to think that my patches only use the parts of the android sync driver that genuinely are missing from the drm fence model: allowing user space to operate on fence objects that are independent of buffer objects.

Imo de-staging the android syncpt stuff needs to happen first, before drivers can use it. Since non-staging stuff really shouldn't depend upon code from staging.

...

The last two patches are mocks that show how (2) and (3) might work out. I haven't done any testing with them yet. Before going any further, I'd like to get your feedback. Can you see the benefits of explicit sync as an alternative synchronization model? Do you think we could use the android sync_fence for passing fences between user space? Or did you have something else in mind for explicit sync in the drm world?

I'm all for adding explicit syncing. Our plans are roughly.

• Add both an in and and out fence to execbuf to sync with other rendering and give userspace a fence back. Needs to different flags probably.

• Maybe add an ioctl to dma-bufs to get at the current implicit fences attached to them (both an exclusive and non-exclusive version). This should help with making explicit and implicit sync work together nicely.

• Add fence support to kms. Probably only worth it together with the new atomic stuff. Again we need an in fence to wait for (one for each buffer) and an out fence. The later can easily be implemented by extending struct drm_event, which means not a single driver code line needs to be changed for this.

• For de-staging android syncpts we need to de-clutter the internal interfaces and also review all the ioctls exposed. Like you say it should be just the userspace interface for struct drm_fence. Also, it needs testcases and preferrably manpages.

Unfortunately it looks like Intel won't do this all for you due to a bunch of hilarious internal reasons :( At least not anytime soon.

Cheers, Daniel

Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel

Thanks Daniel for your input!

On Mon, Sep 29, 2014 at 09:43:02AM +0200, Daniel Vetter wrote:

On Fri, Sep 26, 2014 at 01:00:05PM +0300, Lauri Peltonen wrote:

...

(2) Stop automatically storing fences to the buffers that user space wants to synchronize explicitly.

The problem with this approach is that you then need hw faulting to make sure the memory is there. Implicit fences aren't just used for syncing, but also to make sure that the gpu still has access to the buffer as long as it needs it. So you need at least a non-exclusive fence attached for each command submission.

Of course on Android you don't have swap (would kill the puny mmc within seconds) and you don't care for letting userspace pin most of memory for gfx. So you'll get away with no fences at all. But for upstream I don't see a good solution unfortunately. Ideas very much welcome.

...

(3) Allow user space to attach an explicit fence to dma-buf when exporting to another driver that uses implicit sync.

There are still some open issues beyond these. For example, can we skip acquiring the ww mutex for explicitly synchronized buffers? I think we could eventually, at least on unified memory systems where we don't need to migrate between heaps (our downstream Tegra GPU driver does not lock any buffers at submit, it just grabs refcounts for hw). Another quirk is that now Nouveau waits on the buffer fences when closing the gem object to ensure that it doesn't unmap too early. We need to rework that for explicit sync, but that shouldn't be difficult.

See above, but you can't avoid to attach fences as long as we still use a buffer-object based gfx memory management model. At least afaics. Which means you need the ordering guarantees imposed by ww mutexes to ensure that the oddball implicit ordered client can't deadlock the kernel's memory management code.

Implicit fences attached to individual buffers are one way for residency management. Do you think a working set based model could work in the DRM framework? For example, something like this:

- Allow user space to create "working set objects" and associate buffers with them. If the user space doesn't want to manage working sets explicitly, it could also use an implicit default working set that contains all buffers that are mapped to the channel vm (on Android we could always use the default working set since we don't need to manage residency). The working sets are initially marked as dirty. - User space tells which working sets are referenced by each work submission. Kernel locks these working sets, pins all buffers in dirty working sets, and resets the dirty bits. After kicking off work, kernel stores the fence to the _working sets_, and then releases the locks (if an implicit default working set is used, then this would be roughly equivalent to storing a fence to channel vm that tells "this is the last hw operation that might have touched buffers in this address space"). - If swapping doesn't happen, then we just need to check the working set dirty bits at each submit. - When a buffer is swapped out, all working sets that refer to it need to be marked as dirty. - When a buffer is swapped out or unmapped, we need to wait for the fences from all working sets that refer to the buffer.

Initially one might think of working sets as a mere optimization - we now need to process a few working sets at every submit instead of many individual buffers. However, it makes a huge difference because of fences: fences that are attached to buffers are used for implicitly synchronizing work across different channels and engines. They are in the performance critical path, and we want to carefully manage them (that's the idea of explicit synchronization). The working set fences, on the other hand, would only be used to guarantee that we don't swap out or unmap something that the GPU might be accessing. We never need to wait for those fences (except when swapping or unmapping), so we can be conservative without hurting performance.

Imo de-staging the android syncpt stuff needs to happen first, before drivers can use it. Since non-staging stuff really shouldn't depend upon code from staging.

Fully agree. I thought the best way towards that would be to show some driver code that _would_ use it. :)

I'm all for adding explicit syncing. Our plans are roughly. - Add both an in and and out fence to execbuf to sync with other rendering and give userspace a fence back. Needs to different flags probably.

• Maybe add an ioctl to dma-bufs to get at the current implicit fences attached to them (both an exclusive and non-exclusive version). This should help with making explicit and implicit sync work together nicely.

• Add fence support to kms. Probably only worth it together with the new atomic stuff. Again we need an in fence to wait for (one for each buffer) and an out fence. The later can easily be implemented by extending struct drm_event, which means not a single driver code line needs to be changed for this.

• For de-staging android syncpts we need to de-clutter the internal interfaces and also review all the ioctls exposed. Like you say it should be just the userspace interface for struct drm_fence. Also, it needs testcases and preferrably manpages.

This all sounds very similar to what we'd like to do! Maybe we can move forward with these parts, and continue to attach fences at submit until we have a satisfactory solution for the pinning problem?

I'd like to understand what are the concrete steps to de-stage struct sync_fence, since that's the first thing that needs to be done. For example, what do you mean by "de-cluttering the internal interfaces"? Just that we'd move the sync_fence parts from drivers/staging/android/sync.c to, say, drivers/dma-buf/sync-fence.c ? Would we still leave a copy of the existing full driver to staging/android?

Thanks, Lauri

On Wed, Oct 01, 2014 at 06:14:16PM +0300, Lauri Peltonen wrote:

Thanks Daniel for your input!

On Mon, Sep 29, 2014 at 09:43:02AM +0200, Daniel Vetter wrote:

...

On Fri, Sep 26, 2014 at 01:00:05PM +0300, Lauri Peltonen wrote:

...

(2) Stop automatically storing fences to the buffers that user space wants to synchronize explicitly.

The problem with this approach is that you then need hw faulting to make sure the memory is there. Implicit fences aren't just used for syncing, but also to make sure that the gpu still has access to the buffer as long as it needs it. So you need at least a non-exclusive fence attached for each command submission.

Of course on Android you don't have swap (would kill the puny mmc within seconds) and you don't care for letting userspace pin most of memory for gfx. So you'll get away with no fences at all. But for upstream I don't see a good solution unfortunately. Ideas very much welcome.

...

(3) Allow user space to attach an explicit fence to dma-buf when exporting to another driver that uses implicit sync.

There are still some open issues beyond these. For example, can we skip acquiring the ww mutex for explicitly synchronized buffers? I think we could eventually, at least on unified memory systems where we don't need to migrate between heaps (our downstream Tegra GPU driver does not lock any buffers at submit, it just grabs refcounts for hw). Another quirk is that now Nouveau waits on the buffer fences when closing the gem object to ensure that it doesn't unmap too early. We need to rework that for explicit sync, but that shouldn't be difficult.

See above, but you can't avoid to attach fences as long as we still use a buffer-object based gfx memory management model. At least afaics. Which means you need the ordering guarantees imposed by ww mutexes to ensure that the oddball implicit ordered client can't deadlock the kernel's memory management code.

Implicit fences attached to individual buffers are one way for residency management. Do you think a working set based model could work in the DRM framework? For example, something like this:

• Allow user space to create "working set objects" and associate buffers with them. If the user space doesn't want to manage working sets explicitly, it could also use an implicit default working set that contains all buffers that are mapped to the channel vm (on Android we could always use the default working set since we don't need to manage residency). The working sets are initially marked as dirty.
• User space tells which working sets are referenced by each work submission. Kernel locks these working sets, pins all buffers in dirty working sets, and resets the dirty bits. After kicking off work, kernel stores the fence to the _working sets_, and then releases the locks (if an implicit default working set is used, then this would be roughly equivalent to storing a fence to channel vm that tells "this is the last hw operation that might have touched buffers in this address space").
• If swapping doesn't happen, then we just need to check the working set dirty bits at each submit.
• When a buffer is swapped out, all working sets that refer to it need to be marked as dirty.
• When a buffer is swapped out or unmapped, we need to wait for the fences from all working sets that refer to the buffer.

Initially one might think of working sets as a mere optimization - we now need to process a few working sets at every submit instead of many individual buffers. However, it makes a huge difference because of fences: fences that are attached to buffers are used for implicitly synchronizing work across different channels and engines. They are in the performance critical path, and we want to carefully manage them (that's the idea of explicit synchronization). The working set fences, on the other hand, would only be used to guarantee that we don't swap out or unmap something that the GPU might be accessing. We never need to wait for those fences (except when swapping or unmapping), so we can be conservative without hurting performance.

Yeah, within the driver (i.e. for private objects which are never exported to dma_buf) we can recently do stuff like this. And your above idea is roughly one of the things we're tossing around for i915.

But the cool stuff with drm is that cmd submission is driver-specific, so you can just go wild with nouveau. Of course you have to coninvce the nouveau guys (and also have open-source users for the new interface).

For shared buffers I think we should stick with the implicit fences for a while simply because I'm not sure whether it's really worth the fuzz. And reworking all the drivers and dma-buf for some working sets is a lot of fuzz ;-) Like Maarten said you can mostly short-circuit the implicit fencing by only attaching shared fences.

In case you're curious: The idea is to have a 1:1 association between ppgtt address spaces and what you call the working set above, to implement the buffer svm model in ocl2. Mostly because we expect that applications won't get the more fine-grained buffer list right anyway. And this kind of gang-scheduling of working set sizes should be more efficient for the usual case where everything fits.

...

Imo de-staging the android syncpt stuff needs to happen first, before drivers can use it. Since non-staging stuff really shouldn't depend upon code from staging.

Fully agree. I thought the best way towards that would be to show some driver code that _would_ use it. :)

Oh, there's the usual chicken&egg where we need a full-blown prototype before we can start merging. Interface work on upstream is super-hard, but given the ridiculous backwards compat guarantees Linus expects us to keep up totally justified. Mistakes are really expensive. So I'm happy to see you charge ahead here.

...

I'm all for adding explicit syncing. Our plans are roughly. - Add both an in and and out fence to execbuf to sync with other rendering and give userspace a fence back. Needs to different flags probably.

• Maybe add an ioctl to dma-bufs to get at the current implicit fences attached to them (both an exclusive and non-exclusive version). This should help with making explicit and implicit sync work together nicely.

• Add fence support to kms. Probably only worth it together with the new atomic stuff. Again we need an in fence to wait for (one for each buffer) and an out fence. The later can easily be implemented by extending struct drm_event, which means not a single driver code line needs to be changed for this.

• For de-staging android syncpts we need to de-clutter the internal interfaces and also review all the ioctls exposed. Like you say it should be just the userspace interface for struct drm_fence. Also, it needs testcases and preferrably manpages.

This all sounds very similar to what we'd like to do! Maybe we can move forward with these parts, and continue to attach fences at submit until we have a satisfactory solution for the pinning problem?

Yeah, that's our plan for i915 too. First add explicit fences, then figure out whether we need to be better at neutering the implicit fences, in case and only where it really gets in the way.

I'd like to understand what are the concrete steps to de-stage struct sync_fence, since that's the first thing that needs to be done. For example, what do you mean by "de-cluttering the internal interfaces"? Just that we'd move the sync_fence parts from drivers/staging/android/sync.c to, say, drivers/dma-buf/sync-fence.c ? Would we still leave a copy of the existing full driver to staging/android?

Yeah I guess that would be an approach. Personally I think we should also have basic ioctl testcase for all the ioctls exposed by syncpt fds. And reviewing the kerneldoc for the driver-internal interfaces (which includes removing everything that's no made obsolete by struct fence). Bonus points for documenting the ioctls. We could throw the test binary into libdrm maybe, there's a bunch other like it already there.

I'm not sure whether/how much google has already for this.

Aside: Will you be at XDC or linux plumbers? Either would be a perfect place to discuss plans and ideas - I'll attend both.

Cheers, Daniel§

On Thu, Oct 02, 2014 at 05:59:51PM +0300, Lauri Peltonen wrote:

+Rom who seems to be presenting about mainlining android sync at linux plumbers

Also add Greg KH as fyi that we're working on de-stage one of the android subsystems.

On Wed, Oct 01, 2014 at 05:58:52PM +0200, Maarten Lankhorst wrote:

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You could neuter implicit fences by always attaching the fences as shared when explicit syncing is used. This would work correctly with eviction, and wouldn't cause any unneeded syncing. :)

Yes, that will probably work! So, just to reiterate that I understood you and Daniel correctly:

• de-stage sync_fence and it's user space API (the tedious part)
• add dma-buf ioctls for extracting and attaching explicit fences
• Nouveau specific: allow flagging gem buffers for explicit sync
  • do not check pre-fences from explicitly synced buffers at submit
  • continue to attach a shared fence after submit so that pinning and unmapping continue to work

- Have explicit in/out fences for the pushbuf ioctl is missing I guess in this step?

I also think we need some kind of demonstration vehicle using nouveau to satisfy Dave Airlie's open-source userspace requirements for new interfaces. Might be good to chat with him to make sure we have that covered (and how much needs to be there really).

Then working sets and getting rid of locking all buffers individually can be dealt with later as an optimization.

Yeah, sounds like a good plan.

On Wed, Oct 01, 2014 at 07:27:21PM +0200, Daniel Vetter wrote:

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On Wed, Oct 01, 2014 at 06:14:16PM +0300, Lauri Peltonen wrote:

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Implicit fences attached to individual buffers are one way for residency management. Do you think a working set based model could work in the DRM framework? For example, something like this:

• Allow user space to create "working set objects" and associate buffers with them. If the user space doesn't want to manage working sets explicitly, it could also use an implicit default working set that contains all buffers that are mapped to the channel vm (on Android we could always use the default working set since we don't need to manage residency). The working sets are initially marked as dirty.
• User space tells which working sets are referenced by each work submission. Kernel locks these working sets, pins all buffers in dirty working sets, and resets the dirty bits. After kicking off work, kernel stores the fence to the _working sets_, and then releases the locks (if an implicit default working set is used, then this would be roughly equivalent to storing a fence to channel vm that tells "this is the last hw operation that might have touched buffers in this address space").
• If swapping doesn't happen, then we just need to check the working set dirty bits at each submit.
• When a buffer is swapped out, all working sets that refer to it need to be marked as dirty.
• When a buffer is swapped out or unmapped, we need to wait for the fences from all working sets that refer to the buffer.

Initially one might think of working sets as a mere optimization - we now need to process a few working sets at every submit instead of many individual buffers. However, it makes a huge difference because of fences: fences that are attached to buffers are used for implicitly synchronizing work across different channels and engines. They are in the performance critical path, and we want to carefully manage them (that's the idea of explicit synchronization). The working set fences, on the other hand, would only be used to guarantee that we don't swap out or unmap something that the GPU might be accessing. We never need to wait for those fences (except when swapping or unmapping), so we can be conservative without hurting performance.

Yeah, within the driver (i.e. for private objects which are never exported to dma_buf) we can recently do stuff like this. And your above idea is roughly one of the things we're tossing around for i915.

But the cool stuff with drm is that cmd submission is driver-specific, so you can just go wild with nouveau. Of course you have to coninvce the nouveau guys (and also have open-source users for the new interface).

For shared buffers I think we should stick with the implicit fences for a while simply because I'm not sure whether it's really worth the fuzz. And reworking all the drivers and dma-buf for some working sets is a lot of fuzz ;-) Like Maarten said you can mostly short-circuit the implicit fencing by only attaching shared fences.

Yes, I'll try to do that.

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In case you're curious: The idea is to have a 1:1 association between ppgtt address spaces and what you call the working set above, to implement the buffer svm model in ocl2. Mostly because we expect that applications won't get the more fine-grained buffer list right anyway. And this kind of gang-scheduling of working set sizes should be more efficient for the usual case where everything fits.

If I understood correctly, this would be exactly the same as what I called the "default working set" above. On Android we don't care much about finer grained working sets either, because of UMA and no swapping.

Yeah, that's pretty much the idea. Well with ocl the SVM buffer working set sizes are attached to an ocl context, but I don't think there'll be more than one of those around really (except maybe when different libraries all use ocl, but don't work together on the same data).

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Imo de-staging the android syncpt stuff needs to happen first, before drivers can use it. Since non-staging stuff really shouldn't depend upon code from staging.

Fully agree. I thought the best way towards that would be to show some driver code that _would_ use it. :)

Oh, there's the usual chicken&egg where we need a full-blown prototype before we can start merging. Interface work on upstream is super-hard, but given the ridiculous backwards compat guarantees Linus expects us to keep up totally justified. Mistakes are really expensive. So I'm happy to see you charge ahead here.

Given that I'm not used to working with upstream, don't expect too much from my "charging ahead". :) I'm still secretly hoping that the Android guys at Google would jump in to help, now that we seem to agree that we could de-stage sync_fence.

Forget that, imo the android guys are 100% absorbed with their own stuff, at least on the gfx side. Occasionally they pipe up with "btw this is what we're doing now".

Also, the problem is that to actually push android stuff out of staging you need a use-case in upstream, which means an open-source gpu driver. There's not a lot of companies who have both that and ship android, and definitely not the nexus/android lead platforms.

Display side would be easier since there's a bunch of kms drivers now upstream. But given that google decided to go ahead with their own adf instead of drm-kms that's also a non-starter.

Heck, I have a hard time draggin our own android folks here at intel into upstream work ...

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I'm all for adding explicit syncing. Our plans are roughly. - Add both an in and and out fence to execbuf to sync with other rendering and give userspace a fence back. Needs to different flags probably.

• Maybe add an ioctl to dma-bufs to get at the current implicit fences attached to them (both an exclusive and non-exclusive version). This should help with making explicit and implicit sync work together nicely.

• Add fence support to kms. Probably only worth it together with the new atomic stuff. Again we need an in fence to wait for (one for each buffer) and an out fence. The later can easily be implemented by extending struct drm_event, which means not a single driver code line needs to be changed for this.

• For de-staging android syncpts we need to de-clutter the internal interfaces and also review all the ioctls exposed. Like you say it should be just the userspace interface for struct drm_fence. Also, it needs testcases and preferrably manpages.

This all sounds very similar to what we'd like to do! Maybe we can move forward with these parts, and continue to attach fences at submit until we have a satisfactory solution for the pinning problem?

Yeah, that's our plan for i915 too. First add explicit fences, then figure out whether we need to be better at neutering the implicit fences, in case and only where it really gets in the way.

...

I'd like to understand what are the concrete steps to de-stage struct sync_fence, since that's the first thing that needs to be done. For example, what do you mean by "de-cluttering the internal interfaces"? Just that we'd move the sync_fence parts from drivers/staging/android/sync.c to, say, drivers/dma-buf/sync-fence.c ? Would we still leave a copy of the existing full driver to staging/android?

Yeah I guess that would be an approach. Personally I think we should also have basic ioctl testcase for all the ioctls exposed by syncpt fds. And reviewing the kerneldoc for the driver-internal interfaces (which includes removing everything that's no made obsolete by struct fence). Bonus points for documenting the ioctls. We could throw the test binary into libdrm maybe, there's a bunch other like it already there.

I'm not sure whether/how much google has already for this.

The simplest way to add tests is if we allow user space to create and trigger fences. We don't want to enable that from kernel by default, because that opens possibilities for deadlocks (e.g. a process could deadlock a compositor by passing a fence that it never triggers). Android sync driver solves this by having a separate CONFIG_SW_SYNC_USER that can be used for testing.

Here's a simple test by Google: https://android.googlesource.com/platform/system/core/+/master/libsync/sync_...

Hm, usually we expose such test interfaces through debugfs - that way production system won't ever ship with it (since there's too many exploits in there, especially with secure boot). But since you need it for validation tests (at least for the i915 suite) it should always be there when you need it.

Exposing this as a configurable driver in dev is imo a no-go. But we should be able to easily convert this into a few debugfs files, so not too much fuzz hopefully.

And this is their userspace wrapper lib: https://android.googlesource.com/platform/system/core/+/master/libsync/sync.... https://android.googlesource.com/platform/system/core/+/master/libsync/inclu...

Would that go to libdrm now...?

Imo it would make sense. At least we kinda want to use fences outside of Android, and a separate library project feels like overkill.

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Aside: Will you be at XDC or linux plumbers? Either would be a perfect place to discuss plans and ideas - I'll attend both.

I wasn't going to, but let's see. The former is pretty soon and the latter is sold out. At least Andy Ritger from Nvidia is coming to XDC for sure, and he's been involved in our internal discussions around these topics. So I suggest you have a chat with him at least! :)

I'll definitely have a chat (and some beers) with Andy, been a while I've last seen him ;-)

Cheers, Daniel

On Thu, Oct 02, 2014 at 10:44:05PM +0200, Daniel Vetter wrote:

On Thu, Oct 02, 2014 at 05:59:51PM +0300, Lauri Peltonen wrote:

...

Yes, that will probably work! So, just to reiterate that I understood you and Daniel correctly:

• de-stage sync_fence and it's user space API (the tedious part)
• add dma-buf ioctls for extracting and attaching explicit fences
• Nouveau specific: allow flagging gem buffers for explicit sync
  • do not check pre-fences from explicitly synced buffers at submit
  • continue to attach a shared fence after submit so that pinning and unmapping continue to work

- Have explicit in/out fences for the pushbuf ioctl is missing I
  guess in this step?

Yes, I was missing that. :)

I also think we need some kind of demonstration vehicle using nouveau to satisfy Dave Airlie's open-source userspace requirements for new interfaces. Might be good to chat with him to make sure we have that covered (and how much needs to be there really).

Agreed.

Also, the problem is that to actually push android stuff out of staging you need a use-case in upstream, which means an open-source gpu driver. There's not a lot of companies who have both that and ship android, and definitely not the nexus/android lead platforms.

Display side would be easier since there's a bunch of kms drivers now upstream. But given that google decided to go ahead with their own adf instead of drm-kms that's also a non-starter.

Hmm.. Maybe we could use TegraDRM on the display side.. That and Nouveau would already be two upstream drivers that support explicit sync on Tegra K1.

Also, if we bring sync fd's out of staging, one idea would be to add support for EGL_ANDROID_native_fence_sync in mesa, along with some tests. That would demonstrate converting between sync fd's and EGLSync objects.

Hm, usually we expose such test interfaces through debugfs - that way production system won't ever ship with it (since there's too many exploits in there, especially with secure boot). But since you need it for validation tests (at least for the i915 suite) it should always be there when you need it.

Exposing this as a configurable driver in dev is imo a no-go. But we should be able to easily convert this into a few debugfs files, so not too much fuzz hopefully.

Good idea!

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Aside: Will you be at XDC or linux plumbers? Either would be a perfect place to discuss plans and ideas - I'll attend both.

I wasn't going to, but let's see. The former is pretty soon and the latter is sold out. At least Andy Ritger from Nvidia is coming to XDC for sure, and he's been involved in our internal discussions around these topics. So I suggest you have a chat with him at least! :)

I'll definitely have a chat (and some beers) with Andy, been a while I've last seen him ;-)

Change of plans, I'll attend XDC, so see you there! I'll even give a short talk about explicit sync to get some discussions going. :)

Thanks, Lauri