From: Mikita Lipski mikita.lipski@amd.com
Synaptics DP1.4 hubs (BRANCH_ID 0x90CC24) do not support virtual DPCD registers, but do support DSC. The DSC caps can be read from the physical aux, like in SST DSC. These hubs have many different DEVICE_IDs. Add a new quirk to detect this case.
Reviewed-by: Wenjing Liu Wenjing.Liu@amd.com Reviewed-by: Lyude Paul lyude@redhat.com Signed-off-by: David Francis David.Francis@amd.com --- drivers/gpu/drm/drm_dp_helper.c | 2 ++ drivers/gpu/drm/drm_dp_mst_topology.c | 27 +++++++++++++++++++++++++++ include/drm/drm_dp_helper.h | 7 +++++++ 3 files changed, 36 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index af1cd968adfd..02fa8c3d9a82 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -1271,6 +1271,8 @@ static const struct dpcd_quirk dpcd_quirk_list[] = { { OUI(0x00, 0x10, 0xfa), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_NO_PSR) }, /* CH7511 seems to leave SINK_COUNT zeroed */ { OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) }, + /* Synaptics DP1.4 MST hubs can support DSC without virtual DPCD */ + { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) }, };
#undef OUI diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index d8f9ba27b559..d5df02315e14 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c @@ -4222,6 +4222,7 @@ struct drm_dp_aux *drm_dp_mst_dsc_aux_for_port(struct drm_dp_mst_port *port) { struct drm_dp_mst_port *immediate_upstream_port; struct drm_dp_mst_port *fec_port; + struct drm_dp_desc desc = { 0 };
if (!port) return NULL; @@ -4274,6 +4275,32 @@ struct drm_dp_aux *drm_dp_mst_dsc_aux_for_port(struct drm_dp_mst_port *port) if (drm_dp_mst_is_virtual_dpcd(port)) return &port->aux;
+ /* + * Synaptics quirk + * Applies to ports for which: + * - Physical aux has Synaptics OUI + * - DPv1.4 or higher + * - Port is on primary branch device + * - Not a VGA adapter (DP_DWN_STRM_PORT_TYPE_ANALOG) + */ + if (!drm_dp_read_desc(port->mgr->aux, &desc, true)) + return NULL; + + if (drm_dp_has_quirk(&desc, DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) && + port->mgr->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14 && + port->parent == port->mgr->mst_primary) { + u8 downstreamport; + + if (drm_dp_dpcd_read(&port->aux, DP_DOWNSTREAMPORT_PRESENT, + &downstreamport, 1) < 0) + return NULL; + + if ((downstreamport & DP_DWN_STRM_PORT_PRESENT) && + ((downstreamport & DP_DWN_STRM_PORT_TYPE_MASK) + != DP_DWN_STRM_PORT_TYPE_ANALOG)) + return port->mgr->aux; + } + return NULL; } EXPORT_SYMBOL(drm_dp_mst_dsc_aux_for_port); diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 8364502f92cf..a1331b08705f 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -1434,6 +1434,13 @@ enum drm_dp_quirk { * The driver should ignore SINK_COUNT during detection. */ DP_DPCD_QUIRK_NO_SINK_COUNT, + /** + * @DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD: + * + * The device supports MST DSC despite not supporting Virtual DPCD. + * The DSC caps can be read from the physical aux instead. + */ + DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD, };
/**
From: David Francis David.Francis@amd.com
We were using drm helpers to convert a timing into its bandwidth, its bandwidth into pbn, and its pbn into timeslots
These helpers -Did not take DSC timings into account -Used the link rate and lane count of the link's aux device, which are not the same as the link's current cap -Did not take FEC into account (FEC reduces the PBN per timeslot)
For converting timing into PBN, use the new function drm_dp_calc_pbn_mode_dsc that handles the DSC case
For converting PBN into time slots, amdgpu doesn't use the 'correct' atomic method (drm_dp_atomic_find_vcpi_slots), so don't add a new helper to cover our approach. Use the same means of calculating pbn per time slot as the DSC code.
Cc: Jerry Zuo Jerry.Zuo@amd.com Cc: Nicholas Kazlauskas nicholas.kazlauskas@amd.com Signed-off-by: David Francis David.Francis@amd.com --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 5256abe32e92..fc537ae25eeb 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -185,6 +185,7 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( struct drm_dp_mst_topology_mgr *mst_mgr; struct drm_dp_mst_port *mst_port; bool ret; + int pbn_per_timeslot = 0;
aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
@@ -200,6 +201,11 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
if (enable) {
+ /* Convert kilobits per second / 64 (for 64 timeslots) to pbn (54/64 megabytes per second) */ + pbn_per_timeslot = dc_link_bandwidth_kbps( + stream->link, dc_link_get_link_cap(stream->link)) / (8 * 1000 * 54); + aconnector->vcpi_slots = DIV_ROUND_UP(aconnector->pbn, pbn_per_timeslot); + ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, aconnector->pbn, aconnector->vcpi_slots);
From: David Francis David.Francis@amd.com
For DSC MST, sometimes monitors would break out in full-screen static. The issue traced back to the PPS generation code, where these variables were being used uninitialized and were picking up garbage.
memset to 0 to avoid this
Reviewed-by: Nicholas Kazlauskas nicholas.kazlauskas@amd.com Signed-off-by: David Francis David.Francis@amd.com --- drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 3 +++ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 3 +++ 2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c index a519dbc5ecb6..5d6cbaebebc0 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c @@ -496,6 +496,9 @@ bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable) struct dsc_config dsc_cfg; uint8_t dsc_packed_pps[128];
+ memset(&dsc_cfg, 0, sizeof(dsc_cfg)); + memset(dsc_packed_pps, 0, 128); + /* Enable DSC hw block */ dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c index 63eb377ed9c0..296eeff00296 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c @@ -207,6 +207,9 @@ static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const str struct dsc_reg_values dsc_reg_vals; struct dsc_optc_config dsc_optc_cfg;
+ memset(&dsc_reg_vals, 0, sizeof(dsc_reg_vals)); + memset(&dsc_optc_cfg, 0, sizeof(dsc_optc_cfg)); + DC_LOG_DSC("Getting packed DSC PPS for DSC Config:"); dsc_config_log(dsc, dsc_cfg); DC_LOG_DSC("DSC Picture Parameter Set (PPS):");
From: David Francis David.Francis@amd.com
During MST mode enumeration, if a new dc_sink is created, populate it with dsc caps as appropriate.
Use drm_dp_mst_dsc_aux_for_port to get the raw caps, then parse them onto dc_sink with dc_dsc_parse_dsc_dpcd.
Reviewed-by: Wenjing Liu Wenjing.Liu@amd.com Signed-off-by: David Francis David.Francis@amd.com --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 3 ++ .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 31 ++++++++++++++++++- 2 files changed, 33 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 3ce104324096..8bae6f264ef1 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -279,6 +279,9 @@ struct amdgpu_dm_connector { struct drm_dp_mst_port *port; struct amdgpu_dm_connector *mst_port; struct amdgpu_encoder *mst_encoder; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + struct drm_dp_aux *dsc_aux; +#endif
/* MST specific */ uint32_t vcpi_slots; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 7f3ce29bd14c..270d972c9c3c 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -25,6 +25,7 @@
#include <linux/version.h> #include <drm/drm_atomic_helper.h> +#include <drm/drm_dp_mst_helper.h> #include "dm_services.h" #include "amdgpu.h" #include "amdgpu_dm.h" @@ -187,6 +188,28 @@ static const struct drm_connector_funcs dm_dp_mst_connector_funcs = { .early_unregister = amdgpu_dm_mst_connector_early_unregister, };
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT +static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector) +{ + struct dc_sink *dc_sink = aconnector->dc_sink; + struct drm_dp_mst_port *port = aconnector->port; + u8 dsc_caps[16] = { 0 }; + + aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port); + + if (!aconnector->dsc_aux) + return false; + + if (drm_dp_dpcd_read(aconnector->dsc_aux, DP_DSC_SUPPORT, dsc_caps, 16) < 0) + return false; + + if (!dc_dsc_parse_dsc_dpcd(dsc_caps, NULL, &dc_sink->sink_dsc_caps.dsc_dec_caps)) + return false; + + return true; +} +#endif + static int dm_dp_mst_get_modes(struct drm_connector *connector) { struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); @@ -229,10 +252,16 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) /* dc_link_add_remote_sink returns a new reference */ aconnector->dc_sink = dc_sink;
- if (aconnector->dc_sink) + if (aconnector->dc_sink) { amdgpu_dm_update_freesync_caps( connector, aconnector->edid);
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + if (!validate_dsc_caps_on_connector(aconnector)) + memset(&aconnector->dc_sink->sink_dsc_caps, + 0, sizeof(aconnector->dc_sink->sink_dsc_caps)); +#endif + } }
drm_connector_update_edid_property(
From: David Francis David.Francis@amd.com
Rework the dm_helpers_write_dsc_enable callback to handle the MST case.
Use the cached dsc_aux field.
Reviewed-by: Wenjing Liu Wenjing.Liu@amd.com Signed-off-by: David Francis David.Francis@amd.com --- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index fc537ae25eeb..bd694499e3de 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -37,6 +37,7 @@ #include "dc.h" #include "amdgpu_dm.h" #include "amdgpu_dm_irq.h" +#include "amdgpu_dm_mst_types.h"
#include "dm_helpers.h"
@@ -518,8 +519,24 @@ bool dm_helpers_dp_write_dsc_enable( ) { uint8_t enable_dsc = enable ? 1 : 0; + struct amdgpu_dm_connector *aconnector; + + if (!stream) + return false; + + if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { + aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; + + if (!aconnector->dsc_aux) + return false; + + return (drm_dp_dpcd_write(aconnector->dsc_aux, DP_DSC_ENABLE, &enable_dsc, 1) >= 0); + } + + if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT) + return dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1);
- return dm_helpers_dp_write_dpcd(ctx, stream->sink->link, DP_DSC_ENABLE, &enable_dsc, 1); + return false; } #endif
From: David Francis David.Francis@amd.com
If there is limited link bandwidth on a MST network, it must be divided fairly between the streams on that network
Implement an algorithm to determine the correct DSC config for each stream
The algorithm: This [ ] ( ) represents the range of bandwidths possible for a given stream. The [] area represents the range of DSC configs, and the () represents no DSC. The bandwidth used increases from left to right.
First, try disabling DSC on all streams [ ] (|) [ ] (|) Check this against the bandwidth limits of the link and each branch (including each endpoint). If it passes, the job is done
Second, try maximum DSC compression on all streams that support DSC [| ] ( ) [| ] ( ) If this does not pass, then enabling this combination of streams is impossible
Otherwise, divide the remaining bandwidth evenly amongst the streams [ | ] ( ) [ | ] ( )
If one or more of the streams reach minimum compression, evenly divide the reamining bandwidth amongst the remaining streams [ |] ( ) [ |] ( ) [ | ] ( ) [ | ] ( )
If all streams can reach minimum compression, disable compression greedily [ |] ( ) [ |] ( ) [ ] (|)
Perform this algorithm on each full update, on each MST link with at least one DSC stream on it
After the configs are computed, call dcn20_add_dsc_to_stream_resource on each stream with DSC enabled. It is only after all streams are created that we can know which of them will need DSC.
Do all of this at the end of amdgpu atomic check. If it fails, fail check; This combination of timings cannot be supported.
Reviewed-by: Wenjing Liu Wenjing.Liu@amd.com Signed-off-by: David Francis David.Francis@amd.com --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 + .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 386 ++++++++++++++++++ .../display/amdgpu_dm/amdgpu_dm_mst_types.h | 4 + .../drm/amd/display/dc/dcn20/dcn20_resource.c | 7 +- .../drm/amd/display/dc/dcn20/dcn20_resource.h | 1 + 5 files changed, 400 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 59114b52090d..81e30918f9ec 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7702,6 +7702,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, if (ret) goto fail;
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + if (!compute_mst_dsc_configs_for_state(dm_state->context)) + goto fail; +#endif if (dc_validate_global_state(dc, dm_state->context, false) != DC_OK) { ret = -EINVAL; goto fail; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 270d972c9c3c..6b9696889668 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -38,6 +38,8 @@
#include "i2caux_interface.h"
+#include "dc/dcn20/dcn20_resource.h" + /* #define TRACE_DPCD */
#ifdef TRACE_DPCD @@ -490,3 +492,387 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, aconnector->connector_id); }
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT +struct dsc_mst_fairness_params { + struct dc_crtc_timing *timing; + struct dc_sink *sink; + struct dc_dsc_bw_range bw_range; + bool compression_possible; + struct drm_dp_mst_port *port; +}; + +struct dsc_mst_fairness_vars { + int pbn; + bool dsc_enabled; + int bpp_x16; +}; + +static bool port_downstream_of_branch(struct drm_dp_mst_port *port, + struct drm_dp_mst_branch *branch) +{ + while (port->parent) { + if (port->parent == branch) + return true; + + if (port->parent->port_parent) + port = port->parent->port_parent; + else + break; + } + return false; +} + +static bool check_pbn_limit_on_branch(struct drm_dp_mst_branch *branch, + struct dsc_mst_fairness_params *params, + struct dsc_mst_fairness_vars *vars, int count) +{ + struct drm_dp_mst_port *port; + int i; + int pbn_limit = 0; + int pbn_used = 0; + + list_for_each_entry(port, &branch->ports, next) { + if (port->mstb) + if (!check_pbn_limit_on_branch(port->mstb, params, vars, count)) + return false; + + if (port->available_pbn > 0) + pbn_limit = port->available_pbn; + } + + for (i = 0; i < count; i++) { + if (port_downstream_of_branch(params[i].port, branch)) + pbn_used += vars[i].pbn; + } + + if (pbn_used > pbn_limit) + return false; + + return true; +} + +static bool check_bandwidth_limits(struct dc_link *dc_link, + struct dsc_mst_fairness_params *params, + struct dsc_mst_fairness_vars *vars, + int count) +{ + int link_timeslot_limit = 63; + int link_timeslots_used = 0; + int pbn_per_timeslot; + int i; + struct drm_dp_mst_topology_mgr *mst_mgr; + + /* kbits to pbn, dividing by 64 */ + pbn_per_timeslot = dc_link_bandwidth_kbps(dc_link, + dc_link_get_link_cap(dc_link)) / (8 * 1000 * 54); + + /* Check link bandwidth limit */ + for (i = 0; i < count; i++) + link_timeslots_used += DIV_ROUND_UP(vars[i].pbn, pbn_per_timeslot); + + if (link_timeslots_used > link_timeslot_limit) + return false; + + /* Check branch bandwidth limit for each port on each branch */ + mst_mgr = params[0].port->mgr; + if (!check_pbn_limit_on_branch(mst_mgr->mst_primary, params, vars, count)) + return false; + + return true; +} + +static int kbps_to_peak_pbn(int kbps) +{ + u64 peak_kbps = kbps; + + peak_kbps *= 1006; + peak_kbps /= 1000; + return (int) DIV_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000)); +} + +static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params, + struct dsc_mst_fairness_vars *vars, + int count) +{ + int i; + + for (i = 0; i < count; i++) { + memset(¶ms[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg)); + if (vars[i].dsc_enabled && dc_dsc_compute_config( + params[i].sink->ctx->dc->res_pool->dscs[0], + ¶ms[i].sink->sink_dsc_caps.dsc_dec_caps, + params[i].sink->ctx->dc->debug.dsc_min_slice_height_override, + 0, + params[i].timing, + ¶ms[i].timing->dsc_cfg)) { + params[i].timing->flags.DSC = 1; + params[i].timing->dsc_cfg.bits_per_pixel = vars[i].bpp_x16; + } else { + params[i].timing->flags.DSC = 0; + } + + } + +} + +static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn) +{ + struct dc_dsc_config dsc_config; + u64 kbps; + + kbps = (u64)pbn * 994 * 8 * 54 / 64; + dc_dsc_compute_config( + param.sink->ctx->dc->res_pool->dscs[0], + ¶m.sink->sink_dsc_caps.dsc_dec_caps, + param.sink->ctx->dc->debug.dsc_min_slice_height_override, + (int) kbps, param.timing, &dsc_config); + + return dsc_config.bits_per_pixel; +} + +static void increase_dsc_bpp(struct dc_link *dc_link, + struct dsc_mst_fairness_params *params, + struct dsc_mst_fairness_vars *vars, + int count) +{ + int i; + bool bpp_increased[MAX_PIPES]; + int initial_slack[MAX_PIPES]; + int min_initial_slack; + int next_index; + int remaining_to_increase = 0; + int pbn_per_timeslot; + int link_timeslots_used; + int fair_pbn_alloc; + + for (i = 0; i < count; i++) { + if (vars[i].dsc_enabled) { + initial_slack[i] = kbps_to_peak_pbn(params[i].bw_range.max_kbps) - vars[i].pbn; + bpp_increased[i] = false; + remaining_to_increase += 1; + } else { + initial_slack[i] = 0; + bpp_increased[i] = true; + } + } + + pbn_per_timeslot = dc_link_bandwidth_kbps(dc_link, + dc_link_get_link_cap(dc_link)) / (8 * 1000 * 54); + + while (remaining_to_increase) { + next_index = -1; + min_initial_slack = -1; + for (i = 0; i < count; i++) { + if (!bpp_increased[i]) { + if (min_initial_slack == -1 || min_initial_slack > initial_slack[i]) { + min_initial_slack = initial_slack[i]; + next_index = i; + } + } + } + + if (next_index == -1) + break; + + link_timeslots_used = 0; + + for (i = 0; i < count; i++) + link_timeslots_used += DIV_ROUND_UP(vars[i].pbn, pbn_per_timeslot); + + fair_pbn_alloc = (63 - link_timeslots_used) / remaining_to_increase * pbn_per_timeslot; + + if (initial_slack[next_index] > fair_pbn_alloc) { + vars[next_index].pbn += fair_pbn_alloc; + if (check_bandwidth_limits(dc_link, params, vars, count)) + vars[next_index].bpp_x16 = bpp_x16_from_pbn(params[next_index], vars[next_index].pbn); + else + vars[next_index].pbn -= fair_pbn_alloc; + } else { + vars[next_index].pbn += initial_slack[next_index]; + if (check_bandwidth_limits(dc_link, params, vars, count)) + vars[next_index].bpp_x16 = params[next_index].bw_range.max_target_bpp_x16; + else + vars[next_index].pbn -= initial_slack[next_index]; + } + + bpp_increased[next_index] = true; + remaining_to_increase--; + } +} + +static void try_disable_dsc(struct dc_link *dc_link, + struct dsc_mst_fairness_params *params, + struct dsc_mst_fairness_vars *vars, + int count) +{ + int i; + bool tried[MAX_PIPES]; + int kbps_increase[MAX_PIPES]; + int max_kbps_increase; + int next_index; + int remaining_to_try = 0; + + for (i = 0; i < count; i++) { + if (vars[i].dsc_enabled && vars[i].bpp_x16 == params[i].bw_range.max_target_bpp_x16) { + kbps_increase[i] = params[i].bw_range.stream_kbps - params[i].bw_range.max_kbps; + tried[i] = false; + remaining_to_try += 1; + } else { + kbps_increase[i] = 0; + tried[i] = true; + } + } + + while (remaining_to_try) { + next_index = -1; + max_kbps_increase = -1; + for (i = 0; i < count; i++) { + if (!tried[i]) { + if (max_kbps_increase == -1 || max_kbps_increase < kbps_increase[i]) { + max_kbps_increase = kbps_increase[i]; + next_index = i; + } + } + } + + if (next_index == -1) + break; + + vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps); + + if (check_bandwidth_limits(dc_link, params, vars, count)) { + vars[next_index].dsc_enabled = false; + vars[next_index].bpp_x16 = 0; + } else { + vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.max_kbps); + } + + tried[next_index] = true; + remaining_to_try--; + } +} + +static bool compute_mst_dsc_configs_for_link(struct dc_state *dc_state, struct dc_link *dc_link) +{ + int i; + struct dc_stream_state *stream; + struct dsc_mst_fairness_params params[MAX_PIPES]; + struct dsc_mst_fairness_vars vars[MAX_PIPES]; + struct amdgpu_dm_connector *aconnector; + int count = 0; + + memset(params, 0, sizeof(params)); + + /* Set up params */ + for (i = 0; i < dc_state->stream_count; i++) { + stream = dc_state->streams[i]; + + if (stream->link != dc_link) + continue; + + stream->timing.flags.DSC = 0; + + params[count].timing = &stream->timing; + params[count].sink = stream->sink; + aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; + params[count].port = aconnector->port; + params[count].compression_possible = stream->sink->sink_dsc_caps.dsc_dec_caps.is_dsc_supported; + if (!dc_dsc_compute_bandwidth_range( + stream->sink->ctx->dc->res_pool->dscs[0], + stream->sink->ctx->dc->debug.dsc_min_slice_height_override, + 8, 16, + &stream->sink->sink_dsc_caps.dsc_dec_caps, + &stream->timing, ¶ms[count].bw_range)) + params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing); + + count++; + } + + /* Try no compression */ + for (i = 0; i < count; i++) { + vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps); + vars[i].dsc_enabled = false; + vars[i].bpp_x16 = 0; + } + + if (check_bandwidth_limits(dc_link, params, vars, count)) { + set_dsc_configs_from_fairness_vars(params, vars, count); + return true; + } + + /* Try max compression */ + for (i = 0; i < count; i++) { + if (params[i].compression_possible) { + vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps); + vars[i].dsc_enabled = true; + vars[i].bpp_x16 = params[i].bw_range.min_target_bpp_x16; + } else { + vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps); + vars[i].dsc_enabled = false; + vars[i].bpp_x16 = 0; + } + } + + if (!check_bandwidth_limits(dc_link, params, vars, count)) + return false; + + /* Optimize degree of compression */ + increase_dsc_bpp(dc_link, params, vars, count); + + try_disable_dsc(dc_link, params, vars, count); + + set_dsc_configs_from_fairness_vars(params, vars, count); + + return true; +} + +bool compute_mst_dsc_configs_for_state(struct dc_state *dc_state) +{ + int i, j; + struct dc_stream_state *stream; + bool computed_streams[MAX_PIPES]; + struct amdgpu_dm_connector *aconnector; + + for (i = 0; i < dc_state->stream_count; i++) + computed_streams[i] = false; + + for (i = 0; i < dc_state->stream_count; i++) { + stream = dc_state->streams[i]; + + if (stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) + continue; + + aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; + + if (!aconnector || !aconnector->dc_sink) + continue; + + if (!aconnector->dc_sink->sink_dsc_caps.dsc_dec_caps.is_dsc_supported) + continue; + + if (computed_streams[i]) + continue; + + mutex_lock(&aconnector->mst_mgr.lock); + if (!compute_mst_dsc_configs_for_link(dc_state, stream->link)) { + mutex_unlock(&aconnector->mst_mgr.lock); + return false; + } + mutex_unlock(&aconnector->mst_mgr.lock); + + for (j = 0; j < dc_state->stream_count; j++) { + if (dc_state->streams[j]->link == stream->link) + computed_streams[j] = true; + } + } + + for (i = 0; i < dc_state->stream_count; i++) { + stream = dc_state->streams[i]; + + if (stream->timing.flags.DSC == 1) + dcn20_add_dsc_to_stream_resource(stream->ctx->dc, dc_state, stream); + } + + return true; +} +#endif diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h index 2da851b40042..da957611214a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h @@ -32,4 +32,8 @@ struct amdgpu_dm_connector; void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, struct amdgpu_dm_connector *aconnector);
+ +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT +bool compute_mst_dsc_configs_for_state(struct dc_state *dc_state); +#endif #endif diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c index f57c686398fe..98ad803ff224 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c @@ -1447,7 +1447,7 @@ static void release_dsc(struct resource_context *res_ctx,
#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT -static enum dc_status add_dsc_to_stream_resource(struct dc *dc, +enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc, struct dc_state *dc_ctx, struct dc_stream_state *dc_stream) { @@ -1462,6 +1462,9 @@ static enum dc_status add_dsc_to_stream_resource(struct dc *dc, if (pipe_ctx->stream != dc_stream) continue;
+ if (pipe_ctx->stream_res.dsc) + continue; + acquire_dsc(&dc_ctx->res_ctx, pool, &pipe_ctx->stream_res.dsc);
/* The number of DSCs can be less than the number of pipes */ @@ -1513,7 +1516,7 @@ enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Get a DSC if required and available */ if (result == DC_OK && dc_stream->timing.flags.DSC) - result = add_dsc_to_stream_resource(dc, new_ctx, dc_stream); + result = dcn20_add_dsc_to_stream_resource(dc, new_ctx, dc_stream); #endif
if (result == DC_OK) diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h index 44f95aa0d61e..2209ebda6ef6 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h @@ -131,6 +131,7 @@ void dcn20_calculate_dlg_params(
enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream); enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream); +enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc, struct dc_state *dc_ctx, struct dc_stream_state *dc_stream); enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream); enum dc_status dcn20_get_default_swizzle_mode(struct dc_plane_state *plane_state);
From: Mikita Lipski mikita.lipski@amd.com
Since for DSC MST connector's PBN is claculated differently due to compression, we have to recalculate both PBN and VCPI slots for that connector.
This patch proposes to use similair logic as in dm_encoder_helper_atomic_chek, but since we do not know which connectors will have DSC enabled we have to recalculate PBN only after that's determined, which is done in compute_mst_dsc_configs_for_state.
Cc: Jerry Zuo Jerry.Zuo@amd.com Cc: Harry Wentland harry.wentland@amd.com Cc: Lyude Paul lyude@redhat.com Signed-off-by: Mikita Lipski mikita.lipski@amd.com --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 64 +++++++++++++++++-- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 6 -- 2 files changed, 59 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 81e30918f9ec..7501ce2233ed 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4569,6 +4569,27 @@ static void dm_encoder_helper_disable(struct drm_encoder *encoder)
}
+static int convert_dc_color_depth_into_bpc (enum dc_color_depth display_color_depth) +{ + switch (display_color_depth) { + case COLOR_DEPTH_666: + return 6; + case COLOR_DEPTH_888: + return 8; + case COLOR_DEPTH_101010: + return 10; + case COLOR_DEPTH_121212: + return 12; + case COLOR_DEPTH_141414: + return 14; + case COLOR_DEPTH_161616: + return 16; + default: + break; + } + return 0; +} + static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) @@ -4616,6 +4637,36 @@ const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { .atomic_check = dm_encoder_helper_atomic_check };
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT +static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, + struct dc_state *dc_state) +{ + struct dc_stream_state *stream; + struct amdgpu_dm_connector *aconnector; + int i, clock = 0, bpp = 0; + + for (i = 0; i < dc_state->stream_count; i++) { + stream = dc_state->streams[i]; + aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; + + if (stream && stream->timing.flags.DSC == 1) { + bpp = convert_dc_color_depth_into_bpc(stream->timing.display_color_depth)* 3; + clock = stream->timing.pix_clk_100hz / 10; + + aconnector->pbn = drm_dp_calc_pbn_mode(clock, bpp, true); + + aconnector->vcpi_slots = drm_dp_atomic_find_vcpi_slots(state, + &aconnector->mst_port->mst_mgr, + aconnector->port, + aconnector->pbn); + if (aconnector->vcpi_slots < 0) + return aconnector->vcpi_slots; + } + } + return 0; +} +#endif + static void dm_drm_plane_reset(struct drm_plane *plane) { struct dm_plane_state *amdgpu_state = NULL; @@ -7629,11 +7680,6 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, if (ret) goto fail;
- /* Perform validation of MST topology in the state*/ - ret = drm_dp_mst_atomic_check(state); - if (ret) - goto fail; - if (state->legacy_cursor_update) { /* * This is a fast cursor update coming from the plane update @@ -7705,6 +7751,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (!compute_mst_dsc_configs_for_state(dm_state->context)) goto fail; + + ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context); + if (ret) + goto fail; #endif if (dc_validate_global_state(dc, dm_state->context, false) != DC_OK) { ret = -EINVAL; @@ -7734,6 +7784,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, dc_retain_state(old_dm_state->context); } } + /* Perform validation of MST topology in the state*/ + ret = drm_dp_mst_atomic_check(state); + if (ret) + goto fail;
/* Store the overall update type for use later in atomic check. */ for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index bd694499e3de..3e44e2da2d0d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -201,12 +201,6 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( mst_port = aconnector->port;
if (enable) { - - /* Convert kilobits per second / 64 (for 64 timeslots) to pbn (54/64 megabytes per second) */ - pbn_per_timeslot = dc_link_bandwidth_kbps( - stream->link, dc_link_get_link_cap(stream->link)) / (8 * 1000 * 54); - aconnector->vcpi_slots = DIV_ROUND_UP(aconnector->pbn, pbn_per_timeslot); - ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, aconnector->pbn, aconnector->vcpi_slots);
From: David Francis David.Francis@amd.com
Whenever a connector on an MST network is attached, detached, or undergoes a modeset, the DSC configs for each stream on that topology will be recalculated. This can change their required bandwidth, requiring a full reprogramming, as though a modeset was performed, even if that stream did not change timing.
Therefore, whenever a crtc has drm_atomic_crtc_needs_modeset, for each crtc that shares a MST topology with that stream and supports DSC, add that crtc (and all affected connectors and planes) to the atomic state and set mode_changed on its state
v2: Do this check only on Navi and before adding connectors and planes on modesetting crtcs
Cc: Leo Li sunpeng.li@amd.com Cc: Nicholas Kazlauskas nicholas.kazlauskas@amd.com Cc: Lyude Paul lyude@redhat.com Signed-off-by: David Francis David.Francis@amd.com --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 79 +++++++++++++++++++ 1 file changed, 79 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 7501ce2233ed..371086a67c68 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6888,6 +6888,74 @@ static int do_aquire_global_lock(struct drm_device *dev, return ret < 0 ? ret : 0; }
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT +/* + * TODO: This logic should at some point be moved into DRM + */ +static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc) +{ + struct drm_connector *connector; + struct drm_connector_state *conn_state; + struct drm_connector_list_iter conn_iter; + struct drm_crtc_state *new_crtc_state; + struct amdgpu_dm_connector *aconnector = NULL, *aconnector_to_add; + int i, j; + struct drm_crtc *crtcs_affected[AMDGPU_MAX_CRTCS] = { 0 }; + + for_each_new_connector_in_state(state, connector, conn_state, i) { + if (conn_state->crtc != crtc) + continue; + + aconnector = to_amdgpu_dm_connector(connector); + if (!aconnector->port) + aconnector = NULL; + else + break; + } + + if (!aconnector) + return 0; + + i = 0; + drm_connector_list_iter_begin(state->dev, &conn_iter); + drm_for_each_connector_iter(connector, &conn_iter) { + if (!connector->state || !connector->state->crtc) + continue; + + aconnector_to_add = to_amdgpu_dm_connector(connector); + if (!aconnector_to_add->port) + continue; + + if (aconnector_to_add->port->mgr != aconnector->port->mgr) + continue; + + if (!aconnector_to_add->dc_sink) + continue; + + if (!aconnector_to_add->dc_sink->sink_dsc_caps.dsc_dec_caps.is_dsc_supported) + continue; + + if (i >= AMDGPU_MAX_CRTCS) + continue; + + crtcs_affected[i] = connector->state->crtc; + i++; + } + drm_connector_list_iter_end(&conn_iter); + + for (j = 0; j < i; j++) { + new_crtc_state = drm_atomic_get_crtc_state(state, crtcs_affected[j]); + if (IS_ERR(new_crtc_state)) + return PTR_ERR(new_crtc_state); + + new_crtc_state->mode_changed = true; + } + + return 0; + +} +#endif + static void get_freesync_config_for_crtc( struct dm_crtc_state *new_crtc_state, struct dm_connector_state *new_con_state) @@ -7577,6 +7645,17 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, if (ret) goto fail;
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + if (adev->asic_type >= CHIP_NAVI10) { + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { + if (drm_atomic_crtc_needs_modeset(new_crtc_state)) { + ret = add_affected_mst_dsc_crtcs(state, crtc); + if (ret) + goto fail; + } + } + } +#endif for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && !new_crtc_state->color_mgmt_changed &&
Ok, let's stop and slow down for a minute here since I've repeated myself a few times, and I'd like to figure out what's actually happening here and whether I'm not being clear enough with my explanations, or if there's just some misunderstanding here.
I'll start of by trying my best to explain my hesistance in accepting these patches. To be clear, MST with DSC is a big thing in terms of impact. There's a lot of things to consider: * What should the default DSC policy for MST be? Should we keep it on by default so that we don't need to trigger a large number of PBN recalculations and enable DSC on a per-case basis, or are there legitimate reasons to keep DSC off by default (such as potential issues with lossiness down the line). * We have other drivers in the tree that are planning on implementing MST DSC quite soon. Chances are they'll be implementing helpers to do this so this can be supported across the DRM tree, and chances are we'll just have to rewrite and remove most of this code in that case once they do. * amdgpu already has a _lot_ of code that doesn't need to, and shouldn't be there. This ranges from various DC specific helpers that are essentially the same as the helpers that we already implement in the rest of DRM, to misuses of various kernel APIs, and a complete lack of any kind of code style (at least the last time that I checked) in or out of DC. This makes the driver more difficult for people who don't work at AMD but are well accustomed to working on the rest of the kernel, e.g. myself and others, and it's a problem that seriously needs to be solved. Adding more redundant DP helpers that will inevitably get removed is just making the problem worse.
With all of this being said: I've been asking the same questions about this patch throughout the whole patch series so far (since it got passed off to you from David's internship ending):
* Can we keep DSC enabled by default, so that these patches aren't needed? * If we can't, can we move this into common code so that other drivers can use it? The problem is I haven't received any responses to these questions, other then being told by David a month or two ago that it would be expedient to just accept the patches and move on. Honestly, if discussion had been had about the changes I requested, I would have given my r-b a long time ago. In fact-I really want to give it now! There's multiple patches in this series that would be very useful for other things that are being worked on at the moment, such as the changes to drm_dp_dpcd_read/drm_dp_dpcd_write(). But I really think this needs to be discussed first, and I'm worried that just going ahead and giving my R-B before they have been discussed will further encourage rushing changes like this in the future and continually building more tech debt for ourselves.
Please note as well: if anything I've asked for is confusing, or you don't understand what I'm asking or looking for I am more then willing to help explain things and help out as best as I can. I understand that a lot of the developers working on DRM at AMD may have more experience in Windows and Mac land and as a result, trying to get used to the way that we do things in the Linux kernel can be a confusing endeavor. I'm more then happy to help out with this wherever I can, all you need to do is ask. Asking a few questions about something you aren't sure you understand can save both of us a lot of time, and avoid having to go through this many patch respins.
In the mean time, I'd be willing to look at what patches from this series that have already been reviewed which could be pushed to drm-misc or friends in the mean time to speed things up a bit.
On Tue, 2019-10-01 at 12:17 -0400, mikita.lipski@amd.com wrote:
From: Mikita Lipski mikita.lipski@amd.com
Since for DSC MST connector's PBN is claculated differently due to compression, we have to recalculate both PBN and VCPI slots for that connector.
This patch proposes to use similair logic as in dm_encoder_helper_atomic_chek, but since we do not know which connectors will have DSC enabled we have to recalculate PBN only after that's determined, which is done in compute_mst_dsc_configs_for_state.
Cc: Jerry Zuo Jerry.Zuo@amd.com Cc: Harry Wentland harry.wentland@amd.com Cc: Lyude Paul lyude@redhat.com Signed-off-by: Mikita Lipski mikita.lipski@amd.com
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 64 +++++++++++++++++-- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 6 -- 2 files changed, 59 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 81e30918f9ec..7501ce2233ed 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4569,6 +4569,27 @@ static void dm_encoder_helper_disable(struct drm_encoder *encoder)
}
+static int convert_dc_color_depth_into_bpc (enum dc_color_depth display_color_depth) +{
- switch (display_color_depth) {
case COLOR_DEPTH_666:return 6;case COLOR_DEPTH_888:return 8;case COLOR_DEPTH_101010:return 10;case COLOR_DEPTH_121212:return 12;case COLOR_DEPTH_141414:return 14;case COLOR_DEPTH_161616:return 16;default:break;}- return 0;
+}
static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) @@ -4616,6 +4637,36 @@ const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { .atomic_check = dm_encoder_helper_atomic_check };
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT +static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
struct dc_state *dc_state)+{
- struct dc_stream_state *stream;
- struct amdgpu_dm_connector *aconnector;
- int i, clock = 0, bpp = 0;
- for (i = 0; i < dc_state->stream_count; i++) {
stream = dc_state->streams[i];aconnector = (struct amdgpu_dm_connector *)stream-dm_stream_context;
if (stream && stream->timing.flags.DSC == 1) {bpp = convert_dc_color_depth_into_bpc(stream-timing.display_color_depth)* 3;
clock = stream->timing.pix_clk_100hz / 10;aconnector->pbn = drm_dp_calc_pbn_mode(clock, bpp,true);
aconnector->vcpi_slots =drm_dp_atomic_find_vcpi_slots(state,
&aconnector-mst_port->mst_mgr,
aconnector->port,aconnector->pbn);if (aconnector->vcpi_slots < 0)return aconnector->vcpi_slots;}- }
- return 0;
+} +#endif
static void dm_drm_plane_reset(struct drm_plane *plane) { struct dm_plane_state *amdgpu_state = NULL; @@ -7629,11 +7680,6 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, if (ret) goto fail;
- /* Perform validation of MST topology in the state*/
- ret = drm_dp_mst_atomic_check(state);
- if (ret)
goto fail;- if (state->legacy_cursor_update) { /*
- This is a fast cursor update coming from the plane update
@@ -7705,6 +7751,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (!compute_mst_dsc_configs_for_state(dm_state->context)) goto fail;
ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state-context);
if (ret)goto fail;#endif if (dc_validate_global_state(dc, dm_state->context, false) != DC_OK) { ret = -EINVAL; @@ -7734,6 +7784,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, dc_retain_state(old_dm_state->context); } }
/* Perform validation of MST topology in the state*/
ret = drm_dp_mst_atomic_check(state);
if (ret)
goto fail;/* Store the overall update type for use later in atomic check. */ for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index bd694499e3de..3e44e2da2d0d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -201,12 +201,6 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( mst_port = aconnector->port;
if (enable) {
/* Convert kilobits per second / 64 (for 64 timeslots) to pbn(54/64 megabytes per second) */
pbn_per_timeslot = dc_link_bandwidth_kbps(stream->link, dc_link_get_link_cap(stream-link)) / (8 * 1000 * 54);
aconnector->vcpi_slots = DIV_ROUND_UP(aconnector->pbn,pbn_per_timeslot);
- ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, aconnector->pbn, aconnector->vcpi_slots);
... yikes I need to apologize because I was going through my email and I realized you _did_ respond to me earlier regarding some of these questions, it just appears the reply fell through the cracks and somehow I didn't notice it until just now. Sorry about that!
I'm still not sure I understand why this is a future enhancement? Everything we need to implement these helpers should already be here, it's just a matter of keeping track who has dsc enabled where in the mst atomic state
On Mon, 2019-10-07 at 17:52 -0400, Lyude Paul wrote:
Ok, let's stop and slow down for a minute here since I've repeated myself a few times, and I'd like to figure out what's actually happening here and whether I'm not being clear enough with my explanations, or if there's just some misunderstanding here.
I'll start of by trying my best to explain my hesistance in accepting these patches. To be clear, MST with DSC is a big thing in terms of impact. There's a lot of things to consider:
- What should the default DSC policy for MST be? Should we keep it on by default so that we don't need to trigger a large number of PBN recalculations and enable DSC on a per-case basis, or are there
legitimate reasons to keep DSC off by default (such as potential issues with lossiness down the line).
- We have other drivers in the tree that are planning on implementing MST
DSC quite soon. Chances are they'll be implementing helpers to do this so this can be supported across the DRM tree, and chances are we'll just have to rewrite and remove most of this code in that case once they do.
- amdgpu already has a _lot_ of code that doesn't need to, and shouldn't be there. This ranges from various DC specific helpers that are essentially the same as the helpers that we already implement in the rest of DRM, to misuses of various kernel APIs, and a complete lack of any kind of code style (at least the last time that I checked) in or out of DC. This makes the driver more difficult for people who don't work at AMD but are well accustomed to working on the rest of the kernel, e.g. myself and others, and it's a problem that seriously needs to be solved. Adding more
redundant DP helpers that will inevitably get removed is just making the problem worse.
With all of this being said: I've been asking the same questions about this patch throughout the whole patch series so far (since it got passed off to you from David's internship ending):
- Can we keep DSC enabled by default, so that these patches aren't needed?
- If we can't, can we move this into common code so that other drivers can use it?
The problem is I haven't received any responses to these questions, other then being told by David a month or two ago that it would be expedient to just accept the patches and move on. Honestly, if discussion had been had about the changes I requested, I would have given my r-b a long time ago. In fact-I really want to give it now! There's multiple patches in this series that would be very useful for other things that are being worked on at the moment, such as the changes to drm_dp_dpcd_read/drm_dp_dpcd_write(). But I really think this needs to be discussed first, and I'm worried that just going ahead and giving my R-B before they have been discussed will further encourage rushing changes like this in the future and continually building more tech debt for ourselves.
Please note as well: if anything I've asked for is confusing, or you don't understand what I'm asking or looking for I am more then willing to help explain things and help out as best as I can. I understand that a lot of the developers working on DRM at AMD may have more experience in Windows and Mac land and as a result, trying to get used to the way that we do things in the Linux kernel can be a confusing endeavor. I'm more then happy to help out with this wherever I can, all you need to do is ask. Asking a few questions about something you aren't sure you understand can save both of us a lot of time, and avoid having to go through this many patch respins.
In the mean time, I'd be willing to look at what patches from this series that have already been reviewed which could be pushed to drm-misc or friends in the mean time to speed things up a bit.
On Tue, 2019-10-01 at 12:17 -0400, mikita.lipski@amd.com wrote:
From: Mikita Lipski mikita.lipski@amd.com
Since for DSC MST connector's PBN is claculated differently due to compression, we have to recalculate both PBN and VCPI slots for that connector.
This patch proposes to use similair logic as in dm_encoder_helper_atomic_chek, but since we do not know which connectors will have DSC enabled we have to recalculate PBN only after that's determined, which is done in compute_mst_dsc_configs_for_state.
Cc: Jerry Zuo Jerry.Zuo@amd.com Cc: Harry Wentland harry.wentland@amd.com Cc: Lyude Paul lyude@redhat.com Signed-off-by: Mikita Lipski mikita.lipski@amd.com
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 64 +++++++++++++++++-- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 6 -- 2 files changed, 59 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 81e30918f9ec..7501ce2233ed 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4569,6 +4569,27 @@ static void dm_encoder_helper_disable(struct drm_encoder *encoder)
}
+static int convert_dc_color_depth_into_bpc (enum dc_color_depth display_color_depth) +{
- switch (display_color_depth) {
case COLOR_DEPTH_666:return 6;case COLOR_DEPTH_888:return 8;case COLOR_DEPTH_101010:return 10;case COLOR_DEPTH_121212:return 12;case COLOR_DEPTH_141414:return 14;case COLOR_DEPTH_161616:return 16;default:break;}- return 0;
+}
static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) @@ -4616,6 +4637,36 @@ const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { .atomic_check = dm_encoder_helper_atomic_check };
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT +static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
struct dc_state *dc_state)+{
- struct dc_stream_state *stream;
- struct amdgpu_dm_connector *aconnector;
- int i, clock = 0, bpp = 0;
- for (i = 0; i < dc_state->stream_count; i++) {
stream = dc_state->streams[i];aconnector = (struct amdgpu_dm_connector *)stream-dm_stream_context;
if (stream && stream->timing.flags.DSC == 1) {bpp = convert_dc_color_depth_into_bpc(stream-timing.display_color_depth)* 3;
clock = stream->timing.pix_clk_100hz / 10;aconnector->pbn = drm_dp_calc_pbn_mode(clock, bpp,true);
aconnector->vcpi_slots =drm_dp_atomic_find_vcpi_slots(state,
&aconnector-mst_port->mst_mgr,
aconnector->port,aconnector->pbn);if (aconnector->vcpi_slots < 0)return aconnector->vcpi_slots;}- }
- return 0;
+} +#endif
static void dm_drm_plane_reset(struct drm_plane *plane) { struct dm_plane_state *amdgpu_state = NULL; @@ -7629,11 +7680,6 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, if (ret) goto fail;
- /* Perform validation of MST topology in the state*/
- ret = drm_dp_mst_atomic_check(state);
- if (ret)
goto fail;- if (state->legacy_cursor_update) { /*
- This is a fast cursor update coming from the plane update
@@ -7705,6 +7751,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (!compute_mst_dsc_configs_for_state(dm_state->context)) goto fail;
ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state-context);
if (ret)goto fail;#endif if (dc_validate_global_state(dc, dm_state->context, false) != DC_OK) { ret = -EINVAL; @@ -7734,6 +7784,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, dc_retain_state(old_dm_state->context); } }
/* Perform validation of MST topology in the state*/
ret = drm_dp_mst_atomic_check(state);
if (ret)
goto fail;/* Store the overall update type for use later in atomic check. */ for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index bd694499e3de..3e44e2da2d0d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -201,12 +201,6 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( mst_port = aconnector->port;
if (enable) {
/* Convert kilobits per second / 64 (for 64 timeslots) to pbn(54/64 megabytes per second) */
pbn_per_timeslot = dc_link_bandwidth_kbps(stream->link, dc_link_get_link_cap(stream-link)) / (8 * 1000 * 54);
aconnector->vcpi_slots = DIV_ROUND_UP(aconnector->pbn,pbn_per_timeslot);
- ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, aconnector->pbn, aconnector->vcpi_slots);
On Tue, 2019-10-08 at 12:24 -0400, Lyude Paul wrote:
... yikes I need to apologize because I was going through my email and I realized you _did_ respond to me earlier regarding some of these questions, it just appears the reply fell through the cracks and somehow I didn't notice it until just now. Sorry about that!
Referring to this response, jfyi: https://lists.freedesktop.org/archives/amd-gfx/2019-October/040683.html
(sorry again for replying before reading that!)
I'm still not sure I understand why this is a future enhancement? Everything we need to implement these helpers should already be here, it's just a matter of keeping track who has dsc enabled where in the mst atomic state
On Mon, 2019-10-07 at 17:52 -0400, Lyude Paul wrote:
Ok, let's stop and slow down for a minute here since I've repeated myself a few times, and I'd like to figure out what's actually happening here and whether I'm not being clear enough with my explanations, or if there's just some misunderstanding here.
I'll start of by trying my best to explain my hesistance in accepting these patches. To be clear, MST with DSC is a big thing in terms of impact. There's a lot of things to consider:
- What should the default DSC policy for MST be? Should we keep it on by default so that we don't need to trigger a large number of PBN recalculations and enable DSC on a per-case basis, or are there
legitimate reasons to keep DSC off by default (such as potential issues with lossiness down the line).
- We have other drivers in the tree that are planning on implementing MST
DSC quite soon. Chances are they'll be implementing helpers to do this so this can be supported across the DRM tree, and chances are we'll just have to rewrite and remove most of this code in that case once they do.
- amdgpu already has a _lot_ of code that doesn't need to, and shouldn't
be there. This ranges from various DC specific helpers that are essentially the same as the helpers that we already implement in the rest of DRM, to misuses of various kernel APIs, and a complete lack of any kind of code style (at least the last time that I checked) in or out of DC. This makes the driver more difficult for people who don't work at AMD but are well accustomed to working on the rest of the kernel, e.g. myself and others, and it's a problem that seriously needs to be solved. Adding more redundant DP helpers that will inevitably get removed is just making the problem worse.
With all of this being said: I've been asking the same questions about this patch throughout the whole patch series so far (since it got passed off to you from David's internship ending):
- Can we keep DSC enabled by default, so that these patches aren't
needed?
- If we can't, can we move this into common code so that other drivers
can use it? The problem is I haven't received any responses to these questions, other then being told by David a month or two ago that it would be expedient to just accept the patches and move on. Honestly, if discussion had been had about the changes I requested, I would have given my r-b a long time ago. In fact-I really want to give it now! There's multiple patches in this series that would be very useful for other things that are being worked on at the moment, such as the changes to drm_dp_dpcd_read/drm_dp_dpcd_write(). But I really think this needs to be discussed first, and I'm worried that just going ahead and giving my R-B before they have been discussed will further encourage rushing changes like this in the future and continually building more tech debt for ourselves.
Please note as well: if anything I've asked for is confusing, or you don't understand what I'm asking or looking for I am more then willing to help explain things and help out as best as I can. I understand that a lot of the developers working on DRM at AMD may have more experience in Windows and Mac land and as a result, trying to get used to the way that we do things in the Linux kernel can be a confusing endeavor. I'm more then happy to help out with this wherever I can, all you need to do is ask. Asking a few questions about something you aren't sure you understand can save both of us a lot of time, and avoid having to go through this many patch respins.
In the mean time, I'd be willing to look at what patches from this series that have already been reviewed which could be pushed to drm-misc or friends in the mean time to speed things up a bit.
On Tue, 2019-10-01 at 12:17 -0400, mikita.lipski@amd.com wrote:
From: Mikita Lipski mikita.lipski@amd.com
Since for DSC MST connector's PBN is claculated differently due to compression, we have to recalculate both PBN and VCPI slots for that connector.
This patch proposes to use similair logic as in dm_encoder_helper_atomic_chek, but since we do not know which connectors will have DSC enabled we have to recalculate PBN only after that's determined, which is done in compute_mst_dsc_configs_for_state.
Cc: Jerry Zuo Jerry.Zuo@amd.com Cc: Harry Wentland harry.wentland@amd.com Cc: Lyude Paul lyude@redhat.com Signed-off-by: Mikita Lipski mikita.lipski@amd.com
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 64 +++++++++++++++++-- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 6 -- 2 files changed, 59 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 81e30918f9ec..7501ce2233ed 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4569,6 +4569,27 @@ static void dm_encoder_helper_disable(struct drm_encoder *encoder)
}
+static int convert_dc_color_depth_into_bpc (enum dc_color_depth display_color_depth) +{
- switch (display_color_depth) {
case COLOR_DEPTH_666:return 6;case COLOR_DEPTH_888:return 8;case COLOR_DEPTH_101010:return 10;case COLOR_DEPTH_121212:return 12;case COLOR_DEPTH_141414:return 14;case COLOR_DEPTH_161616:return 16;default:break;}- return 0;
+}
static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) @@ -4616,6 +4637,36 @@ const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { .atomic_check = dm_encoder_helper_atomic_check };
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT +static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
struct dc_state *dc_state)+{
- struct dc_stream_state *stream;
- struct amdgpu_dm_connector *aconnector;
- int i, clock = 0, bpp = 0;
- for (i = 0; i < dc_state->stream_count; i++) {
stream = dc_state->streams[i];aconnector = (struct amdgpu_dm_connector *)stream-dm_stream_context;
if (stream && stream->timing.flags.DSC == 1) {bpp = convert_dc_color_depth_into_bpc(stream-timing.display_color_depth)* 3;
clock = stream->timing.pix_clk_100hz / 10;aconnector->pbn = drm_dp_calc_pbn_mode(clock, bpp,true);
aconnector->vcpi_slots =drm_dp_atomic_find_vcpi_slots(state,
&aconnector-mst_port->mst_mgr,
aconnector->port,aconnector->pbn);if (aconnector->vcpi_slots < 0)return aconnector->vcpi_slots;}- }
- return 0;
+} +#endif
static void dm_drm_plane_reset(struct drm_plane *plane) { struct dm_plane_state *amdgpu_state = NULL; @@ -7629,11 +7680,6 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, if (ret) goto fail;
- /* Perform validation of MST topology in the state*/
- ret = drm_dp_mst_atomic_check(state);
- if (ret)
goto fail;- if (state->legacy_cursor_update) { /*
- This is a fast cursor update coming from the plane update
@@ -7705,6 +7751,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (!compute_mst_dsc_configs_for_state(dm_state->context)) goto fail;
ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state-context);
if (ret)goto fail;#endif if (dc_validate_global_state(dc, dm_state->context, false) != DC_OK) { ret = -EINVAL; @@ -7734,6 +7784,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, dc_retain_state(old_dm_state->context); } }
/* Perform validation of MST topology in the state*/
ret = drm_dp_mst_atomic_check(state);
if (ret)
goto fail;/* Store the overall update type for use later in atomic check. */ for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index bd694499e3de..3e44e2da2d0d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -201,12 +201,6 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( mst_port = aconnector->port;
if (enable) {
/* Convert kilobits per second / 64 (for 64 timeslots) to pbn(54/64 megabytes per second) */
pbn_per_timeslot = dc_link_bandwidth_kbps(stream->link, dc_link_get_link_cap(stream-link)) / (8 * 1000 * 54);
aconnector->vcpi_slots = DIV_ROUND_UP(aconnector->pbn,pbn_per_timeslot);
- ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, aconnector->pbn, aconnector->vcpi_slots);
On 08.10.2019 12:24, Lyude Paul wrote:
... yikes I need to apologize because I was going through my email and I realized you _did_ respond to me earlier regarding some of these questions, it just appears the reply fell through the cracks and somehow I didn't notice it until just now. Sorry about that!
No worries, the patches got messy and are easily lost in here. I'll clean up on the next batch so it will be clearer what's happening
I'm still not sure I understand why this is a future enhancement? Everything we need to implement these helpers should already be here, it's just a matter of keeping track who has dsc enabled where in the mst atomic state
As I've mentioned earlier our policy for DSC is to keep it disabled if not needed, because it is a lossy compression. Beside the fact that we don't want imperfect image on the screen, enabling DSC would also increase our power consumption. If we need it - we use the greedy algorithm inside compute_mst_dsc_configs_for_link to only enable DSC on streams that can't fit into allowed bandwidth without compression.
I'm not exactly sure how it can be moved as helper to DRM. We keep track on which stream has DSC enabled by raising DSC flag in dc_stream_state flags structure. That it why pbn recalculation was moved to a separate function so only streams that have DSC flag raised get VCPI recalculated.
I guess if we would have dsc_desired flag on drm_connnector_state and it would then perform recalculation of PBN and VCPI for the connector. Would that be something applicable as a DRM helper?
On Mon, 2019-10-07 at 17:52 -0400, Lyude Paul wrote:
Ok, let's stop and slow down for a minute here since I've repeated myself a few times, and I'd like to figure out what's actually happening here and whether I'm not being clear enough with my explanations, or if there's just some misunderstanding here.
I'll start of by trying my best to explain my hesistance in accepting these patches. To be clear, MST with DSC is a big thing in terms of impact. There's a lot of things to consider:
- What should the default DSC policy for MST be? Should we keep it on by default so that we don't need to trigger a large number of PBN recalculations and enable DSC on a per-case basis, or are there
legitimate reasons to keep DSC off by default (such as potential issues with lossiness down the line).
- We have other drivers in the tree that are planning on implementing MST
DSC quite soon. Chances are they'll be implementing helpers to do this so this can be supported across the DRM tree, and chances are we'll just have to rewrite and remove most of this code in that case once they do.
- amdgpu already has a _lot_ of code that doesn't need to, and shouldn't be there. This ranges from various DC specific helpers that are essentially the same as the helpers that we already implement in the rest of DRM, to misuses of various kernel APIs, and a complete lack of any kind of code style (at least the last time that I checked) in or out of DC. This makes the driver more difficult for people who don't work at AMD but are well accustomed to working on the rest of the kernel, e.g. myself and others, and it's a problem that seriously needs to be solved. Adding more
redundant DP helpers that will inevitably get removed is just making the problem worse.
With all of this being said: I've been asking the same questions about this patch throughout the whole patch series so far (since it got passed off to you from David's internship ending):
- Can we keep DSC enabled by default, so that these patches aren't needed?
- If we can't, can we move this into common code so that other drivers can use it?
The problem is I haven't received any responses to these questions, other then being told by David a month or two ago that it would be expedient to just accept the patches and move on. Honestly, if discussion had been had about the changes I requested, I would have given my r-b a long time ago. In fact-I really want to give it now! There's multiple patches in this series that would be very useful for other things that are being worked on at the moment, such as the changes to drm_dp_dpcd_read/drm_dp_dpcd_write(). But I really think this needs to be discussed first, and I'm worried that just going ahead and giving my R-B before they have been discussed will further encourage rushing changes like this in the future and continually building more tech debt for ourselves.
Please note as well: if anything I've asked for is confusing, or you don't understand what I'm asking or looking for I am more then willing to help explain things and help out as best as I can. I understand that a lot of the developers working on DRM at AMD may have more experience in Windows and Mac land and as a result, trying to get used to the way that we do things in the Linux kernel can be a confusing endeavor. I'm more then happy to help out with this wherever I can, all you need to do is ask. Asking a few questions about something you aren't sure you understand can save both of us a lot of time, and avoid having to go through this many patch respins.
In the mean time, I'd be willing to look at what patches from this series that have already been reviewed which could be pushed to drm-misc or friends in the mean time to speed things up a bit.
On Tue, 2019-10-01 at 12:17 -0400, mikita.lipski@amd.com wrote:
From: Mikita Lipski mikita.lipski@amd.com
Since for DSC MST connector's PBN is claculated differently due to compression, we have to recalculate both PBN and VCPI slots for that connector.
This patch proposes to use similair logic as in dm_encoder_helper_atomic_chek, but since we do not know which connectors will have DSC enabled we have to recalculate PBN only after that's determined, which is done in compute_mst_dsc_configs_for_state.
Cc: Jerry Zuo Jerry.Zuo@amd.com Cc: Harry Wentland harry.wentland@amd.com Cc: Lyude Paul lyude@redhat.com Signed-off-by: Mikita Lipski mikita.lipski@amd.com
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 64 +++++++++++++++++-- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 6 -- 2 files changed, 59 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 81e30918f9ec..7501ce2233ed 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4569,6 +4569,27 @@ static void dm_encoder_helper_disable(struct drm_encoder *encoder)
}
+static int convert_dc_color_depth_into_bpc (enum dc_color_depth display_color_depth) +{
- switch (display_color_depth) {
case COLOR_DEPTH_666:return 6;case COLOR_DEPTH_888:return 8;case COLOR_DEPTH_101010:return 10;case COLOR_DEPTH_121212:return 12;case COLOR_DEPTH_141414:return 14;case COLOR_DEPTH_161616:return 16;default:break;}- return 0;
+}
- static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state, struct drm_connector_state
*conn_state) @@ -4616,6 +4637,36 @@ const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { .atomic_check = dm_encoder_helper_atomic_check };
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT +static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
struct dc_state *dc_state)+{
- struct dc_stream_state *stream;
- struct amdgpu_dm_connector *aconnector;
- int i, clock = 0, bpp = 0;
- for (i = 0; i < dc_state->stream_count; i++) {
stream = dc_state->streams[i];aconnector = (struct amdgpu_dm_connector *)stream-dm_stream_context;
if (stream && stream->timing.flags.DSC == 1) {bpp = convert_dc_color_depth_into_bpc(stream-timing.display_color_depth)* 3;
clock = stream->timing.pix_clk_100hz / 10;aconnector->pbn = drm_dp_calc_pbn_mode(clock, bpp,true);
aconnector->vcpi_slots =drm_dp_atomic_find_vcpi_slots(state,
&aconnector-mst_port->mst_mgr,
aconnector->port,aconnector->pbn);if (aconnector->vcpi_slots < 0)return aconnector->vcpi_slots;}- }
- return 0;
+} +#endif
- static void dm_drm_plane_reset(struct drm_plane *plane) { struct dm_plane_state *amdgpu_state = NULL;
@@ -7629,11 +7680,6 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, if (ret) goto fail;
- /* Perform validation of MST topology in the state*/
- ret = drm_dp_mst_atomic_check(state);
- if (ret)
goto fail;- if (state->legacy_cursor_update) { /*
- This is a fast cursor update coming from the plane update
@@ -7705,6 +7751,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (!compute_mst_dsc_configs_for_state(dm_state->context)) goto fail;
ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state-context);
if (ret)goto fail;DC_OK) { ret = -EINVAL; @@ -7734,6 +7784,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, dc_retain_state(old_dm_state->context); } }
/* Perform validation of MST topology in the state*/
ret = drm_dp_mst_atomic_check(state);
if (ret)
goto fail;/* Store the overall update type for use later in atomic check. */ for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) {
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index bd694499e3de..3e44e2da2d0d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -201,12 +201,6 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( mst_port = aconnector->port;
if (enable) {
/* Convert kilobits per second / 64 (for 64 timeslots) to pbn(54/64 megabytes per second) */
pbn_per_timeslot = dc_link_bandwidth_kbps(stream->link, dc_link_get_link_cap(stream-link)) / (8 * 1000 * 54);
aconnector->vcpi_slots = DIV_ROUND_UP(aconnector->pbn,pbn_per_timeslot);
- ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, aconnector->pbn, aconnector->vcpi_slots);
On Tue, 2019-10-08 at 21:26 +0000, Mikita Lipski wrote:
On 08.10.2019 12:24, Lyude Paul wrote:
... yikes I need to apologize because I was going through my email and I realized you _did_ respond to me earlier regarding some of these questions, it just appears the reply fell through the cracks and somehow I didn't notice it until just now. Sorry about that!
No worries, the patches got messy and are easily lost in here. I'll clean up on the next batch so it will be clearer what's happening
I'm still not sure I understand why this is a future enhancement? Everything we need to implement these helpers should already be here, it's just a matter of keeping track who has dsc enabled where in the mst atomic state
As I've mentioned earlier our policy for DSC is to keep it disabled if not needed, because it is a lossy compression. Beside the fact that we don't want imperfect image on the screen, enabling DSC would also increase our power consumption. If we need it - we use the greedy algorithm inside compute_mst_dsc_configs_for_link to only enable DSC on streams that can't fit into allowed bandwidth without compression.
I'm not exactly sure how it can be moved as helper to DRM. We keep track on which stream has DSC enabled by raising DSC flag in dc_stream_state flags structure. That it why pbn recalculation was moved to a separate function so only streams that have DSC flag raised get VCPI recalculated.
I guess if we would have dsc_desired flag on drm_connnector_state and it would then perform recalculation of PBN and VCPI for the connector. Would that be something applicable as a DRM helper?
This would probably be a better fit for drm_dp_mst_topology_mgr's atomic state (take a look at the atomic VCPI helpers), specifically in struct drm_dp_mst_vcpi (maybe we should rename it to struct drm_dp_mst_port_bw while we're at it) and store DSC enablement information there. Then we can write a helper to go through all of the enabled ports on the topology and add the affected ones into the atomic state and set ->mode_changed on all of them.
On Mon, 2019-10-07 at 17:52 -0400, Lyude Paul wrote:
Ok, let's stop and slow down for a minute here since I've repeated myself a few times, and I'd like to figure out what's actually happening here and whether I'm not being clear enough with my explanations, or if there's just some misunderstanding here.
I'll start of by trying my best to explain my hesistance in accepting these patches. To be clear, MST with DSC is a big thing in terms of impact. There's a lot of things to consider:
- What should the default DSC policy for MST be? Should we keep it on
by default so that we don't need to trigger a large number of PBN recalculations and enable DSC on a per-case basis, or are there legitimate reasons to keep DSC off by default (such as potential issues with lossiness down the line).
- We have other drivers in the tree that are planning on implementing
MST DSC quite soon. Chances are they'll be implementing helpers to do this so this can be supported across the DRM tree, and chances are we'll just have to rewrite and remove most of this code in that case once they do.
- amdgpu already has a _lot_ of code that doesn't need to, and
shouldn't be there. This ranges from various DC specific helpers that are essentially the same as the helpers that we already implement in the rest of DRM, to misuses of various kernel APIs, and a complete lack of any kind of code style (at least the last time that I checked) in or out of DC. This makes the driver more difficult for people who don't work at AMD but are well accustomed to working on the rest of the kernel, e.g. myself and others, and it's a problem that seriously needs to be solved. Adding more redundant DP helpers that will inevitably get removed is just making the problem worse.
With all of this being said: I've been asking the same questions about this patch throughout the whole patch series so far (since it got passed off to you from David's internship ending):
- Can we keep DSC enabled by default, so that these patches aren't
needed?
- If we can't, can we move this into common code so that other drivers
can use it? The problem is I haven't received any responses to these questions, other then being told by David a month or two ago that it would be expedient to just accept the patches and move on. Honestly, if discussion had been had about the changes I requested, I would have given my r-b a long time ago. In fact- I really want to give it now! There's multiple patches in this series that would be very useful for other things that are being worked on at the moment, such as the changes to drm_dp_dpcd_read/drm_dp_dpcd_write(). But I really think this needs to be discussed first, and I'm worried that just going ahead and giving my R-B before they have been discussed will further encourage rushing changes like this in the future and continually building more tech debt for ourselves.
Please note as well: if anything I've asked for is confusing, or you don't understand what I'm asking or looking for I am more then willing to help explain things and help out as best as I can. I understand that a lot of the developers working on DRM at AMD may have more experience in Windows and Mac land and as a result, trying to get used to the way that we do things in the Linux kernel can be a confusing endeavor. I'm more then happy to help out with this wherever I can, all you need to do is ask. Asking a few questions about something you aren't sure you understand can save both of us a lot of time, and avoid having to go through this many patch respins.
In the mean time, I'd be willing to look at what patches from this series that have already been reviewed which could be pushed to drm-misc or friends in the mean time to speed things up a bit.
On Tue, 2019-10-01 at 12:17 -0400, mikita.lipski@amd.com wrote:
From: Mikita Lipski mikita.lipski@amd.com
Since for DSC MST connector's PBN is claculated differently due to compression, we have to recalculate both PBN and VCPI slots for that connector.
This patch proposes to use similair logic as in dm_encoder_helper_atomic_chek, but since we do not know which connectors will have DSC enabled we have to recalculate PBN only after that's determined, which is done in compute_mst_dsc_configs_for_state.
Cc: Jerry Zuo Jerry.Zuo@amd.com Cc: Harry Wentland harry.wentland@amd.com Cc: Lyude Paul lyude@redhat.com Signed-off-by: Mikita Lipski mikita.lipski@amd.com
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 64 +++++++++++++++++-- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 6 -- 2 files changed, 59 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 81e30918f9ec..7501ce2233ed 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4569,6 +4569,27 @@ static void dm_encoder_helper_disable(struct drm_encoder *encoder)
}
+static int convert_dc_color_depth_into_bpc (enum dc_color_depth display_color_depth) +{
- switch (display_color_depth) {
case COLOR_DEPTH_666:return 6;case COLOR_DEPTH_888:return 8;case COLOR_DEPTH_101010:return 10;case COLOR_DEPTH_121212:return 12;case COLOR_DEPTH_141414:return 14;case COLOR_DEPTH_161616:return 16;default:break;}- return 0;
+}
- static int dm_encoder_helper_atomic_check(struct drm_encoder
*encoder, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) @@ -4616,6 +4637,36 @@ const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { .atomic_check = dm_encoder_helper_atomic_check };
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT +static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
struct dc_state *dc_state)+{
- struct dc_stream_state *stream;
- struct amdgpu_dm_connector *aconnector;
- int i, clock = 0, bpp = 0;
- for (i = 0; i < dc_state->stream_count; i++) {
stream = dc_state->streams[i];aconnector = (struct amdgpu_dm_connector *)stream-dm_stream_context;
if (stream && stream->timing.flags.DSC == 1) {bpp = convert_dc_color_depth_into_bpc(stream-timing.display_color_depth)* 3;
clock = stream->timing.pix_clk_100hz / 10;aconnector->pbn = drm_dp_calc_pbn_mode(clock,bpp, true);
aconnector->vcpi_slots =drm_dp_atomic_find_vcpi_slots(state,
&aconnector-mst_port->mst_mgr,
aconnector-port,
aconnector-pbn);
if (aconnector->vcpi_slots < 0)return aconnector->vcpi_slots;}- }
- return 0;
+} +#endif
- static void dm_drm_plane_reset(struct drm_plane *plane) { struct dm_plane_state *amdgpu_state = NULL;
@@ -7629,11 +7680,6 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, if (ret) goto fail;
- /* Perform validation of MST topology in the state*/
- ret = drm_dp_mst_atomic_check(state);
- if (ret)
goto fail;- if (state->legacy_cursor_update) { /*
- This is a fast cursor update coming from the plane
update @@ -7705,6 +7751,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (!compute_mst_dsc_configs_for_state(dm_state-
context))
goto fail;
ret = dm_update_mst_vcpi_slots_for_dsc(state,dm_state-
context);
if (ret)goto fail;false) != DC_OK) { ret = -EINVAL; @@ -7734,6 +7784,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, dc_retain_state(old_dm_state-
context);
}}
/* Perform validation of MST topology in the state*/
ret = drm_dp_mst_atomic_check(state);
if (ret)
goto fail;/* Store the overall update type for use later in atomic
check. */ for_each_new_crtc_in_state (state, crtc, new_crtc_state, i) { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index bd694499e3de..3e44e2da2d0d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -201,12 +201,6 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( mst_port = aconnector->port;
if (enable) {
/* Convert kilobits per second / 64 (for 64 timeslots)to pbn (54/64 megabytes per second) */
pbn_per_timeslot = dc_link_bandwidth_kbps(stream->link,dc_link_get_link_cap(stream-
link)) / (8 * 1000 * 54);
aconnector->vcpi_slots = DIV_ROUND_UP(aconnector->pbn,pbn_per_timeslot);
- ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, aconnector->pbn, aconnector-
vcpi_slots);
-- Thanks, Mikita Lipski Software Engineer, AMD mikita.lipski@amd.com
dri-devel@lists.freedesktop.org
-
Lyude Paul -
Mikita Lipski -
mikita.lipski＠amd.com