We have a few more DG2 workarounds that weren't included in the initial batch.
v2: - Apply pipe control workaround to rcs indirect context rather than xcs indirect context.
v3: - s/IS_DG2_DISP_STEP/IS_DG2_DISPLAY_STEPPING/ for consistency with other platforms.
Matt Atwood (1): drm/i915/dg2: extend Wa_1409120013 to DG2
Matt Roper (3): drm/i915/dg2: s/DISP_STEPPING/DISPLAY_STEPPING/ drm/i915/dg2: Add Wa_14010547955 drm/i915/dg2: Add Wa_16011777198
Ramalingam C (1): drm/i915/dg2: Add Wa_16013000631
drivers/gpu/drm/i915/display/intel_display.c | 4 ++++ drivers/gpu/drm/i915/gt/intel_lrc.c | 5 +++++ drivers/gpu/drm/i915/gt/intel_rc6.c | 15 +++++++++++---- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/i915_reg.h | 5 +++-- drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 6 files changed, 26 insertions(+), 9 deletions(-)
Commit cd0fcf5af791 ("drm/i915: rename DISP_STEPPING->DISPLAY_STEP and GT_STEPPING->GT_STEP") renamed all platforms' display stepping tests, but the DG2 patches were still in-flight at that time and did not incorporate the new naming scheme. Rename DG2's macro now for consistency with other platforms.
Cc: Jani Nikula jani.nikula@linux.intel.com Signed-off-by: Matt Roper matthew.d.roper@intel.com --- drivers/gpu/drm/i915/i915_drv.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 6f9f20a10c0c..b3404041294d 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1598,7 +1598,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, (IS_SUBPLATFORM(__i915, INTEL_DG2, INTEL_SUBPLATFORM_##variant) && \ IS_GRAPHICS_STEP(__i915, since, until))
-#define IS_DG2_DISP_STEP(__i915, since, until) \ +#define IS_DG2_DISPLAY_STEP(__i915, since, until) \ (IS_DG2(__i915) && \ IS_DISPLAY_STEP(__i915, since, until))
On Tue, 16 Nov 2021, Matt Roper matthew.d.roper@intel.com wrote:
Commit cd0fcf5af791 ("drm/i915: rename DISP_STEPPING->DISPLAY_STEP and GT_STEPPING->GT_STEP") renamed all platforms' display stepping tests, but the DG2 patches were still in-flight at that time and did not incorporate the new naming scheme. Rename DG2's macro now for consistency with other platforms.
Cc: Jani Nikula jani.nikula@linux.intel.com Signed-off-by: Matt Roper matthew.d.roper@intel.com
Reviewed-by: Jani Nikula jani.nikula@intel.com
drivers/gpu/drm/i915/i915_drv.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 6f9f20a10c0c..b3404041294d 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1598,7 +1598,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, (IS_SUBPLATFORM(__i915, INTEL_DG2, INTEL_SUBPLATFORM_##variant) && \ IS_GRAPHICS_STEP(__i915, since, until))
-#define IS_DG2_DISP_STEP(__i915, since, until) \ +#define IS_DG2_DISPLAY_STEP(__i915, since, until) \ (IS_DG2(__i915) && \ IS_DISPLAY_STEP(__i915, since, until))
This workaround is documented a bit strangely in the bspec; it's listed as an A0 workaround, but the description clarifies that the workaround is implicitly handled by the hardware and what the driver really needs to do is program a chicken bit to reenable some internal behavior.
Signed-off-by: Matt Roper matthew.d.roper@intel.com --- drivers/gpu/drm/i915/display/intel_display.c | 4 ++++ drivers/gpu/drm/i915/i915_reg.h | 5 +++-- 2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 0ceee8ac6671..1639bdbe2091 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -988,6 +988,10 @@ static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state) else if (DISPLAY_VER(dev_priv) >= 13) tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP;
+ /* Wa_14010547955:dg2 */ + if (IS_DG2_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER)) + tmp |= DG2_RENDER_CCSTAG_4_3_EN; + intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp); }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f15ffc53e858..c187ec122fdb 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8568,8 +8568,9 @@ enum { _PIPEB_CHICKEN) #define UNDERRUN_RECOVERY_DISABLE_ADLP REG_BIT(30) #define UNDERRUN_RECOVERY_ENABLE_DG2 REG_BIT(30) -#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU (1 << 15) -#define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7) +#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU REG_BIT(15) +#define DG2_RENDER_CCSTAG_4_3_EN REG_BIT(12) +#define PER_PIXEL_ALPHA_BYPASS_EN REG_BIT(7)
#define VFLSKPD _MMIO(0x62a8) #define DIS_OVER_FETCH_CACHE REG_BIT(1)
Looks correct.
Reviewed-by: Clint Taylor Clinton.A.Taylor@intel.com
-Clint
On 11/16/21 9:48 AM, Matt Roper wrote:
This workaround is documented a bit strangely in the bspec; it's listed as an A0 workaround, but the description clarifies that the workaround is implicitly handled by the hardware and what the driver really needs to do is program a chicken bit to reenable some internal behavior.
Signed-off-by: Matt Roper matthew.d.roper@intel.com
drivers/gpu/drm/i915/display/intel_display.c | 4 ++++ drivers/gpu/drm/i915/i915_reg.h | 5 +++-- 2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 0ceee8ac6671..1639bdbe2091 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -988,6 +988,10 @@ static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state) else if (DISPLAY_VER(dev_priv) >= 13) tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP;
- /* Wa_14010547955:dg2 */
- if (IS_DG2_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER))
tmp |= DG2_RENDER_CCSTAG_4_3_EN;- intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp); }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f15ffc53e858..c187ec122fdb 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8568,8 +8568,9 @@ enum { _PIPEB_CHICKEN) #define UNDERRUN_RECOVERY_DISABLE_ADLP REG_BIT(30) #define UNDERRUN_RECOVERY_ENABLE_DG2 REG_BIT(30) -#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU (1 << 15) -#define PER_PIXEL_ALPHA_BYPASS_EN (1 << 7) +#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU REG_BIT(15) +#define DG2_RENDER_CCSTAG_4_3_EN REG_BIT(12) +#define PER_PIXEL_ALPHA_BYPASS_EN REG_BIT(7)
#define VFLSKPD _MMIO(0x62a8) #define DIS_OVER_FETCH_CACHE REG_BIT(1)
Coarse power gating for render should not be enabled on some DG2 steppings.
Bspec: 52698 Signed-off-by: Matt Roper matthew.d.roper@intel.com --- drivers/gpu/drm/i915/gt/intel_rc6.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c index 43093dd2d0c9..c3155ee58689 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6.c +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c @@ -117,10 +117,17 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6) GEN6_RC_CTL_RC6_ENABLE | GEN6_RC_CTL_EI_MODE(1);
- pg_enable = - GEN9_RENDER_PG_ENABLE | - GEN9_MEDIA_PG_ENABLE | - GEN11_MEDIA_SAMPLER_PG_ENABLE; + /* Wa_16011777198 - Render powergating must remain disabled */ + if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) || + IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0)) + pg_enable = + GEN9_MEDIA_PG_ENABLE | + GEN11_MEDIA_SAMPLER_PG_ENABLE; + else + pg_enable = + GEN9_RENDER_PG_ENABLE | + GEN9_MEDIA_PG_ENABLE | + GEN11_MEDIA_SAMPLER_PG_ENABLE;
if (GRAPHICS_VER(gt->i915) >= 12) { for (i = 0; i < I915_MAX_VCS; i++)
Correct,
Reviewed-by: Clint Taylor Clinton.A.Taylor@intel.com
-Clint
On 11/16/21 9:48 AM, Matt Roper wrote:
Coarse power gating for render should not be enabled on some DG2 steppings.
Bspec: 52698 Signed-off-by: Matt Roper matthew.d.roper@intel.com
drivers/gpu/drm/i915/gt/intel_rc6.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c index 43093dd2d0c9..c3155ee58689 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6.c +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c @@ -117,10 +117,17 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6) GEN6_RC_CTL_RC6_ENABLE | GEN6_RC_CTL_EI_MODE(1);
- pg_enable =
GEN9_RENDER_PG_ENABLE |GEN9_MEDIA_PG_ENABLE |GEN11_MEDIA_SAMPLER_PG_ENABLE;
/* Wa_16011777198 - Render powergating must remain disabled */
if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||
IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0))pg_enable =GEN9_MEDIA_PG_ENABLE |GEN11_MEDIA_SAMPLER_PG_ENABLE;else
pg_enable =GEN9_RENDER_PG_ENABLE |GEN9_MEDIA_PG_ENABLE |GEN11_MEDIA_SAMPLER_PG_ENABLE;if (GRAPHICS_VER(gt->i915) >= 12) { for (i = 0; i < I915_MAX_VCS; i++)
From: Ramalingam C ramalingam.c@intel.com
Invalidate IC cache through pipe control command as part of the ctx restore flow through indirect ctx pointer.
v2: - Move pipe control from xcs indirect context to the rcs indirect context. We'll eventually need this on the CCS engines too, but support for those hasn't landed yet.
Cc: Chris Wilson chris.p.wilson@intel.com Signed-off-by: Ramalingam C ramalingam.c@intel.com Signed-off-by: Matt Roper matthew.d.roper@intel.com --- drivers/gpu/drm/i915/gt/intel_lrc.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 56156cf18c41..b3489599e4de 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1167,6 +1167,11 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs) cs = gen12_emit_cmd_buf_wa(ce, cs); cs = gen12_emit_restore_scratch(ce, cs);
+ /* Wa_16013000631:dg2 */ + if (IS_DG2_GRAPHICS_STEP(ce->engine->i915, G10, STEP_B0, STEP_C0) || + IS_DG2_G11(ce->engine->i915)) + cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE, 0); + return cs; }
Reviewed-by: Clint Taylor Clinton.A.Taylor@intel.com
-Clint
On 11/16/21 9:48 AM, Matt Roper wrote:
From: Ramalingam C ramalingam.c@intel.com
Invalidate IC cache through pipe control command as part of the ctx restore flow through indirect ctx pointer.
v2:
- Move pipe control from xcs indirect context to the rcs indirect context. We'll eventually need this on the CCS engines too, but support for those hasn't landed yet.
Cc: Chris Wilson chris.p.wilson@intel.com Signed-off-by: Ramalingam C ramalingam.c@intel.com Signed-off-by: Matt Roper matthew.d.roper@intel.com
drivers/gpu/drm/i915/gt/intel_lrc.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 56156cf18c41..b3489599e4de 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1167,6 +1167,11 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs) cs = gen12_emit_cmd_buf_wa(ce, cs); cs = gen12_emit_restore_scratch(ce, cs);
- /* Wa_16013000631:dg2 */
- if (IS_DG2_GRAPHICS_STEP(ce->engine->i915, G10, STEP_B0, STEP_C0) ||
IS_DG2_G11(ce->engine->i915))cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE, 0);- return cs; }
From: Matt Atwood matthew.s.atwood@intel.com
Extend existing workaround 1409120013 to DG2.
Cc: José Roberto de Souza jose.souza@intel.com Signed-off-by: Matt Atwood matthew.s.atwood@intel.com Signed-off-by: Matt Roper matthew.d.roper@intel.com --- drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 89dc7f69baf3..e721c421cc58 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -7444,9 +7444,9 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv) { - /* Wa_1409120013:tgl,rkl,adl-s,dg1 */ + /* Wa_1409120013:tgl,rkl,adl-s,dg1,dg2 */ if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv) || - IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) + IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv) || IS_DG2(dev_priv)) intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, DPFC_CHICKEN_COMP_DUMMY_PIXEL);
On Tue, Nov 16, 2021 at 09:48:18AM -0800, Matt Roper wrote:
From: Matt Atwood matthew.s.atwood@intel.com
Extend existing workaround 1409120013 to DG2.
I don't see this listed for DG2.
Cc: José Roberto de Souza jose.souza@intel.com Signed-off-by: Matt Atwood matthew.s.atwood@intel.com Signed-off-by: Matt Roper matthew.d.roper@intel.com
drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 89dc7f69baf3..e721c421cc58 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -7444,9 +7444,9 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv) {
- /* Wa_1409120013:tgl,rkl,adl-s,dg1 */
- /* Wa_1409120013:tgl,rkl,adl-s,dg1,dg2 */ if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv))
IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv) || IS_DG2(dev_priv))-- 2.33.0
On Wed, Nov 17, 2021 at 08:43:19PM +0200, Ville Syrjälä wrote:
On Tue, Nov 16, 2021 at 09:48:18AM -0800, Matt Roper wrote:
From: Matt Atwood matthew.s.atwood@intel.com
Extend existing workaround 1409120013 to DG2.
I don't see this listed for DG2.
This seems to be problem with the DG2 query since for some reason they marked this workaround as 'driver_change_required' rather than 'driver_permanent_wa' in the database and that prevents it from showing up in some of the queries properly. The DG2-specific ID number to check is 1409222275.
Matt
Cc: José Roberto de Souza jose.souza@intel.com Signed-off-by: Matt Atwood matthew.s.atwood@intel.com Signed-off-by: Matt Roper matthew.d.roper@intel.com
drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 89dc7f69baf3..e721c421cc58 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -7444,9 +7444,9 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv) {
- /* Wa_1409120013:tgl,rkl,adl-s,dg1 */
- /* Wa_1409120013:tgl,rkl,adl-s,dg1,dg2 */ if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv))
IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv) || IS_DG2(dev_priv))-- 2.33.0
-- Ville Syrjälä Intel
On Wed, Nov 17, 2021 at 10:51:39AM -0800, Matt Roper wrote:
On Wed, Nov 17, 2021 at 08:43:19PM +0200, Ville Syrjälä wrote:
On Tue, Nov 16, 2021 at 09:48:18AM -0800, Matt Roper wrote:
From: Matt Atwood matthew.s.atwood@intel.com
Extend existing workaround 1409120013 to DG2.
I don't see this listed for DG2.
This seems to be problem with the DG2 query since for some reason they marked this workaround as 'driver_change_required' rather than 'driver_permanent_wa' in the database and that prevents it from showing up in some of the queries properly. The DG2-specific ID number to check is 1409222275.
Bit of mes that one. I can't really figure out if dg2 is the only d13 platform that needs this or might there be others?
On Wed, Nov 17, 2021 at 08:43:19PM +0200, Ville Syrjälä wrote:
On Tue, Nov 16, 2021 at 09:48:18AM -0800, Matt Roper wrote:
From: Matt Atwood matthew.s.atwood@intel.com
Extend existing workaround 1409120013 to DG2.
I don't see this listed for DG2.
Cc: José Roberto de Souza jose.souza@intel.com Signed-off-by: Matt Atwood matthew.s.atwood@intel.com Signed-off-by: Matt Roper matthew.d.roper@intel.com
drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 89dc7f69baf3..e721c421cc58 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -7444,9 +7444,9 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv) {
- /* Wa_1409120013:tgl,rkl,adl-s,dg1 */
- /* Wa_1409120013:tgl,rkl,adl-s,dg1,dg2 */ if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv))
IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv) || IS_DG2(dev_priv))
AFAIK we're not even calling this function on dg2, so this is just dead code. And in fact without dg2 this seems to be the same as DISPLAY_VER==12 so we shuld stop calling it on adl-p as well. We could then rip out most of the platform checks in here.
intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN, DPFC_CHICKEN_COMP_DUMMY_PIXEL);-- 2.33.0
-- Ville Syrjälä Intel
On Tue, 2021-11-16 at 09:48 -0800, Matt Roper wrote:
From: Matt Atwood matthew.s.atwood@intel.com
Extend existing workaround 1409120013 to DG2.
Cc: José Roberto de Souza jose.souza@intel.com Signed-off-by: Matt Atwood matthew.s.atwood@intel.com Signed-off-by: Matt Roper matthew.d.roper@intel.com
drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 89dc7f69baf3..e721c421cc58 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -7444,9 +7444,9 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv) {
- /* Wa_1409120013:tgl,rkl,adl-s,dg1 */
- /* Wa_1409120013:tgl,rkl,adl-s,dg1,dg2 */
I'm not finding this workaround in the DG2 WA spec page, maybe it was removed because it is not necessary anymore?
if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv))
IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv) || IS_DG2(dev_priv))
On Fri, Nov 19, 2021 at 08:36:56AM -0800, Souza, Jose wrote:
On Tue, 2021-11-16 at 09:48 -0800, Matt Roper wrote:
From: Matt Atwood matthew.s.atwood@intel.com
Extend existing workaround 1409120013 to DG2.
Cc: José Roberto de Souza jose.souza@intel.com Signed-off-by: Matt Atwood matthew.s.atwood@intel.com Signed-off-by: Matt Roper matthew.d.roper@intel.com
drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 89dc7f69baf3..e721c421cc58 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -7444,9 +7444,9 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv) {
- /* Wa_1409120013:tgl,rkl,adl-s,dg1 */
- /* Wa_1409120013:tgl,rkl,adl-s,dg1,dg2 */
I'm not finding this workaround in the DG2 WA spec page, maybe it was removed because it is not necessary anymore?
Ville raised the same question; I believe this is just an issue with the query that generates the bspec page from the database; here's my earlier response:
>> This seems to be problem with the DG2 query since for some >> reason they marked this workaround as >> 'driver_change_required' rather than 'driver_permanent_wa' in >> the database and that prevents it from showing up in some of >> the queries properly. The DG2-specific ID number to check is >> 1409222275.
Since it appears this is currently needed on every version 12 and version 13 display platform _except_ for ADL-P, I did send a question to the HW team to confirm that the lack of ADL-P isn't an oversight, but I haven't heard back yet.
Matt
if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv))
IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv) || IS_DG2(dev_priv))
Reviewed-by: Clint Taylor Clinton.A.Taylor@intel.com
-Clint
On 11/16/21 9:48 AM, Matt Roper wrote:
From: Matt Atwood matthew.s.atwood@intel.com
Extend existing workaround 1409120013 to DG2.
Cc: José Roberto de Souza jose.souza@intel.com Signed-off-by: Matt Atwood matthew.s.atwood@intel.com Signed-off-by: Matt Roper matthew.d.roper@intel.com
drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 89dc7f69baf3..e721c421cc58 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -7444,9 +7444,9 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv) {
- /* Wa_1409120013:tgl,rkl,adl-s,dg1 */
- /* Wa_1409120013:tgl,rkl,adl-s,dg1,dg2 */ if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv))
IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv) || IS_DG2(dev_priv))
dri-devel@lists.freedesktop.org
-
Clint Taylor -
Jani Nikula -
Matt Roper -
Souza, Jose -
Ville Syrjälä