From: Conor Dooley conor.dooley@microchip.com
Hey all, This series should rid us of dtbs_check errors for the RISC-V Canaan k210 based boards (well, unless you enable W=1 but that's another days work). I *DO NOT* have any Canaan hardware so I have not tested any of this in anger. I based the series on next-20220617.
For the bindings, I am never sure about which of {unevaluated,additional} Properties is correct to use, but the if statements in the binding didn't work with additional so I used unevaluated...
@Mark, for your two bindings I was not sure about the properties that I made depend on the compatible, but I looked in tree and was not able to find other users to contradict what's in the Canaan devicetrees nor did I get that much help from their docs.
@Rob, yesterday's removal of ilitek,ili9341.txt is moved to ths series since I was editing the dt-schema binding here anyway.
Finally, @Palmer: This + Atul's stuff + the sifive dts watchdog patch will get us sorted in terms of dtbs_check errors. To make keeping it that way a little easier, I changed the Canaan devicetree Makefile so that it would build all of the devicetrees in the directory if SOC_CANAAN. Hopefully someone with a device can test it - but my build log *looked* fine but that's not exactly sufficient.
Thanks, Conor.
Conor Dooley (14): dt-bindings: display: convert ilitek,ili9341.txt to dt-schema dt-bindings: display: panel: allow ilitek,ili9341 in isolation ASoC: dt-bindings: convert designware-i2s to dt-schema dt-bindings: dma: add Canaan k210 to Synopsys DesignWare DMA dt-bindings: timer: add Canaan k210 to Synopsys DesignWare timer spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi riscv: dts: canaan: fix the k210's memory node riscv: dts: canaan: add a specific compatible for k210's dma riscv: dts: canaan: add a specific compatible for k210's timers riscv: dts: canaan: fix mmc node names riscv: dts: canaan: fix kd233 display spi frequency riscv: dts: canaan: use custom compatible for k210 i2s riscv: dts: canaan: remove spi-max-frequency from controllers riscv: dts: canaan: build all devicetress if SOC_CANAAN
.../bindings/display/ilitek,ili9341.txt | 27 ------ .../display/panel/ilitek,ili9341.yaml | 60 ++++++++---- .../bindings/dma/snps,dw-axi-dmac.yaml | 35 +++++-- .../bindings/sound/designware-i2s.txt | 35 ------- .../bindings/sound/snps,designware-i2s.yaml | 93 +++++++++++++++++++ .../bindings/spi/snps,dw-apb-ssi.yaml | 48 +++++++--- .../bindings/timer/snps,dw-apb-timer.yaml | 28 ++++-- arch/riscv/boot/dts/canaan/Makefile | 10 +- arch/riscv/boot/dts/canaan/canaan_kd233.dts | 4 +- arch/riscv/boot/dts/canaan/k210.dtsi | 25 ++--- .../riscv/boot/dts/canaan/sipeed_maix_bit.dts | 2 +- .../boot/dts/canaan/sipeed_maix_dock.dts | 2 +- arch/riscv/boot/dts/canaan/sipeed_maix_go.dts | 2 +- .../boot/dts/canaan/sipeed_maixduino.dts | 2 +- 14 files changed, 239 insertions(+), 134 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/ilitek,ili9341.txt delete mode 100644 Documentation/devicetree/bindings/sound/designware-i2s.txt create mode 100644 Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml
base-commit: 07dc787be2316e243a16a33d0a9b734cd9365bd3
From: Conor Dooley conor.dooley@microchip.com
A dt-schema binding for the Ilitek ili9341 was created as panel/ilitek,ili9341.yaml but the txt binding was ignored in the process. Move the remaining items in the txt binding to the yaml one & delete it.
The example in the txt binding has a spi-max-frequency which disagrees with the yaml replacement (and its own documentation) so change that to conform with the binding. There are no users in tree of the Adafruit yx240qv29 to check against.
Link: https://cdn-learn.adafruit.com/assets/assets/000/046/879/original/SPEC-YX240... Signed-off-by: Conor Dooley conor.dooley@microchip.com --- .../bindings/display/ilitek,ili9341.txt | 27 ----------- .../display/panel/ilitek,ili9341.yaml | 48 +++++++++++++------ 2 files changed, 34 insertions(+), 41 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/ilitek,ili9341.txt
diff --git a/Documentation/devicetree/bindings/display/ilitek,ili9341.txt b/Documentation/devicetree/bindings/display/ilitek,ili9341.txt deleted file mode 100644 index 169b32e4ee4e..000000000000 --- a/Documentation/devicetree/bindings/display/ilitek,ili9341.txt +++ /dev/null @@ -1,27 +0,0 @@ -Ilitek ILI9341 display panels - -This binding is for display panels using an Ilitek ILI9341 controller in SPI -mode. - -Required properties: -- compatible: "adafruit,yx240qv29", "ilitek,ili9341" -- dc-gpios: D/C pin -- reset-gpios: Reset pin - -The node for this driver must be a child node of a SPI controller, hence -all mandatory properties described in ../spi/spi-bus.txt must be specified. - -Optional properties: -- rotation: panel rotation in degrees counter clockwise (0,90,180,270) -- backlight: phandle of the backlight device attached to the panel - -Example: - display@0{ - compatible = "adafruit,yx240qv29", "ilitek,ili9341"; - reg = <0>; - spi-max-frequency = <32000000>; - dc-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; - rotation = <270>; - backlight = <&backlight>; - }; diff --git a/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml b/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml index 6058948a9764..94ca92878434 100644 --- a/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml +++ b/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml @@ -23,6 +23,7 @@ properties: - enum: # ili9341 240*320 Color on stm32f429-disco board - st,sf-tc240t-9370-t + - adafruit,yx240qv29 - const: ilitek,ili9341
reg: true @@ -47,31 +48,50 @@ properties: vddi-led-supply: description: Voltage supply for the LED driver (1.65 .. 3.3 V)
-additionalProperties: false +unevaluatedProperties: false
required: - compatible - reg - dc-gpios - - port + +if: + properties: + compatible: + contains: + enum: + - st,sf-tc240t-9370-t +then: + required: + - port
examples: - |+ + #include <dt-bindings/gpio/gpio.h> spi { #address-cells = <1>; #size-cells = <0>; panel: display@0 { - compatible = "st,sf-tc240t-9370-t", - "ilitek,ili9341"; - reg = <0>; - spi-3wire; - spi-max-frequency = <10000000>; - dc-gpios = <&gpiod 13 0>; - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; + compatible = "st,sf-tc240t-9370-t", + "ilitek,ili9341"; + reg = <0>; + spi-3wire; + spi-max-frequency = <10000000>; + dc-gpios = <&gpiod 13 0>; + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + display@1{ + compatible = "adafruit,yx240qv29", "ilitek,ili9341"; + reg = <1>; + spi-max-frequency = <10000000>; + dc-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; + rotation = <270>; + backlight = <&backlight>; }; + }; ...
From: Conor Dooley conor.dooley@microchip.com
The dt-binding for the ilitek,ili9341 does not allow it to be used as a compatible in isolation. This generates a warning for the Canaan kd233 devicetree: arch/riscv/boot/dts/canaan/canaan_kd233.dtb: panel@0: compatible:0: 'ilitek,ili9341' is not one of ['st,sf-tc240t-9370-t'] From schema: Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml arch/riscv/boot/dts/canaan/canaan_kd233.dtb: panel@0: compatible: ['ilitek,ili9341'] is too short From schema: Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml Allow ilitek,ili9341 to be selected in isolation.
Signed-off-by: Conor Dooley conor.dooley@microchip.com --- .../bindings/display/panel/ilitek,ili9341.yaml | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml b/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml index 94ca92878434..c402bedaa37a 100644 --- a/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml +++ b/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml @@ -19,12 +19,14 @@ allOf:
properties: compatible: - items: - - enum: - # ili9341 240*320 Color on stm32f429-disco board - - st,sf-tc240t-9370-t - - adafruit,yx240qv29 - - const: ilitek,ili9341 + oneOf: + - items: + - const: ilitek,ili9341 + - items: + - enum: + - st,sf-tc240t-9370-t + - adafruit,yx240qv29 + - const: ilitek,ili9341
reg: true
From: Conor Dooley conor.dooley@microchip.com
Convert the Synopsys DesignWare I2S controller binding to dt-schema. There was no listed maintainer but Jose Abreu was the last editor of the txt binding so add him as maintainer.
Signed-off-by: Conor Dooley conor.dooley@microchip.com --- .../bindings/sound/designware-i2s.txt | 35 ------- .../bindings/sound/snps,designware-i2s.yaml | 93 +++++++++++++++++++ 2 files changed, 93 insertions(+), 35 deletions(-) delete mode 100644 Documentation/devicetree/bindings/sound/designware-i2s.txt create mode 100644 Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml
diff --git a/Documentation/devicetree/bindings/sound/designware-i2s.txt b/Documentation/devicetree/bindings/sound/designware-i2s.txt deleted file mode 100644 index 6a536d570e29..000000000000 --- a/Documentation/devicetree/bindings/sound/designware-i2s.txt +++ /dev/null @@ -1,35 +0,0 @@ -DesignWare I2S controller - -Required properties: - - compatible : Must be "snps,designware-i2s" - - reg : Must contain the I2S core's registers location and length - - clocks : Pairs of phandle and specifier referencing the controller's - clocks. The controller expects one clock: the clock used as the sampling - rate reference clock sample. - - clock-names : "i2sclk" for the sample rate reference clock. - - dmas: Pairs of phandle and specifier for the DMA channels that are used by - the core. The core expects one or two dma channels: one for transmit and - one for receive. - - dma-names : "tx" for the transmit channel, "rx" for the receive channel. - -Optional properties: - - interrupts: The interrupt line number for the I2S controller. Add this - parameter if the I2S controller that you are using does not support DMA. - -For more details on the 'dma', 'dma-names', 'clock' and 'clock-names' -properties please check: - * resource-names.txt - * clock/clock-bindings.txt - * dma/dma.txt - -Example: - - soc_i2s: i2s@7ff90000 { - compatible = "snps,designware-i2s"; - reg = <0x0 0x7ff90000 0x0 0x1000>; - clocks = <&scpi_i2sclk 0>; - clock-names = "i2sclk"; - #sound-dai-cells = <0>; - dmas = <&dma0 5>; - dma-names = "tx"; - }; diff --git a/Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml b/Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml new file mode 100644 index 000000000000..5ac9c00157bf --- /dev/null +++ b/Documentation/devicetree/bindings/sound/snps,designware-i2s.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/snps,designware-i2s.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: DesignWare I2S controller + +maintainers: + - Jose Abreu joabreu@synopsys.com + +properties: + compatible: + oneOf: + - items: + - const: canaan,k210-i2s + - const: snps,designware-i2s + - enum: + - snps,designware-i2s + + reg: + maxItems: 1 + + interrupts: + description: | + The interrupt line number for the I2S controller. Add this + parameter if the I2S controller that you are using does not + support DMA. + maxItems: 1 + + clocks: + description: Sampling rate reference clock + + clock-names: + const: i2sclk + + resets: + maxItems: 1 + + dmas: + items: + - description: TX DMA Channel + - description: RX DMA Channel + minItems: 1 + + dma-names: + items: + - const: tx + - const: rx + minItems: 1 + +if: + properties: + compatible: + contains: + const: canaan,k210-i2s + +then: + properties: + "#sound-dai-cells": + const: 1 + +else: + properties: + "#sound-dai-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + +oneOf: + - required: + - dmas + - dma-names + - required: + - interrupts + +unevaluatedProperties: false + +examples: + - | + soc_i2s: i2s@7ff90000 { + compatible = "snps,designware-i2s"; + reg = <0x7ff90000 0x1000>; + clocks = <&scpi_i2sclk 0>; + clock-names = "i2sclk"; + #sound-dai-cells = <0>; + dmas = <&dma0 5>; + dma-names = "tx"; + };
From: Conor Dooley conor.dooley@microchip.com
The Canaan k210 apparently has a Sysnopsys Designware AXI DMA controller, but according to the documentation & devicetree it has 6 interrupts rather than the standard one. Add a custom compatible that supports the 6 interrupt configuration which falls back to the standard binding which is currently the one in use in the devicetree entry.
Link: https://canaan-creative.com/wp-content/uploads/2020/03/kendryte_standalone_p... #Page 58 Signed-off-by: Conor Dooley conor.dooley@microchip.com --- .../bindings/dma/snps,dw-axi-dmac.yaml | 35 ++++++++++++++----- 1 file changed, 26 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml index 4324a94b26b2..bc85598151ef 100644 --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml @@ -18,9 +18,13 @@ allOf:
properties: compatible: - enum: - - snps,axi-dma-1.01a - - intel,kmb-axi-dma + oneOf: + - items: + - const: canaan,k210-axi-dma + - const: snps,axi-dma-1.01a + - enum: + - snps,axi-dma-1.01a + - intel,kmb-axi-dma
reg: minItems: 1 @@ -33,9 +37,6 @@ properties: - const: axidma_ctrl_regs - const: axidma_apb_regs
- interrupts: - maxItems: 1 - clocks: items: - description: Bus Clock @@ -92,6 +93,22 @@ properties: minimum: 1 maximum: 256
+if: + properties: + compatible: + contains: + const: canaan,k210-axi-dma + +then: + properties: + interrupts: + maxItems: 6 + +else: + properties: + interrupts: + maxItems: 1 + required: - compatible - reg @@ -105,7 +122,7 @@ required: - snps,priority - snps,block-size
-additionalProperties: false +unevaluatedProperties: false
examples: - | @@ -113,12 +130,12 @@ examples: #include <dt-bindings/interrupt-controller/irq.h> /* example with snps,dw-axi-dmac */ dmac: dma-controller@80000 { - compatible = "snps,axi-dma-1.01a"; + compatible = "canaan,k210-axi-dma", "snps,axi-dma-1.01a"; reg = <0x80000 0x400>; clocks = <&core_clk>, <&cfgr_clk>; clock-names = "core-clk", "cfgr-clk"; interrupt-parent = <&intc>; - interrupts = <27>; + interrupts = <27>, <28>, <29>, <30>, <31>, <32>; #dma-cells = <1>; dma-channels = <4>; snps,dma-masters = <2>;
From: Conor Dooley conor.dooley@microchip.com
The Canaan k210 apparently has a Sysnopsys Designware timer but according to the documentation & devicetree it has 2 interrupts rather than the standard one. Add a custom compatible that supports the 2 interrupt configuration and falls back to the standard binding (which is currently the one in use in the devicetree entry).
Link: https://canaan-creative.com/wp-content/uploads/2020/03/kendryte_standalone_p... #Page 58 Signed-off-by: Conor Dooley conor.dooley@microchip.com --- .../bindings/timer/snps,dw-apb-timer.yaml | 28 +++++++++++++++---- 1 file changed, 22 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml index d33c9205a909..9a76acc7a66f 100644 --- a/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml +++ b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml @@ -12,6 +12,9 @@ maintainers: properties: compatible: oneOf: + - items: + - const: canaan,k210-apb-timer + - const: snps,dw-apb-timer - const: snps,dw-apb-timer - enum: - snps,dw-apb-timer-sp @@ -21,9 +24,6 @@ properties: reg: maxItems: 1
- interrupts: - maxItems: 1 - resets: maxItems: 1
@@ -41,7 +41,23 @@ properties:
clock-frequency: true
-additionalProperties: false +unevaluatedProperties: false + +if: + properties: + compatible: + contains: + const: canaan,k210-apb-timer + +then: + properties: + interrupts: + maxItems: 2 + +else: + properties: + interrupts: + maxItems: 1
required: - compatible @@ -60,8 +76,8 @@ oneOf: examples: - | timer@ffe00000 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 170 4>; + compatible = "canaan,k210-apb-timer", "snps,dw-apb-timer"; + interrupts = <0 170 4>, <0 170 4>; reg = <0xffe00000 0x1000>; clocks = <&timer_clk>, <&timer_pclk>; clock-names = "timer", "pclk";
From: Conor Dooley conor.dooley@microchip.com
snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect this.
Signed-off-by: Conor Dooley conor.dooley@microchip.com --- .../bindings/spi/snps,dw-apb-ssi.yaml | 48 ++++++++++++++----- 1 file changed, 35 insertions(+), 13 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml index e25d44c218f2..f2b9e3f062cd 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml @@ -135,19 +135,41 @@ properties: of the designware controller, and the upper limit is also subject to controller configuration.
-patternProperties: - "^.*@[0-9a-f]+$": - type: object - properties: - reg: - minimum: 0 - maximum: 3 - - spi-rx-bus-width: - const: 1 - - spi-tx-bus-width: - const: 1 +if: + properties: + compatible: + contains: + const: snps,dwc-ssi-1.01a + +then: + patternProperties: + "^.*@[0-9a-f]+$": + type: object + properties: + reg: + minimum: 0 + maximum: 3 + + spi-rx-bus-width: + const: 4 + + spi-tx-bus-width: + const: 4 + +else: + patternProperties: + "^.*@[0-9a-f]+$": + type: object + properties: + reg: + minimum: 0 + maximum: 3 + + spi-rx-bus-width: + const: 1 + + spi-tx-bus-width: + const: 1
unevaluatedProperties: false
Hi Conor,
On Sat, Jun 18, 2022 at 2:32 PM Conor Dooley mail@conchuod.ie wrote:
From: Conor Dooley conor.dooley@microchip.com
snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect this.
Signed-off-by: Conor Dooley conor.dooley@microchip.com
Thanks for your patch!
--- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml @@ -135,19 +135,41 @@ properties: of the designware controller, and the upper limit is also subject to controller configuration.
-patternProperties:
- "^.*@[0-9a-f]+$":
- type: object
- properties:
reg:minimum: 0maximum: 3spi-rx-bus-width:const: 1spi-tx-bus-width:const: 1+if:
- properties:
- compatible:
contains:const: snps,dwc-ssi-1.01a+then:
- patternProperties:
- "^.*@[0-9a-f]+$":
type: objectproperties:reg:minimum: 0maximum: 3spi-rx-bus-width:const: 4spi-tx-bus-width:const: 4
These two also depend on the board (SPI device + wiring). So all of [1, 2, 4] are valid values.
+else:
- patternProperties:
- "^.*@[0-9a-f]+$":
type: objectproperties:reg:minimum: 0maximum: 3spi-rx-bus-width:const: 1spi-tx-bus-width:const: 1unevaluatedProperties: false
Gr{oetje,eeting}s,
Geert
-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
On 20/06/2022 09:02, Geert Uytterhoeven wrote:
Hi Conor,
On Sat, Jun 18, 2022 at 2:32 PM Conor Dooley mail@conchuod.ie wrote:
From: Conor Dooley conor.dooley@microchip.com
snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect this.
Signed-off-by: Conor Dooley conor.dooley@microchip.com
Thanks for your patch!
--- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml @@ -135,19 +135,41 @@ properties: of the designware controller, and the upper limit is also subject to controller configuration.
-patternProperties:
- "^.*@[0-9a-f]+$":
- type: object
- properties:
reg:minimum: 0maximum: 3spi-rx-bus-width:const: 1spi-tx-bus-width:const: 1+if:
- properties:
- compatible:
contains:const: snps,dwc-ssi-1.01a+then:
- patternProperties:
- "^.*@[0-9a-f]+$":
type: objectproperties:reg:minimum: 0maximum: 3spi-rx-bus-width:const: 4spi-tx-bus-width:const: 4These two also depend on the board (SPI device + wiring). So all of [1, 2, 4] are valid values.
Yeah, I wasn't sure about this one as I was writing it. enum: [1, 2, 4] I guess. As always, thanks Geert!
Conor.
+else:
patternProperties:
"^.*@[0-9a-f]+$":
type: objectproperties:reg:minimum: 0maximum: 3spi-rx-bus-width:const: 1spi-tx-bus-width:const: 1unevaluatedProperties: false
Gr{oetje,eeting}s,
Geert-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
From: Conor Dooley conor.dooley@microchip.com
snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect this.
Signed-off-by: Conor Dooley conor.dooley@microchip.com
.../bindings/spi/snps,dw-apb-ssi.yaml | 48 ++++++++++++++----- 1 file changed, 35 insertions(+), 13 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml index e25d44c218f2..f2b9e3f062cd 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml @@ -135,19 +135,41 @@ properties: of the designware controller, and the upper limit is also subject to controller configuration.
-patternProperties:
- "^.*@[0-9a-f]+$":
- type: object
- properties:
reg:minimum: 0maximum: 3spi-rx-bus-width:const: 1spi-tx-bus-width:const: 1+if:
- properties:
- compatible:
contains:const: snps,dwc-ssi-1.01a+then:
- patternProperties:
- "^.*@[0-9a-f]+$":
type: objectproperties:reg:minimum: 0maximum: 3spi-rx-bus-width:const: 4spi-tx-bus-width:const: 4+else:
- patternProperties:
- "^.*@[0-9a-f]+$":
type: objectproperties:reg:minimum: 0maximum: 3spi-rx-bus-width:const: 1spi-tx-bus-width:const: 1
You can just use a more relaxed constraint "enum: [1 2 4 8]" here irrespective from the compatible string. The modern DW APB SSI controllers of v.4.* and newer also support the enhanced SPI Modes too (Dual, Quad and Octal). Since the IP-core version is auto-detected at run-time there is no way to create a DT-schema correctly constraining the Rx/Tx SPI bus widths. So let's keep the compatible-string-independent "patternProperties" here but just extend the set of acceptable "spi-rx-bus-width" and "spi-tx-bus-width" properties values.
Note the DW APB SSI/AHB SSI driver currently doesn't support the enhanced SPI modes. So I am not sure whether the multi-lines Rx/Tx SPI bus indeed works for Canaan K210 AHB SSI controller. AFAICS from the DW APB SSI v4.01a manual the Enhanced SPI mode needs to be properly activated by means of the corresponding CSR. So most likely the DW AHB SSI controllers need some specific setups too.
-Sergey
unevaluatedProperties: false
-- 2.36.1
On 20/06/2022 21:56, Serge Semin wrote:
EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
From: Conor Dooley conor.dooley@microchip.com
snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect this.
Signed-off-by: Conor Dooley conor.dooley@microchip.com
.../bindings/spi/snps,dw-apb-ssi.yaml | 48 ++++++++++++++----- 1 file changed, 35 insertions(+), 13 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml index e25d44c218f2..f2b9e3f062cd 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml @@ -135,19 +135,41 @@ properties: of the designware controller, and the upper limit is also subject to controller configuration.
-patternProperties:
- "^.*@[0-9a-f]+$":
- type: object
- properties:
reg:minimum: 0maximum: 3spi-rx-bus-width:const: 1spi-tx-bus-width:const: 1+if:
- properties:
- compatible:
contains:const: snps,dwc-ssi-1.01a+then:
- patternProperties:
- "^.*@[0-9a-f]+$":
type: objectproperties:reg:minimum: 0maximum: 3spi-rx-bus-width:const: 4spi-tx-bus-width:const: 4+else:
- patternProperties:
- "^.*@[0-9a-f]+$":
type: objectproperties:reg:minimum: 0maximum: 3spi-rx-bus-width:const: 1spi-tx-bus-width:const: 1You can just use a more relaxed constraint "enum: [1 2 4 8]" here
8 too? sure.
irrespective from the compatible string. The modern DW APB SSI controllers of v.4.* and newer also support the enhanced SPI Modes too (Dual, Quad and Octal). Since the IP-core version is auto-detected at run-time there is no way to create a DT-schema correctly constraining the Rx/Tx SPI bus widths. So let's keep the compatible-string-independent "patternProperties" here but just extend the set of acceptable "spi-rx-bus-width" and "spi-tx-bus-width" properties values.
SGTM!
Note the DW APB SSI/AHB SSI driver currently doesn't support the enhanced SPI modes. So I am not sure whether the multi-lines Rx/Tx SPI bus indeed works for Canaan K210 AHB SSI controller. AFAICS from the DW APB SSI v4.01a manual the Enhanced SPI mode needs to be properly activated by means of the corresponding CSR. So most likely the DW AHB SSI controllers need some specific setups too.
hmm, well I'll leave that up to people that have Canaan hardware! Thanks, Conor.
-Sergey
unevaluatedProperties: false
-- 2.36.1
On 6/21/22 06:06, Conor.Dooley@microchip.com wrote:
On 20/06/2022 21:56, Serge Semin wrote:
EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
From: Conor Dooley conor.dooley@microchip.com
snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect this.
Signed-off-by: Conor Dooley conor.dooley@microchip.com
.../bindings/spi/snps,dw-apb-ssi.yaml | 48 ++++++++++++++----- 1 file changed, 35 insertions(+), 13 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml index e25d44c218f2..f2b9e3f062cd 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml @@ -135,19 +135,41 @@ properties: of the designware controller, and the upper limit is also subject to controller configuration.
-patternProperties:
- "^.*@[0-9a-f]+$":
- type: object
- properties:
reg:minimum: 0maximum: 3spi-rx-bus-width:const: 1spi-tx-bus-width:const: 1+if:
- properties:
- compatible:
contains:const: snps,dwc-ssi-1.01a+then:
- patternProperties:
- "^.*@[0-9a-f]+$":
type: objectproperties:reg:minimum: 0maximum: 3spi-rx-bus-width:const: 4spi-tx-bus-width:const: 4+else:
- patternProperties:
- "^.*@[0-9a-f]+$":
type: objectproperties:reg:minimum: 0maximum: 3spi-rx-bus-width:const: 1spi-tx-bus-width:const: 1You can just use a more relaxed constraint "enum: [1 2 4 8]" here
8 too? sure.
irrespective from the compatible string. The modern DW APB SSI controllers of v.4.* and newer also support the enhanced SPI Modes too (Dual, Quad and Octal). Since the IP-core version is auto-detected at run-time there is no way to create a DT-schema correctly constraining the Rx/Tx SPI bus widths. So let's keep the compatible-string-independent "patternProperties" here but just extend the set of acceptable "spi-rx-bus-width" and "spi-tx-bus-width" properties values.
SGTM!
Note the DW APB SSI/AHB SSI driver currently doesn't support the enhanced SPI modes. So I am not sure whether the multi-lines Rx/Tx SPI bus indeed works for Canaan K210 AHB SSI controller. AFAICS from the DW APB SSI v4.01a manual the Enhanced SPI mode needs to be properly activated by means of the corresponding CSR. So most likely the DW AHB SSI controllers need some specific setups too.
hmm, well I'll leave that up to people that have Canaan hardware!
I will test this series.
Thanks, Conor.
-Sergey
unevaluatedProperties: false
-- 2.36.1
On 20/06/2022 23:46, Damien Le Moal wrote:
On 6/21/22 06:06, Conor.Dooley@microchip.com wrote:
On 20/06/2022 21:56, Serge Semin wrote:
EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
From: Conor Dooley conor.dooley@microchip.com
snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect this.
Signed-off-by: Conor Dooley conor.dooley@microchip.com
.../bindings/spi/snps,dw-apb-ssi.yaml | 48 ++++++++++++++----- 1 file changed, 35 insertions(+), 13 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml index e25d44c218f2..f2b9e3f062cd 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml @@ -135,19 +135,41 @@ properties: of the designware controller, and the upper limit is also subject to controller configuration.
-patternProperties:
- "^.*@[0-9a-f]+$":
- type: object
- properties:
reg:minimum: 0maximum: 3spi-rx-bus-width:const: 1spi-tx-bus-width:const: 1+if:
- properties:
- compatible:
contains:const: snps,dwc-ssi-1.01a+then:
- patternProperties:
- "^.*@[0-9a-f]+$":
type: objectproperties:reg:minimum: 0maximum: 3spi-rx-bus-width:const: 4spi-tx-bus-width:const: 4+else:
- patternProperties:
- "^.*@[0-9a-f]+$":
type: objectproperties:reg:minimum: 0maximum: 3spi-rx-bus-width:const: 1spi-tx-bus-width:const: 1You can just use a more relaxed constraint "enum: [1 2 4 8]" here
8 too? sure.
irrespective from the compatible string. The modern DW APB SSI controllers of v.4.* and newer also support the enhanced SPI Modes too (Dual, Quad and Octal). Since the IP-core version is auto-detected at run-time there is no way to create a DT-schema correctly constraining the Rx/Tx SPI bus widths. So let's keep the compatible-string-independent "patternProperties" here but just extend the set of acceptable "spi-rx-bus-width" and "spi-tx-bus-width" properties values.
SGTM!
Note the DW APB SSI/AHB SSI driver currently doesn't support the enhanced SPI modes. So I am not sure whether the multi-lines Rx/Tx SPI bus indeed works for Canaan K210 AHB SSI controller. AFAICS from the DW APB SSI v4.01a manual the Enhanced SPI mode needs to be properly activated by means of the corresponding CSR. So most likely the DW AHB SSI controllers need some specific setups too.
hmm, well I'll leave that up to people that have Canaan hardware!
I will test this series.
Cool, thanks. I'll try to get a respin out tomorrow w/ the memory node "unfixed". Conor.
Thanks, Conor.
-Sergey
unevaluatedProperties: false
-- 2.36.1
On 6/21/22 07:49, Conor Dooley wrote:
On 20/06/2022 23:46, Damien Le Moal wrote:
On 6/21/22 06:06, Conor.Dooley@microchip.com wrote:
On 20/06/2022 21:56, Serge Semin wrote:
EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
From: Conor Dooley conor.dooley@microchip.com
snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect this.
Signed-off-by: Conor Dooley conor.dooley@microchip.com
.../bindings/spi/snps,dw-apb-ssi.yaml | 48 ++++++++++++++----- 1 file changed, 35 insertions(+), 13 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml index e25d44c218f2..f2b9e3f062cd 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml @@ -135,19 +135,41 @@ properties: of the designware controller, and the upper limit is also subject to controller configuration.
-patternProperties:
- "^.*@[0-9a-f]+$":
- type: object
- properties:
reg:minimum: 0maximum: 3spi-rx-bus-width:const: 1spi-tx-bus-width:const: 1+if:
- properties:
- compatible:
contains:const: snps,dwc-ssi-1.01a+then:
- patternProperties:
- "^.*@[0-9a-f]+$":
type: objectproperties:reg:minimum: 0maximum: 3spi-rx-bus-width:const: 4spi-tx-bus-width:const: 4+else:
- patternProperties:
- "^.*@[0-9a-f]+$":
type: objectproperties:reg:minimum: 0maximum: 3spi-rx-bus-width:const: 1spi-tx-bus-width:const: 1You can just use a more relaxed constraint "enum: [1 2 4 8]" here
8 too? sure.
irrespective from the compatible string. The modern DW APB SSI controllers of v.4.* and newer also support the enhanced SPI Modes too (Dual, Quad and Octal). Since the IP-core version is auto-detected at run-time there is no way to create a DT-schema correctly constraining the Rx/Tx SPI bus widths. So let's keep the compatible-string-independent "patternProperties" here but just extend the set of acceptable "spi-rx-bus-width" and "spi-tx-bus-width" properties values.
SGTM!
Note the DW APB SSI/AHB SSI driver currently doesn't support the enhanced SPI modes. So I am not sure whether the multi-lines Rx/Tx SPI bus indeed works for Canaan K210 AHB SSI controller. AFAICS from the DW APB SSI v4.01a manual the Enhanced SPI mode needs to be properly activated by means of the corresponding CSR. So most likely the DW AHB SSI controllers need some specific setups too.
hmm, well I'll leave that up to people that have Canaan hardware!
I will test this series.
Cool, thanks. I'll try to get a respin out tomorrow w/ the memory node "unfixed".
OK. I will test that then :)
Conor.
Thanks, Conor.
-Sergey
unevaluatedProperties: false
-- 2.36.1
On 21/06/2022 00:17, Damien Le Moal wrote:
EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
On 6/21/22 07:49, Conor Dooley wrote:
---8<---
hmm, well I'll leave that up to people that have Canaan hardware!
I will test this series.
Cool, thanks. I'll try to get a respin out tomorrow w/ the memory node "unfixed".
OK. I will test that then :)
Since the memory node hit that dt-schema snag, I have not sent a v2. Going to be AFK for a few days, so I dropped the memory node change, changed the spi binding & put the series on: git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ canaan
If you get a chance to look at it great, if not I'll send a v2 once the memory node is figured out.
Thanks, Conor.
On Tue, Jun 21, 2022 at 04:06:21PM +0000, Conor.Dooley@microchip.com wrote:
On 21/06/2022 00:17, Damien Le Moal wrote:
EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
On 6/21/22 07:49, Conor Dooley wrote:
---8<---
hmm, well I'll leave that up to people that have Canaan hardware!
I will test this series.
Cool, thanks. I'll try to get a respin out tomorrow w/ the memory node "unfixed".
OK. I will test that then :)
Since the memory node hit that dt-schema snag, I have not sent a v2. Going to be AFK for a few days, so I dropped the memory node change, changed the spi binding & put the series on: git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ canaan
If you get a chance to look at it great, if not I'll send a v2 once the memory node is figured out.
commit 84df6ca0f277 ("spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width") looks good to me. Feel free to add my ack tag to v2 of that patch.
-Sergey
Thanks, Conor.
On 23/06/2022 11:25, Serge Semin wrote:
On Tue, Jun 21, 2022 at 04:06:21PM +0000, Conor.Dooley@microchip.com wrote:
On 21/06/2022 00:17, Damien Le Moal wrote:
EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
On 6/21/22 07:49, Conor Dooley wrote:
---8<---
hmm, well I'll leave that up to people that have Canaan hardware!
I will test this series.
Cool, thanks. I'll try to get a respin out tomorrow w/ the memory node "unfixed".
OK. I will test that then :)
Since the memory node hit that dt-schema snag, I have not sent a v2. Going to be AFK for a few days, so I dropped the memory node change, changed the spi binding & put the series on: git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ canaan
If you get a chance to look at it great, if not I'll send a v2 once the memory node is figured out.
commit 84df6ca0f277 ("spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width") looks good to me. Feel free to add my ack tag to v2 of that patch.
Sure, thanks!
Hi Serge,
On Mon, Jun 20, 2022 at 10:56 PM Serge Semin fancer.lancer@gmail.com wrote:
On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
From: Conor Dooley conor.dooley@microchip.com
snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect this.
Signed-off-by: Conor Dooley conor.dooley@microchip.com
.../bindings/spi/snps,dw-apb-ssi.yaml | 48 ++++++++++++++----- 1 file changed, 35 insertions(+), 13 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml index e25d44c218f2..f2b9e3f062cd 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml @@ -135,19 +135,41 @@ properties: of the designware controller, and the upper limit is also subject to controller configuration.
-patternProperties:
- "^.*@[0-9a-f]+$":
- type: object
- properties:
reg:minimum: 0maximum: 3spi-rx-bus-width:const: 1spi-tx-bus-width:const: 1+if:
- properties:
- compatible:
contains:const: snps,dwc-ssi-1.01a+then:
- patternProperties:
- "^.*@[0-9a-f]+$":
type: objectproperties:reg:minimum: 0maximum: 3spi-rx-bus-width:const: 4spi-tx-bus-width:const: 4+else:
- patternProperties:
- "^.*@[0-9a-f]+$":
type: objectproperties:reg:minimum: 0maximum: 3spi-rx-bus-width:const: 1spi-tx-bus-width:const: 1You can just use a more relaxed constraint "enum: [1 2 4 8]" here irrespective from the compatible string. The modern DW APB SSI controllers of v.4.* and newer also support the enhanced SPI Modes too (Dual, Quad and Octal). Since the IP-core version is auto-detected at run-time there is no way to create a DT-schema correctly constraining the Rx/Tx SPI bus widths. So let's keep the compatible-string-independent "patternProperties" here but just extend the set of acceptable "spi-rx-bus-width" and "spi-tx-bus-width" properties values.
Note the DW APB SSI/AHB SSI driver currently doesn't support the enhanced SPI modes. So I am not sure whether the multi-lines Rx/Tx SPI bus indeed works for Canaan K210 AHB SSI controller. AFAICS from the DW APB SSI v4.01a manual the Enhanced SPI mode needs to be properly activated by means of the corresponding CSR. So most likely the DW AHB SSI controllers need some specific setups too.
That doesn't matter here, as DT describes hardware, not software limitations.
Gr{oetje,eeting}s,
Geert
-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert
On Tue, Jun 21, 2022 at 09:03:25AM +0200, Geert Uytterhoeven wrote:
Hi Serge,
On Mon, Jun 20, 2022 at 10:56 PM Serge Semin fancer.lancer@gmail.com wrote:
On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
From: Conor Dooley conor.dooley@microchip.com
[...]
spi-rx-bus-width:const: 1spi-tx-bus-width:const: 1You can just use a more relaxed constraint "enum: [1 2 4 8]" here irrespective from the compatible string. The modern DW APB SSI controllers of v.4.* and newer also support the enhanced SPI Modes too (Dual, Quad and Octal). Since the IP-core version is auto-detected at run-time there is no way to create a DT-schema correctly constraining the Rx/Tx SPI bus widths. So let's keep the compatible-string-independent "patternProperties" here but just extend the set of acceptable "spi-rx-bus-width" and "spi-tx-bus-width" properties values.
Note the DW APB SSI/AHB SSI driver currently doesn't support the enhanced SPI modes. So I am not sure whether the multi-lines Rx/Tx SPI bus indeed works for Canaan K210 AHB SSI controller. AFAICS from the DW APB SSI v4.01a manual the Enhanced SPI mode needs to be properly activated by means of the corresponding CSR. So most likely the DW AHB SSI controllers need some specific setups too.
That doesn't matter here, as DT describes hardware, not software limitations.
Can't argue with that.) My note regarding the current DW APB SSI driver was mainly addressed for the Canaan K210 users, since should the SoC-based board really have the Quad Tx/Rx SPI bus most likely the interface won't work with the full bandwidth. So it is a good reason to perform the platform research and if possible alter the driver accordingly.
-Sergey
Gr{oetje,eeting}s,
Geert-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
From: Conor Dooley conor.dooley@microchip.com
The k210 memory node has a compatible string that does not match with any driver or dt-binding & has several non standard properties. Replace the reg names with a comment and delete the rest.
Signed-off-by: Conor Dooley conor.dooley@microchip.com --- --- arch/riscv/boot/dts/canaan/k210.dtsi | 6 ------ 1 file changed, 6 deletions(-)
diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi index 44d338514761..287ea6eebe47 100644 --- a/arch/riscv/boot/dts/canaan/k210.dtsi +++ b/arch/riscv/boot/dts/canaan/k210.dtsi @@ -69,15 +69,9 @@ cpu1_intc: interrupt-controller {
sram: memory@80000000 { device_type = "memory"; - compatible = "canaan,k210-sram"; reg = <0x80000000 0x400000>, <0x80400000 0x200000>, <0x80600000 0x200000>; - reg-names = "sram0", "sram1", "aisram"; - clocks = <&sysclk K210_CLK_SRAM0>, - <&sysclk K210_CLK_SRAM1>, - <&sysclk K210_CLK_AI>; - clock-names = "sram0", "sram1", "aisram"; };
clocks {
On 18/06/2022 13:30, Conor Dooley wrote:
From: Conor Dooley conor.dooley@microchip.com
The k210 memory node has a compatible string that does not match with any driver or dt-binding & has several non standard properties. Replace the reg names with a comment and delete the rest.
Gah, should've fixed that during rebase. I'm sure there'll need to be (at least) a v2 & I'll wait rather than resend. Thanks, Conor.
Signed-off-by: Conor Dooley conor.dooley@microchip.com
arch/riscv/boot/dts/canaan/k210.dtsi | 6 ------ 1 file changed, 6 deletions(-)
diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi index 44d338514761..287ea6eebe47 100644 --- a/arch/riscv/boot/dts/canaan/k210.dtsi +++ b/arch/riscv/boot/dts/canaan/k210.dtsi @@ -69,15 +69,9 @@ cpu1_intc: interrupt-controller {
sram: memory@80000000 { device_type = "memory";
compatible = "canaan,k210-sram";reg = <0x80000000 0x400000>, <0x80400000 0x200000>, <0x80600000 0x200000>;
reg-names = "sram0", "sram1", "aisram";clocks = <&sysclk K210_CLK_SRAM0>,<&sysclk K210_CLK_SRAM1>,<&sysclk K210_CLK_AI>;clock-names = "sram0", "sram1", "aisram";};
clocks {
On 6/18/22 21:30, Conor Dooley wrote:
From: Conor Dooley conor.dooley@microchip.com
The k210 memory node has a compatible string that does not match with any driver or dt-binding & has several non standard properties. Replace the reg names with a comment and delete the rest.
Signed-off-by: Conor Dooley conor.dooley@microchip.com
arch/riscv/boot/dts/canaan/k210.dtsi | 6 ------ 1 file changed, 6 deletions(-)
diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi index 44d338514761..287ea6eebe47 100644 --- a/arch/riscv/boot/dts/canaan/k210.dtsi +++ b/arch/riscv/boot/dts/canaan/k210.dtsi @@ -69,15 +69,9 @@ cpu1_intc: interrupt-controller {
sram: memory@80000000 { device_type = "memory";
compatible = "canaan,k210-sram";reg-names = "sram0", "sram1", "aisram";clocks = <&sysclk K210_CLK_SRAM0>,<&sysclk K210_CLK_SRAM1>,<&sysclk K210_CLK_AI>;clock-names = "sram0", "sram1", "aisram";
These are used by u-boot to setup the memory clocks and initialize the aisram. Sure the kernel actually does not use this, but to be in sync with u-boot DT, I would prefer keeping this as is. Right now, u-boot *and* the kernel work fine with both u-boot internal DT and the kernel DT.
On 20/06/2022 00:38, Damien Le Moal wrote:
EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
On 6/18/22 21:30, Conor Dooley wrote:
From: Conor Dooley conor.dooley@microchip.com
The k210 memory node has a compatible string that does not match with any driver or dt-binding & has several non standard properties. Replace the reg names with a comment and delete the rest.
Signed-off-by: Conor Dooley conor.dooley@microchip.com
arch/riscv/boot/dts/canaan/k210.dtsi | 6 ------ 1 file changed, 6 deletions(-)
diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi index 44d338514761..287ea6eebe47 100644 --- a/arch/riscv/boot/dts/canaan/k210.dtsi +++ b/arch/riscv/boot/dts/canaan/k210.dtsi @@ -69,15 +69,9 @@ cpu1_intc: interrupt-controller {
sram: memory@80000000 { device_type = "memory";
compatible = "canaan,k210-sram"; reg = <0x80000000 0x400000>, <0x80400000 0x200000>, <0x80600000 0x200000>;reg-names = "sram0", "sram1", "aisram";clocks = <&sysclk K210_CLK_SRAM0>,<&sysclk K210_CLK_SRAM1>,<&sysclk K210_CLK_AI>;clock-names = "sram0", "sram1", "aisram"; };These are used by u-boot to setup the memory clocks and initialize the aisram. Sure the kernel actually does not use this, but to be in sync with u-boot DT, I would prefer keeping this as is. Right now, u-boot *and* the kernel work fine with both u-boot internal DT and the kernel DT.
Right, but unfortunately that desire alone doesn't do anything about the dtbs_check complaints.
I guess the alternative approach of actually documenting the compatible would be more palatable?
Thanks, Conor.
On 6/20/22 08:54, Conor.Dooley@microchip.com wrote:
On 20/06/2022 00:38, Damien Le Moal wrote:
EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
On 6/18/22 21:30, Conor Dooley wrote:
From: Conor Dooley conor.dooley@microchip.com
The k210 memory node has a compatible string that does not match with any driver or dt-binding & has several non standard properties. Replace the reg names with a comment and delete the rest.
Signed-off-by: Conor Dooley conor.dooley@microchip.com
arch/riscv/boot/dts/canaan/k210.dtsi | 6 ------ 1 file changed, 6 deletions(-)
diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi index 44d338514761..287ea6eebe47 100644 --- a/arch/riscv/boot/dts/canaan/k210.dtsi +++ b/arch/riscv/boot/dts/canaan/k210.dtsi @@ -69,15 +69,9 @@ cpu1_intc: interrupt-controller {
sram: memory@80000000 { device_type = "memory";
compatible = "canaan,k210-sram"; reg = <0x80000000 0x400000>, <0x80400000 0x200000>, <0x80600000 0x200000>;reg-names = "sram0", "sram1", "aisram";clocks = <&sysclk K210_CLK_SRAM0>,<&sysclk K210_CLK_SRAM1>,<&sysclk K210_CLK_AI>;clock-names = "sram0", "sram1", "aisram"; };These are used by u-boot to setup the memory clocks and initialize the aisram. Sure the kernel actually does not use this, but to be in sync with u-boot DT, I would prefer keeping this as is. Right now, u-boot *and* the kernel work fine with both u-boot internal DT and the kernel DT.
Right, but unfortunately that desire alone doesn't do anything about the dtbs_check complaints.
I guess the alternative approach of actually documenting the compatible would be more palatable?
Yes, I think so. That would allow keeping the fields without the DTB build warnings.
Thanks, Conor.
On 20/06/2022 01:25, Damien Le Moal wrote:
EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
On 6/20/22 08:54, Conor.Dooley@microchip.com wrote:
On 20/06/2022 00:38, Damien Le Moal wrote:
EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
On 6/18/22 21:30, Conor Dooley wrote:
From: Conor Dooley conor.dooley@microchip.com
The k210 memory node has a compatible string that does not match with any driver or dt-binding & has several non standard properties. Replace the reg names with a comment and delete the rest.
Signed-off-by: Conor Dooley conor.dooley@microchip.com
arch/riscv/boot/dts/canaan/k210.dtsi | 6 ------ 1 file changed, 6 deletions(-)
diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi index 44d338514761..287ea6eebe47 100644 --- a/arch/riscv/boot/dts/canaan/k210.dtsi +++ b/arch/riscv/boot/dts/canaan/k210.dtsi @@ -69,15 +69,9 @@ cpu1_intc: interrupt-controller {
sram: memory@80000000 { device_type = "memory";
compatible = "canaan,k210-sram"; reg = <0x80000000 0x400000>, <0x80400000 0x200000>, <0x80600000 0x200000>;reg-names = "sram0", "sram1", "aisram";clocks = <&sysclk K210_CLK_SRAM0>,<&sysclk K210_CLK_SRAM1>,<&sysclk K210_CLK_AI>;clock-names = "sram0", "sram1", "aisram"; };These are used by u-boot to setup the memory clocks and initialize the aisram. Sure the kernel actually does not use this, but to be in sync with u-boot DT, I would prefer keeping this as is. Right now, u-boot *and* the kernel work fine with both u-boot internal DT and the kernel DT.
Right, but unfortunately that desire alone doesn't do anything about the dtbs_check complaints.
I guess the alternative approach of actually documenting the compatible would be more palatable?
Yes, I think so. That would allow keeping the fields without the DTB build warnings.
Hmm looks like that approach contradicts the dt-schema; https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/memor...
@Rob,Krzysztof what is one meant to do here?
Thanks, Conor.
From: Conor Dooley conor.dooley@microchip.com
The DMAC on the k210 has a non standard interrupt configuration, which leads to dtbs_check warnings:
k210_generic.dtb: dma-controller@50000000: interrupts: [[27], [28], [29], [30], [31], [32]] is too long
From schema: linux/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
Update the binding to use a custom compatible to avoid the warning.
Signed-off-by: Conor Dooley conor.dooley@microchip.com --- arch/riscv/boot/dts/canaan/k210.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi index 287ea6eebe47..314f6da5d7f6 100644 --- a/arch/riscv/boot/dts/canaan/k210.dtsi +++ b/arch/riscv/boot/dts/canaan/k210.dtsi @@ -135,7 +135,7 @@ gpio0: gpio-controller@38001000 { };
dmac0: dma-controller@50000000 { - compatible = "snps,axi-dma-1.01a"; + compatible = "canaan,k210-axi-dma", "snps,axi-dma-1.01a"; reg = <0x50000000 0x1000>; interrupts = <27>, <28>, <29>, <30>, <31>, <32>; #dma-cells = <1>;
From: Conor Dooley conor.dooley@microchip.com
The timers on the k210 have non standard interrupt configurations, which leads to dtbs_check warnings:
k210_generic.dtb: timer@502d0000: interrupts: [[14], [15]] is too long
From schema: Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
Change to using the newly added canaan k210 specific binding to avoid the warning.
Signed-off-by: Conor Dooley conor.dooley@microchip.com --- arch/riscv/boot/dts/canaan/k210.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi index 314f6da5d7f6..ef46ddf3c00c 100644 --- a/arch/riscv/boot/dts/canaan/k210.dtsi +++ b/arch/riscv/boot/dts/canaan/k210.dtsi @@ -310,7 +310,7 @@ fpioa: pinmux@502b0000 { };
timer0: timer@502d0000 { - compatible = "snps,dw-apb-timer"; + compatible = "canaan,k210-apb-timer", "snps,dw-apb-timer"; reg = <0x502D0000 0x100>; interrupts = <14>, <15>; clocks = <&sysclk K210_CLK_TIMER0>, @@ -320,7 +320,7 @@ timer0: timer@502d0000 { };
timer1: timer@502e0000 { - compatible = "snps,dw-apb-timer"; + compatible = "canaan,k210-apb-timer", "snps,dw-apb-timer"; reg = <0x502E0000 0x100>; interrupts = <16>, <17>; clocks = <&sysclk K210_CLK_TIMER1>, @@ -330,7 +330,7 @@ timer1: timer@502e0000 { };
timer2: timer@502f0000 { - compatible = "snps,dw-apb-timer"; + compatible = "canaan,k210-apb-timer", "snps,dw-apb-timer"; reg = <0x502F0000 0x100>; interrupts = <18>, <19>; clocks = <&sysclk K210_CLK_TIMER2>,
From: Conor Dooley conor.dooley@microchip.com
The newly-converted-to-dt-schema binding expects the mmc node name to be '^mmc(@.*)?$' so align the devicetree with the schema.
Signed-off-by: Conor Dooley conor.dooley@microchip.com --- arch/riscv/boot/dts/canaan/canaan_kd233.dts | 2 +- arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts | 2 +- arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts | 2 +- arch/riscv/boot/dts/canaan/sipeed_maix_go.dts | 2 +- arch/riscv/boot/dts/canaan/sipeed_maixduino.dts | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/riscv/boot/dts/canaan/canaan_kd233.dts b/arch/riscv/boot/dts/canaan/canaan_kd233.dts index 039b92abf046..40992d495aa8 100644 --- a/arch/riscv/boot/dts/canaan/canaan_kd233.dts +++ b/arch/riscv/boot/dts/canaan/canaan_kd233.dts @@ -142,7 +142,7 @@ &spi1 { cs-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; status = "okay";
- slot@0 { + mmc@0 { compatible = "mmc-spi-slot"; reg = <0>; voltage-ranges = <3300 3300>; diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts index b9e30df127fe..5e809d0e11fb 100644 --- a/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts +++ b/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts @@ -189,7 +189,7 @@ &spi1 { cs-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; status = "okay";
- slot@0 { + mmc@0 { compatible = "mmc-spi-slot"; reg = <0>; voltage-ranges = <3300 3300>; diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts index 8d23401b0bbb..4be5ffac6b4a 100644 --- a/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts +++ b/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts @@ -191,7 +191,7 @@ &spi1 { cs-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; status = "okay";
- slot@0 { + mmc@0 { compatible = "mmc-spi-slot"; reg = <0>; voltage-ranges = <3300 3300>; diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts index 24fd83b43d9d..5c63f79b18ec 100644 --- a/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts +++ b/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts @@ -199,7 +199,7 @@ &spi1 { cs-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; status = "okay";
- slot@0 { + mmc@0 { compatible = "mmc-spi-slot"; reg = <0>; voltage-ranges = <3300 3300>; diff --git a/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts b/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts index 25341f38292a..59f7eaf74655 100644 --- a/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts +++ b/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts @@ -164,7 +164,7 @@ &spi1 { cs-gpios = <&gpio1_0 2 GPIO_ACTIVE_LOW>; status = "okay";
- slot@0 { + mmc@0 { compatible = "mmc-spi-slot"; reg = <0>; voltage-ranges = <3300 3300>;
From: Conor Dooley conor.dooley@microchip.com
The binding for the ili9341 specifies a const spi-max-frequency of 10 MHz but the kd233 devicetree entry has it listed at 15 Mhz. Align the devicetree with the value in the binding.
Signed-off-by: Conor Dooley conor.dooley@microchip.com --- arch/riscv/boot/dts/canaan/canaan_kd233.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/boot/dts/canaan/canaan_kd233.dts b/arch/riscv/boot/dts/canaan/canaan_kd233.dts index 40992d495aa8..4a540158f287 100644 --- a/arch/riscv/boot/dts/canaan/canaan_kd233.dts +++ b/arch/riscv/boot/dts/canaan/canaan_kd233.dts @@ -130,7 +130,7 @@ panel@0 { compatible = "ilitek,ili9341"; reg = <0>; dc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; - spi-max-frequency = <15000000>; + spi-max-frequency = <10000000>; status = "disabled"; }; };
From: Conor Dooley conor.dooley@microchip.com
The devicetrees using the Canaan k210 all have a sound-dai-cells value of 1, whereas the standard binding example for the DesignWare i2s and other use cases suggest 0. Use a k210 specific compatible which supports this difference.
Signed-off-by: Conor Dooley conor.dooley@microchip.com --- arch/riscv/boot/dts/canaan/k210.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi index ef46ddf3c00c..5eb6b69c1170 100644 --- a/arch/riscv/boot/dts/canaan/k210.dtsi +++ b/arch/riscv/boot/dts/canaan/k210.dtsi @@ -243,7 +243,7 @@ spi2: spi@50240000 { };
i2s0: i2s@50250000 { - compatible = "snps,designware-i2s"; + compatible = "canaan,k210-i2s", "snps,designware-i2s"; reg = <0x50250000 0x200>; interrupts = <5>; clocks = <&sysclk K210_CLK_I2S0>; @@ -252,7 +252,7 @@ i2s0: i2s@50250000 { };
i2s1: i2s@50260000 { - compatible = "snps,designware-i2s"; + compatible = "canaan,k210-i2s", "snps,designware-i2s"; reg = <0x50260000 0x200>; interrupts = <6>; clocks = <&sysclk K210_CLK_I2S1>; @@ -261,7 +261,7 @@ i2s1: i2s@50260000 { };
i2s2: i2s@50270000 { - compatible = "snps,designware-i2s"; + compatible = "canaan,k210-i2s", "snps,designware-i2s"; reg = <0x50270000 0x200>; interrupts = <7>; clocks = <&sysclk K210_CLK_I2S2>;
From: Conor Dooley conor.dooley@microchip.com
spi-max-frequency is a device, not a controller property and should be removed.
Link: https://lore.kernel.org/lkml/20220526014141.2872567-1-robh@kernel.org/ Signed-off-by: Conor Dooley conor.dooley@microchip.com --- arch/riscv/boot/dts/canaan/k210.dtsi | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi index 5eb6b69c1170..ec290db4705c 100644 --- a/arch/riscv/boot/dts/canaan/k210.dtsi +++ b/arch/riscv/boot/dts/canaan/k210.dtsi @@ -413,7 +413,6 @@ spi0: spi@52000000 { clock-names = "ssi_clk", "pclk"; resets = <&sysrst K210_RST_SPI0>; reset-names = "spi"; - spi-max-frequency = <25000000>; num-cs = <4>; reg-io-width = <4>; }; @@ -429,7 +428,6 @@ spi1: spi@53000000 { clock-names = "ssi_clk", "pclk"; resets = <&sysrst K210_RST_SPI1>; reset-names = "spi"; - spi-max-frequency = <25000000>; num-cs = <4>; reg-io-width = <4>; }; @@ -445,8 +443,7 @@ spi3: spi@54000000 { clock-names = "ssi_clk", "pclk"; resets = <&sysrst K210_RST_SPI3>; reset-names = "spi"; - /* Could possibly go up to 200 MHz */ - spi-max-frequency = <100000000>; + num-cs = <4>; reg-io-width = <4>; };
From: Conor Dooley conor.dooley@microchip.com
Testing & checking the Canaan devicetrees is inconvenient as only the devicetree corresponding to SOC_CANAAN_K210_DTB_BUILTIN will be built. Change the Makefile so that all devicetrees are built by default if SOC_CANAAN but only the one specified by SOC_CANAAN_K210_DTB_BUILTIN gets built as an object.
Signed-off-by: Conor Dooley conor.dooley@microchip.com --- I don't have any Canaan hardware, but I build tested it and the log looked correct with arch/riscv/boot/dts/canaan/k210_generic.dtb.o getting successfully built. --- arch/riscv/boot/dts/canaan/Makefile | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/boot/dts/canaan/Makefile b/arch/riscv/boot/dts/canaan/Makefile index c61b08ac8554..befe4eb7527b 100644 --- a/arch/riscv/boot/dts/canaan/Makefile +++ b/arch/riscv/boot/dts/canaan/Makefile @@ -1,3 +1,9 @@ # SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += $(addsuffix .dtb, $(CONFIG_SOC_CANAAN_K210_DTB_SOURCE)) -obj-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += $(addsuffix .o, $(dtb-y)) +dtb-$(CONFIG_SOC_CANAAN) += canaan_kd233.dtb +dtb-$(CONFIG_SOC_CANAAN) += k210_generic.dtb +dtb-$(CONFIG_SOC_CANAAN) += sipeed_maix_bit.dtb +dtb-$(CONFIG_SOC_CANAAN) += sipeed_maix_dock.dtb +dtb-$(CONFIG_SOC_CANAAN) += sipeed_maix_go.dtb +dtb-$(CONFIG_SOC_CANAAN) += sipeed_maixduino.dtb + +obj-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += $(addsuffix .dtb.o, $(CONFIG_SOC_CANAAN_K210_DTB_SOURCE))
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