Change-Id: I6c891515d93a6f1a597e762090c3530a6810c6c6 --- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 43 +++++++++++++++++++++++++----- drivers/gpu/drm/msm/adreno/adreno_device.c | 8 ++++++ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 ++- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 ++++ 4 files changed, 52 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c index ef20cb5..9a1ffec 100644 --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c @@ -111,11 +111,17 @@ static void a4xx_enable_hwcg(struct msm_gpu *gpu) gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00000222); gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_HLSQ , 0x00000000); gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000); - gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ, 0x00020000); - gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0xAAAAAAAA); + gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ, 0x00220000); + /* Early A430's have a timing issue with SP/TP power collapse; + disabling HW clock gating prevents it. */ + if (adreno_is_a430(adreno_gpu) && adreno_gpu->rev.patchid < 2) + gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0); + else + gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0xAAAAAAAA); gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2, 0); }
+ static void a4xx_me_init(struct msm_gpu *gpu) { struct msm_ringbuffer *ring = gpu->rb; @@ -150,7 +156,7 @@ static int a4xx_hw_init(struct msm_gpu *gpu) uint32_t *ptr, len; int i, ret;
- if (adreno_is_a4xx(adreno_gpu)) { + if (adreno_is_a420(adreno_gpu)) { gpu_write(gpu, REG_A4XX_VBIF_ABIT_SORT, 0x0001001F); gpu_write(gpu, REG_A4XX_VBIF_ABIT_SORT_CONF, 0x000000A4); gpu_write(gpu, REG_A4XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000001); @@ -159,6 +165,13 @@ static int a4xx_hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF0, 0x18181818); gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF1, 0x00000018); gpu_write(gpu, REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003); + } else if (adreno_is_a430(adreno_gpu)) { + gpu_write(gpu, REG_A4XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000001); + gpu_write(gpu, REG_A4XX_VBIF_IN_RD_LIM_CONF0, 0x18181818); + gpu_write(gpu, REG_A4XX_VBIF_IN_RD_LIM_CONF1, 0x00000018); + gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF0, 0x18181818); + gpu_write(gpu, REG_A4XX_VBIF_IN_WR_LIM_CONF1, 0x00000018); + gpu_write(gpu, REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003); } else { BUG(); } @@ -170,6 +183,10 @@ static int a4xx_hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A4XX_RBBM_SP_HYST_CNT, 0x10); gpu_write(gpu, REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL, 0x10);
+ if (adreno_is_a430(adreno_gpu)) { + gpu_write(gpu, REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2, 0x30); + } + /* Enable the RBBM error reporting bits */ gpu_write(gpu, REG_A4XX_RBBM_AHB_CTL0, 0x00000001);
@@ -192,6 +209,9 @@ static int a4xx_hw_init(struct msm_gpu *gpu) /* Turn on performance counters: */ gpu_write(gpu, REG_A4XX_RBBM_PERFCTR_CTL, 0x01);
+ if (adreno_is_a430(adreno_gpu)) + gpu_write(gpu, REG_A4XX_UCHE_CACHE_WAYS_VFD, 0x07); + /* Disable L2 bypass to avoid UCHE out of bounds errors */ gpu_write(gpu, REG_A4XX_UCHE_TRAP_BASE_LO, 0xffff0000); gpu_write(gpu, REG_A4XX_UCHE_TRAP_BASE_HI, 0xffff0000); @@ -199,6 +219,15 @@ static int a4xx_hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A4XX_CP_DEBUG, (1 << 25) | (adreno_is_a420(adreno_gpu) ? (1 << 29) : 0));
+ /* On A430 enable SP regfile sleep for power savings */ + /* TODO downstream does this for !420, so maybe applies for 405 too? */ + if (!adreno_is_a420(adreno_gpu)) { + gpu_write(gpu, REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0, + 0x00000441); + gpu_write(gpu, REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1, + 0x00000441); + } + a4xx_enable_hwcg(gpu);
/* @@ -213,9 +242,11 @@ static int a4xx_hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ, val); }
- ret = adreno_hw_init(gpu); - if (ret) - return ret; + if (!adreno_is_a430(adreno_gpu)) { + ret = adreno_hw_init(gpu); + if (ret) + return ret; + }
/* setup access protection: */ gpu_write(gpu, REG_A4XX_CP_PROTECT_CTRL, 0x00000007); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 1ea2df5..43d5aaa 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -73,6 +73,14 @@ static const struct adreno_info gpulist[] = { .pfpfw = "a420_pfp.fw", .gmem = (SZ_1M + SZ_512K), .init = a4xx_gpu_init, + }, { + .rev = ADRENO_REV(4, 3, 0, ANY_ID), + .revn = 430, + .name = "A430", + .pm4fw = "a420_pm4.fw", + .pfpfw = "a420_pfp.fw", + .gmem = (SZ_1M + SZ_512K), + .init = a4xx_gpu_init, }, };
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index a3b54cc..0e76a21 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -137,7 +137,8 @@ int adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, if (priv->lastctx == ctx) break; case MSM_SUBMIT_CMD_BUF: - OUT_PKT3(ring, CP_INDIRECT_BUFFER_PFD, 2); + OUT_PKT3(ring, adreno_is_a430(adreno_gpu) ? + CP_INDIRECT_BUFFER_PFE : CP_INDIRECT_BUFFER_PFD, 2); OUT_RING(ring, submit->cmd[i].iova); OUT_RING(ring, submit->cmd[i].size); ibs++; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 0a312e9..c26aea1 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -228,6 +228,11 @@ static inline int adreno_is_a420(struct adreno_gpu *gpu) return gpu->revn == 420; }
+static inline int adreno_is_a430(struct adreno_gpu *gpu) +{ + return gpu->revn == 430; +} + int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value); int adreno_hw_init(struct msm_gpu *gpu); uint32_t adreno_last_fence(struct msm_gpu *gpu);
Change-Id: Ife53627e9985e1204cc319da0221338e5272eb81 --- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 39 +++++++++++++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c index 9a1ffec..9aab904 100644 --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c @@ -552,12 +552,47 @@ static void a4xx_dump(struct msm_gpu *gpu) adreno_dump(gpu); }
+static int a4xx_pm_resume(struct msm_gpu *gpu) { + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + int ret; + + ret = msm_gpu_pm_resume(gpu); + if (ret) + return ret; + + if (adreno_is_a430(adreno_gpu)) { + unsigned int reg; + /* Set the default register values; set SW_COLLAPSE to 0 */ + gpu_write(gpu, REG_A4XX_RBBM_POWER_CNTL_IP, 0x778000); + do { + udelay(5); + reg = gpu_read(gpu, REG_A4XX_RBBM_POWER_STATUS); + } while (!(reg & SP_TP_PWR_ON)); + } + return 0; +} + +static int a4xx_pm_suspend(struct msm_gpu *gpu) { + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + int ret; + + ret = msm_gpu_pm_suspend(gpu); + if (ret) + return ret; + + if (adreno_is_a430(adreno_gpu)) { + /* Set the default register values; set SW_COLLAPSE to 1 */ + gpu_write(gpu, REG_A4XX_RBBM_POWER_CNTL_IP, 0x778001); + } + return 0; +} + static const struct adreno_gpu_funcs funcs = { .base = { .get_param = adreno_get_param, .hw_init = a4xx_hw_init, - .pm_suspend = msm_gpu_pm_suspend, - .pm_resume = msm_gpu_pm_resume, + .pm_suspend = a4xx_pm_suspend, + .pm_resume = a4xx_pm_resume, .recover = a4xx_recover, .last_fence = adreno_last_fence, .submit = adreno_submit,
On 19 February 2016 at 00:50, C Stout cstout@chromium.org wrote:
Change-Id: Ife53627e9985e1204cc319da0221338e5272eb81
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 39 +++++++++++++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c index 9a1ffec..9aab904 100644 --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c @@ -552,12 +552,47 @@ static void a4xx_dump(struct msm_gpu *gpu) adreno_dump(gpu); }
+static int a4xx_pm_resume(struct msm_gpu *gpu) {
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);int ret;ret = msm_gpu_pm_resume(gpu);if (ret)return ret;if (adreno_is_a430(adreno_gpu)) {unsigned int reg;/* Set the default register values; set SW_COLLAPSE to 0 */gpu_write(gpu, REG_A4XX_RBBM_POWER_CNTL_IP, 0x778000);do {udelay(5);reg = gpu_read(gpu, REG_A4XX_RBBM_POWER_STATUS);} while (!(reg & SP_TP_PWR_ON));}
Imho wrapping things the opposite way -> include the 430 specifics in msm_gpu_pm_resume/suspend. If needed.
Hmm is it me or the above register definitions are missing in linux/master and linux/next ? What did you use as a base for the series ?
Regards, Emil
On Mon, Feb 22, 2016 at 8:46 AM, Emil Velikov emil.l.velikov@gmail.com wrote:
On 19 February 2016 at 00:50, C Stout cstout@chromium.org wrote:
Change-Id: Ife53627e9985e1204cc319da0221338e5272eb81
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 39 +++++++++++++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c index 9a1ffec..9aab904 100644 --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c @@ -552,12 +552,47 @@ static void a4xx_dump(struct msm_gpu *gpu) adreno_dump(gpu); }
+static int a4xx_pm_resume(struct msm_gpu *gpu) {
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);int ret;ret = msm_gpu_pm_resume(gpu);if (ret)return ret;if (adreno_is_a430(adreno_gpu)) {unsigned int reg;/* Set the default register values; set SW_COLLAPSE to 0 */gpu_write(gpu, REG_A4XX_RBBM_POWER_CNTL_IP, 0x778000);do {udelay(5);reg = gpu_read(gpu, REG_A4XX_RBBM_POWER_STATUS);} while (!(reg & SP_TP_PWR_ON));}Imho wrapping things the opposite way -> include the 430 specifics in msm_gpu_pm_resume/suspend. If needed.
fyi, the reason for the three level "class" hierarchy (msm_gpu/adreno/aXYZ) was originally so that we could perhaps some day add support for the 2d cores present on some older snapdragons (back in the a2xx days). Not sure if we'll ever do this (upstream kernel support on those older gen's isn't so much there). But at least right now putting that in msm_gpu_pm_resume() isn't really the right thing.
Hmm is it me or the above register definitions are missing in linux/master and linux/next ? What did you use as a base for the series ?
They are in msm-next:
https://cgit.freedesktop.org/~robclark/linux/log/?h=msm-next
(basically for register definitions, they just need to end up in the envytools register database, and then I just regenerate the headers to pull in the latest.. that is easier than dealing with merge conflicts if everyone just adds the needed regs as part of their patch)
BR, -R
On 22 February 2016 at 14:51, Rob Clark robdclark@gmail.com wrote:
On Mon, Feb 22, 2016 at 8:46 AM, Emil Velikov emil.l.velikov@gmail.com wrote:
On 19 February 2016 at 00:50, C Stout cstout@chromium.org wrote:
Change-Id: Ife53627e9985e1204cc319da0221338e5272eb81
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 39 +++++++++++++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c index 9a1ffec..9aab904 100644 --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c @@ -552,12 +552,47 @@ static void a4xx_dump(struct msm_gpu *gpu) adreno_dump(gpu); }
+static int a4xx_pm_resume(struct msm_gpu *gpu) {
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);int ret;ret = msm_gpu_pm_resume(gpu);if (ret)return ret;if (adreno_is_a430(adreno_gpu)) {unsigned int reg;/* Set the default register values; set SW_COLLAPSE to 0 */gpu_write(gpu, REG_A4XX_RBBM_POWER_CNTL_IP, 0x778000);do {udelay(5);reg = gpu_read(gpu, REG_A4XX_RBBM_POWER_STATUS);} while (!(reg & SP_TP_PWR_ON));}Imho wrapping things the opposite way -> include the 430 specifics in msm_gpu_pm_resume/suspend. If needed.
fyi, the reason for the three level "class" hierarchy (msm_gpu/adreno/aXYZ) was originally so that we could perhaps some day add support for the 2d cores present on some older snapdragons (back in the a2xx days). Not sure if we'll ever do this (upstream kernel support on those older gen's isn't so much there). But at least right now putting that in msm_gpu_pm_resume() isn't really the right thing.
Nice one.
Hmm is it me or the above register definitions are missing in linux/master and linux/next ? What did you use as a base for the series ?
They are in msm-next:
https://cgit.freedesktop.org/~robclark/linux/log/?h=msm-next
(basically for register definitions, they just need to end up in the envytools register database, and then I just regenerate the headers to pull in the latest.. that is easier than dealing with merge conflicts if everyone just adds the needed regs as part of their patch)
For some strange reason git grep did not list them even though msm-next is part of linux/next.
Thanks for setting me straight Rob, apologies for the noise.
Regards, Emil
From: cstout cstout@google.com
As described in the downstream/kgsl driver: Sometimes the RPTR shadow memory is unreliable causing timeouts in adreno_idle(). Read it directly from the register instead.
Change-Id: I1617a670e1da0ae25528c37f3424654d5bedd169 --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 34 +++++++++++++++++++++------------ 1 file changed, 22 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 0e76a21..95e582e 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -68,18 +68,15 @@ int adreno_hw_init(struct msm_gpu *gpu) adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_CNTL, /* size is log2(quad-words): */ AXXX_CP_RB_CNTL_BUFSZ(ilog2(gpu->rb->size / 8)) | - AXXX_CP_RB_CNTL_BLKSZ(ilog2(RB_BLKSIZE / 8))); + AXXX_CP_RB_CNTL_BLKSZ(ilog2(RB_BLKSIZE / 8)) | + (adreno_is_a430(adreno_gpu) ? AXXX_CP_RB_CNTL_NO_UPDATE : 0));
/* Setup ringbuffer address: */ adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_BASE, gpu->rb_iova); - adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR, - rbmemptr(adreno_gpu, rptr));
- /* Setup scratch/timestamp: */ - adreno_gpu_write(adreno_gpu, REG_ADRENO_SCRATCH_ADDR, - rbmemptr(adreno_gpu, fence)); - - adreno_gpu_write(adreno_gpu, REG_ADRENO_SCRATCH_UMSK, 0x1); + if (!adreno_is_a430(adreno_gpu)) + adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR, + rbmemptr(adreno_gpu, rptr));
return 0; } @@ -89,6 +86,16 @@ static uint32_t get_wptr(struct msm_ringbuffer *ring) return ring->cur - ring->start; }
+/* Use this helper to read rptr, since a430 doesn't update rptr in memory */ +static uint32_t get_rptr(struct adreno_gpu *adreno_gpu) +{ + if (adreno_is_a430(adreno_gpu)) + return adreno_gpu->memptrs->rptr = adreno_gpu_read( + adreno_gpu, REG_ADRENO_CP_RB_RPTR); + else + return adreno_gpu->memptrs->rptr; +} + uint32_t adreno_last_fence(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); @@ -217,9 +224,12 @@ void adreno_idle(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); uint32_t wptr = get_wptr(gpu->rb); + int ret;
/* wait for CP to drain ringbuffer: */ - if (spin_until(adreno_gpu->memptrs->rptr == wptr)) + ret = spin_until(get_rptr(adreno_gpu) == wptr); + + if (ret) DRM_ERROR("%s: timeout waiting to drain ringbuffer!\n", gpu->name);
/* TODO maybe we need to reset GPU here to recover from hang? */ @@ -238,7 +248,7 @@ void adreno_show(struct msm_gpu *gpu, struct seq_file *m)
seq_printf(m, "fence: %d/%d\n", adreno_gpu->memptrs->fence, gpu->submitted_fence); - seq_printf(m, "rptr: %d\n", adreno_gpu->memptrs->rptr); + seq_printf(m, "rptr: %d\n", get_rptr(adreno_gpu)); seq_printf(m, "wptr: %d\n", adreno_gpu->memptrs->wptr); seq_printf(m, "rb wptr: %d\n", get_wptr(gpu->rb));
@@ -279,7 +289,7 @@ void adreno_dump_info(struct msm_gpu *gpu)
printk("fence: %d/%d\n", adreno_gpu->memptrs->fence, gpu->submitted_fence); - printk("rptr: %d\n", adreno_gpu->memptrs->rptr); + printk("rptr: %d\n", get_rptr(adreno_gpu)); printk("wptr: %d\n", adreno_gpu->memptrs->wptr); printk("rb wptr: %d\n", get_wptr(gpu->rb));
@@ -314,7 +324,7 @@ static uint32_t ring_freewords(struct msm_gpu *gpu) struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); uint32_t size = gpu->rb->size / 4; uint32_t wptr = get_wptr(gpu->rb); - uint32_t rptr = adreno_gpu->memptrs->rptr; + uint32_t rptr = get_rptr(adreno_gpu); return (rptr + (size - 1) - wptr) % size; }
From: cstout cstout@google.com
Change-Id: I44f9854e7a7458730d9bfbfeef3361c438e381d2 --- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c index 9aab904..496732d 100644 --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c @@ -357,6 +357,13 @@ static irqreturn_t a4xx_irq(struct msm_gpu *gpu) status = gpu_read(gpu, REG_A4XX_RBBM_INT_0_STATUS); DBG("%s: Int status %08x", gpu->name, status);
+ if (status & (1 << A4XX_INT_CP_REG_PROTECT_FAULT)) { + uint32_t reg = gpu_read(gpu, REG_A4XX_CP_PROTECT_STATUS); + printk("CP | Protected mode error| %s | addr=%x\n", + reg & (1 << 24) ? "WRITE" : "READ", + (reg & 0xFFFFF) >> 2); + } + gpu_write(gpu, REG_A4XX_RBBM_INT_CLEAR_CMD, status);
msm_gpu_retire(gpu);
[Cutting down the CC list]
Hi there,
Must admit that looking at contributors from chromium.org feels quite heart warming.
On 19 February 2016 at 00:50, C Stout cstout@chromium.org wrote:
Change-Id: I6c891515d93a6f1a597e762090c3530a6810c6c6
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 43 +++++++++++++++++++++++++----- drivers/gpu/drm/msm/adreno/adreno_device.c | 8 ++++++ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 ++- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 ++++ 4 files changed, 52 insertions(+), 7 deletions(-)
Please include your fill name and a signed-off-by as mentioned in the documentation [1]. Without those the maintainer/Rob C cannot pick your work.
While you're there you can nuke the Change-id tag - they're normally frowned upon by kernel developers although Rob might be ok keeping them. Please add a line or two of commit message. Some examples/ideas - what are the differences wrt the 420 devices and/or how you noticed them (official documentation, reverse engineering). what's missing to get the devices fully working, how it's been tested, etc.
Regards Emil
[1] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Documen...
On 22 February 2016 at 12:48, Emil Velikov emil.l.velikov@gmail.com wrote:
[Cutting down the CC list]
Hi there,
Must admit that looking at contributors from chromium.org feels quite heart warming.
On 19 February 2016 at 00:50, C Stout cstout@chromium.org wrote:
Change-Id: I6c891515d93a6f1a597e762090c3530a6810c6c6
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 43 +++++++++++++++++++++++++----- drivers/gpu/drm/msm/adreno/adreno_device.c | 8 ++++++ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 ++- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 ++++ 4 files changed, 52 insertions(+), 7 deletions(-)
Please include your fill name and a signed-off-by as mentioned in the documentation [1]. Without those the maintainer/Rob C cannot pick your work.
While you're there you can nuke the Change-id tag - they're normally frowned upon by kernel developers although Rob might be ok keeping them. Please add a line or two of commit message. Some examples/ideas
- what are the differences wrt the 420 devices and/or how you noticed
them (official documentation, reverse engineering). what's missing to get the devices fully working, how it's been tested, etc.
Completely forgot: prefix the patches based on the subsystem used. Otherwise it's more likely that the maintainer email filter will miss them. Thinking about "drm/msm: add support for adreno 430" although git log is your friend.
Regards, Emil
dri-devel@lists.freedesktop.org
-
C Stout -
Emil Velikov -
Rob Clark