DP 1.4 specification defines Link Training Tunable PHY Repeater (LTTPR) which is required to add support for systems with Thunderbolt or other repeater devices.
Cc: Abdoulaye Berthe Abdoulaye.Berthe@amd.com Cc: Harry Wentland harry.wentland@amd.com Cc: Leo Li sunpeng.li@amd.com Signed-off-by: Rodrigo Siqueira Rodrigo.Siqueira@amd.com Signed-off-by: Abdoulaye Berthe Abdoulaye.Berthe@amd.com --- include/drm/drm_dp_helper.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 8364502f92cf..8336d960da7f 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -134,6 +134,32 @@ #define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */ # define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */
+/** Link Training (LT)-tunable Physical Repeaters - DP 1.4 **/ +#define DP_LTTPR_REV 0xf0000 +#define DP_LTTPR_MAX_LINK_RATE 0xf0001 +#define DP_LTTPR_REPEATER_CNT 0xf0002 +#define DP_LTTPR_REPEATER_MODE 0xf0003 +#define DP_LTTPR_MAX_LANE_CNT 0xf0004 +#define DP_LTTPR_EXTENDED_WAIT_TIMEOUT 0xf0005 +#define DP_LTTPR_TRAINING_PATTERN_SET_REPEATER1 0xf0010 +#define DP_LTTPR_TRAINING_LANE0_SET_REPEATER1 0xf0011 +#define DP_LTTPR_TRAINING_LANE1_SET_REPEATER1 0xf0012 +#define DP_LTTPR_TRAINING_LANE2_SET_REPEATER1 0xf0013 +#define DP_LTTPR_TRAINING_LANE3_SET_REPEATER1 0xf0014 +#define DP_LTTPR_TRAINING_AUX_RD_INTERVAL_REPEATER1 0xf0020 +#define DP_LTTPR_TRANSMITTER_CAPABILITY_REPEATER1 0xf0021 +#define DP_LTTPR_LANE0_1_STATUS_REPEATER1 0xf0030 +#define DP_LTTPR_LANE2_3_STATUS_REPEATER1 0xf0031 +#define DP_LTTPR_LANE_ALIGN_STATUS_UPDATED_REPEATER1 0xf0032 +#define DP_LTTPR_ADJUST_REQUEST_LANE0_1_REPEATER1 0xf0033 +#define DP_LTTPR_ADJUST_REQUEST_LANE2_3_REPEATER1 0xf0034 +#define DP_LTTPR_SYMBOL_ERROR_COUNT_LANE0_REPEATER1 0xf0035 +#define DP_LTTPR_SYMBOL_ERROR_COUNT_LANE1_REPEATER1 0xf0037 +#define DP_LTTPR_SYMBOL_ERROR_COUNT_LANE2_REPEATER1 0xf0039 +#define DP_LTTPR_SYMBOL_ERROR_COUNT_LANE3_REPEATER1 0xf003b +#define DP_REPEATER_CONFIGURATION_AND_STATUS_OFFSET 0x50 +#define DP_LTTPR_FEC_STATUS_REPEATER1 0xf0290 + /* Multiple stream transport */ #define DP_FAUX_CAP 0x020 /* 1.2 */ # define DP_FAUX_CAP_1 (1 << 0)
On 2019-08-22 6:46 p.m., Siqueira, Rodrigo wrote:
DP 1.4 specification defines Link Training Tunable PHY Repeater (LTTPR) which is required to add support for systems with Thunderbolt or other repeater devices.
Cc: Abdoulaye Berthe Abdoulaye.Berthe@amd.com Cc: Harry Wentland harry.wentland@amd.com Cc: Leo Li sunpeng.li@amd.com Signed-off-by: Rodrigo Siqueira Rodrigo.Siqueira@amd.com Signed-off-by: Abdoulaye Berthe Abdoulaye.Berthe@amd.com
include/drm/drm_dp_helper.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 8364502f92cf..8336d960da7f 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -134,6 +134,32 @@ #define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */ # define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */
+/** Link Training (LT)-tunable Physical Repeaters - DP 1.4 **/ +#define DP_LTTPR_REV 0xf0000 +#define DP_LTTPR_MAX_LINK_RATE 0xf0001 +#define DP_LTTPR_REPEATER_CNT 0xf0002 +#define DP_LTTPR_REPEATER_MODE 0xf0003 +#define DP_LTTPR_MAX_LANE_CNT 0xf0004 +#define DP_LTTPR_EXTENDED_WAIT_TIMEOUT 0xf0005 +#define DP_LTTPR_TRAINING_PATTERN_SET_REPEATER1 0xf0010 +#define DP_LTTPR_TRAINING_LANE0_SET_REPEATER1 0xf0011 +#define DP_LTTPR_TRAINING_LANE1_SET_REPEATER1 0xf0012 +#define DP_LTTPR_TRAINING_LANE2_SET_REPEATER1 0xf0013 +#define DP_LTTPR_TRAINING_LANE3_SET_REPEATER1 0xf0014
Can we align the register naming with the spec and to align with the rest of this file?
The seem to take the form of DP_<name-from-spec>
E.g. call this one DP_TRAINING_LANE3_SET_PHY_REPEATER1
Same for all other registers.
Keeping the naming consistent makes it easier to search.
+#define DP_LTTPR_TRAINING_AUX_RD_INTERVAL_REPEATER1 0xf0020 +#define DP_LTTPR_TRANSMITTER_CAPABILITY_REPEATER1 0xf0021 +#define DP_LTTPR_LANE0_1_STATUS_REPEATER1 0xf0030 +#define DP_LTTPR_LANE2_3_STATUS_REPEATER1 0xf0031 +#define DP_LTTPR_LANE_ALIGN_STATUS_UPDATED_REPEATER1 0xf0032 +#define DP_LTTPR_ADJUST_REQUEST_LANE0_1_REPEATER1 0xf0033 +#define DP_LTTPR_ADJUST_REQUEST_LANE2_3_REPEATER1 0xf0034 +#define DP_LTTPR_SYMBOL_ERROR_COUNT_LANE0_REPEATER1 0xf0035 +#define DP_LTTPR_SYMBOL_ERROR_COUNT_LANE1_REPEATER1 0xf0037 +#define DP_LTTPR_SYMBOL_ERROR_COUNT_LANE2_REPEATER1 0xf0039 +#define DP_LTTPR_SYMBOL_ERROR_COUNT_LANE3_REPEATER1 0xf003b +#define DP_REPEATER_CONFIGURATION_AND_STATUS_OFFSET 0x50
With a cursory search I can't seem to find this in the spec. Where is this coming from?
Harry
+#define DP_LTTPR_FEC_STATUS_REPEATER1 0xf0290> + /* Multiple stream transport */ #define DP_FAUX_CAP 0x020 /* 1.2 */ # define DP_FAUX_CAP_1 (1 << 0)
Hi Harry,
Thanks for your feedback, I'll prepare a V2.
On 08/23, Wentland, Harry wrote:
On 2019-08-22 6:46 p.m., Siqueira, Rodrigo wrote:
DP 1.4 specification defines Link Training Tunable PHY Repeater (LTTPR) which is required to add support for systems with Thunderbolt or other repeater devices.
Cc: Abdoulaye Berthe Abdoulaye.Berthe@amd.com Cc: Harry Wentland harry.wentland@amd.com Cc: Leo Li sunpeng.li@amd.com Signed-off-by: Rodrigo Siqueira Rodrigo.Siqueira@amd.com Signed-off-by: Abdoulaye Berthe Abdoulaye.Berthe@amd.com
include/drm/drm_dp_helper.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 8364502f92cf..8336d960da7f 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -134,6 +134,32 @@ #define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */ # define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */
+/** Link Training (LT)-tunable Physical Repeaters - DP 1.4 **/ +#define DP_LTTPR_REV 0xf0000 +#define DP_LTTPR_MAX_LINK_RATE 0xf0001 +#define DP_LTTPR_REPEATER_CNT 0xf0002 +#define DP_LTTPR_REPEATER_MODE 0xf0003 +#define DP_LTTPR_MAX_LANE_CNT 0xf0004 +#define DP_LTTPR_EXTENDED_WAIT_TIMEOUT 0xf0005 +#define DP_LTTPR_TRAINING_PATTERN_SET_REPEATER1 0xf0010 +#define DP_LTTPR_TRAINING_LANE0_SET_REPEATER1 0xf0011 +#define DP_LTTPR_TRAINING_LANE1_SET_REPEATER1 0xf0012 +#define DP_LTTPR_TRAINING_LANE2_SET_REPEATER1 0xf0013 +#define DP_LTTPR_TRAINING_LANE3_SET_REPEATER1 0xf0014
Can we align the register naming with the spec and to align with the rest of this file?
The seem to take the form of DP_<name-from-spec>
E.g. call this one DP_TRAINING_LANE3_SET_PHY_REPEATER1
Same for all other registers.
Keeping the naming consistent makes it easier to search.
+#define DP_LTTPR_TRAINING_AUX_RD_INTERVAL_REPEATER1 0xf0020 +#define DP_LTTPR_TRANSMITTER_CAPABILITY_REPEATER1 0xf0021 +#define DP_LTTPR_LANE0_1_STATUS_REPEATER1 0xf0030 +#define DP_LTTPR_LANE2_3_STATUS_REPEATER1 0xf0031 +#define DP_LTTPR_LANE_ALIGN_STATUS_UPDATED_REPEATER1 0xf0032 +#define DP_LTTPR_ADJUST_REQUEST_LANE0_1_REPEATER1 0xf0033 +#define DP_LTTPR_ADJUST_REQUEST_LANE2_3_REPEATER1 0xf0034 +#define DP_LTTPR_SYMBOL_ERROR_COUNT_LANE0_REPEATER1 0xf0035 +#define DP_LTTPR_SYMBOL_ERROR_COUNT_LANE1_REPEATER1 0xf0037 +#define DP_LTTPR_SYMBOL_ERROR_COUNT_LANE2_REPEATER1 0xf0039 +#define DP_LTTPR_SYMBOL_ERROR_COUNT_LANE3_REPEATER1 0xf003b +#define DP_REPEATER_CONFIGURATION_AND_STATUS_OFFSET 0x50
With a cursory search I can't seem to find this in the spec. Where is this coming from?
Harry
+#define DP_LTTPR_FEC_STATUS_REPEATER1 0xf0290> + /* Multiple stream transport */ #define DP_FAUX_CAP 0x020 /* 1.2 */ # define DP_FAUX_CAP_1 (1 << 0)
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Siqueira, Rodrigo