Matthew Auld matthew.auld@intel.com writes:

If we need to mark the PDE as operating in 64K GTT mode, we should be paranoid and flush the extra writes, like we already do for the PTEs. On some platforms the clflush can apparently add the just the right amount of magical delay to force the GPU to see the updated entry.

Signed-off-by: Matthew Auld matthew.auld@intel.com Cc: Mika Kuoppala mika.kuoppala@linux.intel.com

Makes sense to follow the same pattern as the other writes.

Reviewed-by: Mika Kuoppala mika.kuoppala@linux.intel.com

---

drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c index 6e0e52eeb87a..6a5af995f5b1 100644 --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c @@ -548,6 +548,7 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma, I915_GTT_PAGE_SIZE_2M)))) { vaddr = px_vaddr(pd); vaddr[maybe_64K] |= GEN8_PDE_IPS_64K;

• 	clflush_cache_range(vaddr, PAGE_SIZE);
  page_size = I915_GTT_PAGE_SIZE_64K;
  
  /*
  

@@ -568,6 +569,7 @@ static void gen8_ppgtt_insert_huge(struct i915_vma *vma, for (i = 1; i < index; i += 16) memset64(vaddr + i, encode, 15);

• 		clflush_cache_range(vaddr, PAGE_SIZE);
  }
  

  }

-- 2.26.3