The dpi/dpintf driver and the added helper functions are required for the DisplayPort driver to work.
This series is separated from [1] which is original from Guillaume. The display port driver is [2].
Changes for v13: 1. Change mediatek,mt8195-dp_intf to mediatek,mt8195-dp-intf. 2. Add kernel doc for mtk_dpi_conf. 3. Drop patch of tvd_pll enable. 4. Squash some color format transfer related patches. 5. Add new patch to support setting of direct connection to pins. 6. Change fix tag of "drm/mediatek: dpi: Only enable dpi after the bridge is enabled".
Changes for v12: 1. Remove pll_gate. 2. Add more detailed commit message. 3. Separate tvd_clk patch and yuv422 output support from add dpintf support patch 4. Remove limit patch and use common driver codes to determine this.
Changes for v11: 1. Rename ck_cg to pll_gate. 2. Add some commit message to clarify the modification reason. 3. Fix some driver order and modify for reviewers' comments.
[1]:https://lore.kernel.org/all/20220523104758.29531-1-granquet@baylibre.com/ [2]:https://lore.kernel.org/all/20220610105522.13449-1-rex-bc.chen@mediatek.com/
Bo-Chen Chen (4): drm/mediatek: dpi: Add kernel document for struct mtk_dpi_conf drm/mediatek: dpi: Add support for quantization range drm/mediatek: dpi: Add YUV422 output support drm/mediatek: dpi: add config to control setting of direct connection to pins
Guillaume Ranquet (9): drm/mediatek: dpi: implement a CK/DE pol toggle in SoC config drm/mediatek: dpi: implement a swap_input toggle in SoC config drm/mediatek: dpi: move dimension mask to SoC config drm/mediatek: dpi: move hvsize_mask to SoC config drm/mediatek: dpi: move swap_shift to SoC config drm/mediatek: dpi: move the yuv422_en_bit to SoC config drm/mediatek: dpi: move the csc_enable bit to SoC config drm/mediatek: dpi: Add dp_intf support drm/mediatek: dpi: Only enable dpi after the bridge is enabled
Markus Schneider-Pargmann (1): dt-bindings: mediatek,dpi: Add DP_INTF compatible
.../display/mediatek/mediatek,dpi.yaml | 11 +- drivers/gpu/drm/mediatek/mtk_dpi.c | 266 +++++++++++++++--- drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 15 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 4 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 + 6 files changed, 253 insertions(+), 47 deletions(-)
From: Markus Schneider-Pargmann msp@baylibre.com
DP_INTF is similar to DPI but does not have the exact same feature set or register layouts.
DP_INTF is the sink of the display pipeline that is connected to the DisplayPort controller and encoder unit. It takes the same clocks as DPI.
In this patch, we also do these string replacement: - s/mediatek/MediaTek/ in title. - s/Mediatek/MediaTek/ in description.
Signed-off-by: Markus Schneider-Pargmann msp@baylibre.com Signed-off-by: Guillaume Ranquet granquet@baylibre.com [Bo-Chen: Modify reviewers' comments.] Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com --- .../bindings/display/mediatek/mediatek,dpi.yaml | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml index 77ee1b923991..5bb23e97cf33 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml @@ -4,16 +4,16 @@ $id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml#
-title: mediatek DPI Controller Device Tree Bindings +title: MediaTek DPI and DP_INTF Controller
maintainers: - CK Hu ck.hu@mediatek.com - Jitao shi jitao.shi@mediatek.com
description: | - The Mediatek DPI function block is a sink of the display subsystem and - provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel - output bus. + The MediaTek DPI and DP_INTF function blocks are a sink of the display + subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a + parallel output bus.
properties: compatible: @@ -24,6 +24,7 @@ properties: - mediatek,mt8183-dpi - mediatek,mt8186-dpi - mediatek,mt8192-dpi + - mediatek,mt8195-dp-intf
reg: maxItems: 1 @@ -55,7 +56,7 @@ properties: $ref: /schemas/graph.yaml#/properties/port description: Output port node. This port should be connected to the input port of an - attached HDMI or LVDS encoder chip. + attached HDMI, LVDS or DisplayPort encoder chip.
required: - compatible
Il 21/06/22 13:37, Bo-Chen Chen ha scritto:
From: Markus Schneider-Pargmann msp@baylibre.com
DP_INTF is similar to DPI but does not have the exact same feature set or register layouts.
DP_INTF is the sink of the display pipeline that is connected to the DisplayPort controller and encoder unit. It takes the same clocks as DPI.
In this patch, we also do these string replacement:
- s/mediatek/MediaTek/ in title.
- s/Mediatek/MediaTek/ in description.
Signed-off-by: Markus Schneider-Pargmann msp@baylibre.com Signed-off-by: Guillaume Ranquet granquet@baylibre.com [Bo-Chen: Modify reviewers' comments.] Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com
Reviewed-by: AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com
Hi, Bo-Chen:
On Tue, 2022-06-21 at 19:37 +0800, Bo-Chen Chen wrote:
From: Markus Schneider-Pargmann msp@baylibre.com
DP_INTF is similar to DPI but does not have the exact same feature set or register layouts.
DP_INTF is the sink of the display pipeline that is connected to the DisplayPort controller and encoder unit. It takes the same clocks as DPI.
In this patch, we also do these string replacement:
- s/mediatek/MediaTek/ in title.
- s/Mediatek/MediaTek/ in description.
I would like one patch do one thing. The patch title is "Add DP_INTF compatible" so it would not imply refining the case of "MediaTek". So separate this to an independent patch.
Regards, CK
Signed-off-by: Markus Schneider-Pargmann msp@baylibre.com Signed-off-by: Guillaume Ranquet granquet@baylibre.com [Bo-Chen: Modify reviewers' comments.] Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com
.../bindings/display/mediatek/mediatek,dpi.yaml | 11 ++++++---
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yam l b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yam l index 77ee1b923991..5bb23e97cf33 100644
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yam l +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yam l @@ -4,16 +4,16 @@ $id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml#
-title: mediatek DPI Controller Device Tree Bindings +title: MediaTek DPI and DP_INTF Controller
maintainers:
- CK Hu ck.hu@mediatek.com
- Jitao shi jitao.shi@mediatek.com
description: |
- The Mediatek DPI function block is a sink of the display subsystem
and
- provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a
parallel
- output bus.
- The MediaTek DPI and DP_INTF function blocks are a sink of the
display
- subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422
pixel data on a
- parallel output bus.
properties: compatible: @@ -24,6 +24,7 @@ properties: - mediatek,mt8183-dpi - mediatek,mt8186-dpi - mediatek,mt8192-dpi
- mediatek,mt8195-dp-intfreg: maxItems: 1
@@ -55,7 +56,7 @@ properties: $ref: /schemas/graph.yaml#/properties/port description: Output port node. This port should be connected to the input port of an
attached HDMI or LVDS encoder chip.
attached HDMI, LVDS or DisplayPort encoder chip.required:
- compatible
This driver will support dp_intf and there are many configs between dpi and dp_intf. Therefore, we will add many configs in "struct mtk_dpi_conf". To let this structure more readable, we add this kernel doc.
Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com --- drivers/gpu/drm/mediatek/mtk_dpi.c | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index e61cd67b978f..f66a121ba0c9 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -118,6 +118,15 @@ struct mtk_dpi_yc_limit { u16 c_bottom; };
+/** + * struct mtk_dpi_conf - Configuration of mediatek dpi. + * @cal_factor: Callback function to calculate factor value. + * @reg_h_fre_con: Register address of frequency control. + * @max_clock_khz: Max clock frequency supported for this SoCs in khz units. + * @edge_sel_en: Enable of edge selection. + * @output_fmts: Array of supported output formats. + * @num_output_fmts: Quantity of supported output formats. + */ struct mtk_dpi_conf { unsigned int (*cal_factor)(int clock); u32 reg_h_fre_con;
Il 21/06/22 13:37, Bo-Chen Chen ha scritto:
This driver will support dp_intf and there are many configs between dpi and dp_intf. Therefore, we will add many configs in "struct mtk_dpi_conf". To let this structure more readable, we add this kernel doc.
Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com
Reviewed-by: AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com
For RGB colorimetry, CTA-861 support both limited and full range data when receiving video with RGB color space. We use drm_default_rgb_quant_range() to determine the correct setting.
Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_dpi.c | 34 ++++++++++++++++++------------ 1 file changed, 21 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index f66a121ba0c9..24f4b5618276 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -244,16 +244,30 @@ static void mtk_dpi_config_fb_size(struct mtk_dpi *dpi, u32 width, u32 height) mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, VSIZE_MASK); }
-static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi, - struct mtk_dpi_yc_limit *limit) +static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi) { - mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_bottom << Y_LIMINT_BOT, + struct mtk_dpi_yc_limit limit; + + if (drm_default_rgb_quant_range(&dpi->mode) == + HDMI_QUANTIZATION_RANGE_LIMITED) { + limit.y_bottom = 0x10; + limit.y_top = 0xfe0; + limit.c_bottom = 0x10; + limit.c_top = 0xfe0; + } else { + limit.y_bottom = 0; + limit.y_top = 0xfff; + limit.c_bottom = 0; + limit.c_top = 0xfff; + } + + mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit.y_bottom << Y_LIMINT_BOT, Y_LIMINT_BOT_MASK); - mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_top << Y_LIMINT_TOP, + mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit.y_top << Y_LIMINT_TOP, Y_LIMINT_TOP_MASK); - mtk_dpi_mask(dpi, DPI_C_LIMIT, limit->c_bottom << C_LIMIT_BOT, + mtk_dpi_mask(dpi, DPI_C_LIMIT, limit.c_bottom << C_LIMIT_BOT, C_LIMIT_BOT_MASK); - mtk_dpi_mask(dpi, DPI_C_LIMIT, limit->c_top << C_LIMIT_TOP, + mtk_dpi_mask(dpi, DPI_C_LIMIT, limit.c_top << C_LIMIT_TOP, C_LIMIT_TOP_MASK); }
@@ -458,7 +472,6 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, struct drm_display_mode *mode) { - struct mtk_dpi_yc_limit limit; struct mtk_dpi_polarities dpi_pol; struct mtk_dpi_sync_param hsync; struct mtk_dpi_sync_param vsync_lodd = { 0 }; @@ -493,11 +506,6 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n", pll_rate, vm.pixelclock);
- limit.c_bottom = 0x0010; - limit.c_top = 0x0FE0; - limit.y_bottom = 0x0010; - limit.y_top = 0x0FE0; - dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING; dpi_pol.de_pol = MTK_DPI_POLARITY_RISING; dpi_pol.hsync_pol = vm.flags & DISPLAY_FLAGS_HSYNC_HIGH ? @@ -545,7 +553,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, else mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive);
- mtk_dpi_config_channel_limit(dpi, &limit); + mtk_dpi_config_channel_limit(dpi); mtk_dpi_config_bit_num(dpi, dpi->bit_num); mtk_dpi_config_channel_swap(dpi, dpi->channel_swap); mtk_dpi_config_yc_map(dpi, dpi->yc_map);
Il 21/06/22 13:37, Bo-Chen Chen ha scritto:
For RGB colorimetry, CTA-861 support both limited and full range data when receiving video with RGB color space. We use drm_default_rgb_quant_range() to determine the correct setting.
Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com
Reviewed-by: AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com
From: Guillaume Ranquet granquet@baylibre.com
Dp_intf does not support CK/DE polarity because the polarity information is not used for eDP and DP while dp_intf is only for eDP and DP. Therefore, we add a bit of flexibility to support SoCs without CK/DE pol support.
Signed-off-by: Guillaume Ranquet granquet@baylibre.com [Bo-Chen: Add modification reason in commit message.] Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com Reviewed-by: AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com Reviewed-by: Rex-BC Chen rex-bc.chen@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_dpi.c | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 24f4b5618276..fc2ef10bef31 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -126,6 +126,7 @@ struct mtk_dpi_yc_limit { * @edge_sel_en: Enable of edge selection. * @output_fmts: Array of supported output formats. * @num_output_fmts: Quantity of supported output formats. + * @is_ck_de_pol: Support CK/DE polarity. */ struct mtk_dpi_conf { unsigned int (*cal_factor)(int clock); @@ -134,6 +135,7 @@ struct mtk_dpi_conf { bool edge_sel_en; const u32 *output_fmts; u32 num_output_fmts; + bool is_ck_de_pol; };
static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) @@ -219,13 +221,20 @@ static void mtk_dpi_config_pol(struct mtk_dpi *dpi, struct mtk_dpi_polarities *dpi_pol) { unsigned int pol; + unsigned int mask;
- pol = (dpi_pol->ck_pol == MTK_DPI_POLARITY_RISING ? 0 : CK_POL) | - (dpi_pol->de_pol == MTK_DPI_POLARITY_RISING ? 0 : DE_POL) | - (dpi_pol->hsync_pol == MTK_DPI_POLARITY_RISING ? 0 : HSYNC_POL) | + mask = HSYNC_POL | VSYNC_POL; + pol = (dpi_pol->hsync_pol == MTK_DPI_POLARITY_RISING ? 0 : HSYNC_POL) | (dpi_pol->vsync_pol == MTK_DPI_POLARITY_RISING ? 0 : VSYNC_POL); - mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, pol, - CK_POL | DE_POL | HSYNC_POL | VSYNC_POL); + if (dpi->conf->is_ck_de_pol) { + mask |= CK_POL | DE_POL; + pol |= (dpi_pol->ck_pol == MTK_DPI_POLARITY_RISING ? + 0 : CK_POL) | + (dpi_pol->de_pol == MTK_DPI_POLARITY_RISING ? + 0 : DE_POL); + } + + mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, pol, mask); }
static void mtk_dpi_config_3d(struct mtk_dpi *dpi, bool en_3d) @@ -813,6 +822,7 @@ static const struct mtk_dpi_conf mt8173_conf = { .max_clock_khz = 300000, .output_fmts = mt8173_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), + .is_ck_de_pol = true, };
static const struct mtk_dpi_conf mt2701_conf = { @@ -822,6 +832,7 @@ static const struct mtk_dpi_conf mt2701_conf = { .max_clock_khz = 150000, .output_fmts = mt8173_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), + .is_ck_de_pol = true, };
static const struct mtk_dpi_conf mt8183_conf = { @@ -830,6 +841,7 @@ static const struct mtk_dpi_conf mt8183_conf = { .max_clock_khz = 100000, .output_fmts = mt8183_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), + .is_ck_de_pol = true, };
static const struct mtk_dpi_conf mt8192_conf = { @@ -838,6 +850,7 @@ static const struct mtk_dpi_conf mt8192_conf = { .max_clock_khz = 150000, .output_fmts = mt8183_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), + .is_ck_de_pol = true, };
static int mtk_dpi_probe(struct platform_device *pdev)
From: Guillaume Ranquet granquet@baylibre.com
The hardware design of dp_intf does not support input swap, so we add a bit of flexibility to support SoCs without swap_input support. We also add a warning message if the hardware is not supported and it needs to swap input.
Signed-off-by: Guillaume Ranquet granquet@baylibre.com [Bo-Chen: Add modification reason in commit message.] Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com Reviewed-by: AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com Reviewed-by: Rex-BC Chen rex-bc.chen@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_dpi.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index fc2ef10bef31..bacd6c13186f 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -127,6 +127,7 @@ struct mtk_dpi_yc_limit { * @output_fmts: Array of supported output formats. * @num_output_fmts: Quantity of supported output formats. * @is_ck_de_pol: Support CK/DE polarity. + * @swap_input_support: Support input swap function. */ struct mtk_dpi_conf { unsigned int (*cal_factor)(int clock); @@ -136,6 +137,7 @@ struct mtk_dpi_conf { const u32 *output_fmts; u32 num_output_fmts; bool is_ck_de_pol; + bool swap_input_support; };
static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) @@ -400,18 +402,24 @@ static void mtk_dpi_config_color_format(struct mtk_dpi *dpi, (format == MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL)) { mtk_dpi_config_yuv422_enable(dpi, false); mtk_dpi_config_csc_enable(dpi, true); - mtk_dpi_config_swap_input(dpi, false); + if (dpi->conf->swap_input_support) + mtk_dpi_config_swap_input(dpi, false); mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_BGR); } else if ((format == MTK_DPI_COLOR_FORMAT_YCBCR_422) || (format == MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL)) { mtk_dpi_config_yuv422_enable(dpi, true); mtk_dpi_config_csc_enable(dpi, true); - mtk_dpi_config_swap_input(dpi, true); + if (dpi->conf->swap_input_support) + mtk_dpi_config_swap_input(dpi, true); + else + dev_warn(dpi->dev, + "Failed to swap input, hw is not supported.\n"); mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB); } else { mtk_dpi_config_yuv422_enable(dpi, false); mtk_dpi_config_csc_enable(dpi, false); - mtk_dpi_config_swap_input(dpi, false); + if (dpi->conf->swap_input_support) + mtk_dpi_config_swap_input(dpi, false); mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB); } } @@ -823,6 +831,7 @@ static const struct mtk_dpi_conf mt8173_conf = { .output_fmts = mt8173_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol = true, + .swap_input_support = true, };
static const struct mtk_dpi_conf mt2701_conf = { @@ -833,6 +842,7 @@ static const struct mtk_dpi_conf mt2701_conf = { .output_fmts = mt8173_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol = true, + .swap_input_support = true, };
static const struct mtk_dpi_conf mt8183_conf = { @@ -842,6 +852,7 @@ static const struct mtk_dpi_conf mt8183_conf = { .output_fmts = mt8183_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), .is_ck_de_pol = true, + .swap_input_support = true, };
static const struct mtk_dpi_conf mt8192_conf = { @@ -851,6 +862,7 @@ static const struct mtk_dpi_conf mt8192_conf = { .output_fmts = mt8183_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), .is_ck_de_pol = true, + .swap_input_support = true, };
static int mtk_dpi_probe(struct platform_device *pdev)
From: Guillaume Ranquet granquet@baylibre.com
Add flexibility by moving the dimension mask to the SoC config
Signed-off-by: Guillaume Ranquet granquet@baylibre.com Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com Reviewed-by: AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com Reviewed-by: Rex-BC Chen rex-bc.chen@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_dpi.c | 27 +++++++++++++++++---------- 1 file changed, 17 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index bacd6c13186f..2cc6f1339024 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -128,6 +128,8 @@ struct mtk_dpi_yc_limit { * @num_output_fmts: Quantity of supported output formats. * @is_ck_de_pol: Support CK/DE polarity. * @swap_input_support: Support input swap function. + * @dimension_mask: Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH + * (no shift). */ struct mtk_dpi_conf { unsigned int (*cal_factor)(int clock); @@ -138,6 +140,7 @@ struct mtk_dpi_conf { u32 num_output_fmts; bool is_ck_de_pol; bool swap_input_support; + u32 dimension_mask; };
static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) @@ -166,30 +169,30 @@ static void mtk_dpi_disable(struct mtk_dpi *dpi) static void mtk_dpi_config_hsync(struct mtk_dpi *dpi, struct mtk_dpi_sync_param *sync) { - mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH, - sync->sync_width << HPW, HPW_MASK); - mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, - sync->back_porch << HBP, HBP_MASK); + mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH, sync->sync_width << HPW, + dpi->conf->dimension_mask << HPW); + mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->back_porch << HBP, + dpi->conf->dimension_mask << HBP); mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->front_porch << HFP, - HFP_MASK); + dpi->conf->dimension_mask << HFP); }
static void mtk_dpi_config_vsync(struct mtk_dpi *dpi, struct mtk_dpi_sync_param *sync, u32 width_addr, u32 porch_addr) { - mtk_dpi_mask(dpi, width_addr, - sync->sync_width << VSYNC_WIDTH_SHIFT, - VSYNC_WIDTH_MASK); mtk_dpi_mask(dpi, width_addr, sync->shift_half_line << VSYNC_HALF_LINE_SHIFT, VSYNC_HALF_LINE_MASK); + mtk_dpi_mask(dpi, width_addr, + sync->sync_width << VSYNC_WIDTH_SHIFT, + dpi->conf->dimension_mask << VSYNC_WIDTH_SHIFT); mtk_dpi_mask(dpi, porch_addr, sync->back_porch << VSYNC_BACK_PORCH_SHIFT, - VSYNC_BACK_PORCH_MASK); + dpi->conf->dimension_mask << VSYNC_BACK_PORCH_SHIFT); mtk_dpi_mask(dpi, porch_addr, sync->front_porch << VSYNC_FRONT_PORCH_SHIFT, - VSYNC_FRONT_PORCH_MASK); + dpi->conf->dimension_mask << VSYNC_FRONT_PORCH_SHIFT); }
static void mtk_dpi_config_vsync_lodd(struct mtk_dpi *dpi, @@ -832,6 +835,7 @@ static const struct mtk_dpi_conf mt8173_conf = { .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol = true, .swap_input_support = true, + .dimension_mask = HPW_MASK, };
static const struct mtk_dpi_conf mt2701_conf = { @@ -843,6 +847,7 @@ static const struct mtk_dpi_conf mt2701_conf = { .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol = true, .swap_input_support = true, + .dimension_mask = HPW_MASK, };
static const struct mtk_dpi_conf mt8183_conf = { @@ -853,6 +858,7 @@ static const struct mtk_dpi_conf mt8183_conf = { .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), .is_ck_de_pol = true, .swap_input_support = true, + .dimension_mask = HPW_MASK, };
static const struct mtk_dpi_conf mt8192_conf = { @@ -863,6 +869,7 @@ static const struct mtk_dpi_conf mt8192_conf = { .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), .is_ck_de_pol = true, .swap_input_support = true, + .dimension_mask = HPW_MASK, };
static int mtk_dpi_probe(struct platform_device *pdev)
From: Guillaume Ranquet granquet@baylibre.com
Add flexibility by moving the hvsize mask to SoC specific config.
Signed-off-by: Guillaume Ranquet granquet@baylibre.com Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com Reviewed-by: AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com Reviewed-by: Rex-BC Chen rex-bc.chen@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_dpi.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 2cc6f1339024..e1aa62f0e763 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -130,6 +130,7 @@ struct mtk_dpi_yc_limit { * @swap_input_support: Support input swap function. * @dimension_mask: Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH * (no shift). + * @hvsize_mask: Mask of HSIZE and VSIZE mask (no shift). */ struct mtk_dpi_conf { unsigned int (*cal_factor)(int clock); @@ -141,6 +142,7 @@ struct mtk_dpi_conf { bool is_ck_de_pol; bool swap_input_support; u32 dimension_mask; + u32 hvsize_mask; };
static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) @@ -254,8 +256,10 @@ static void mtk_dpi_config_interface(struct mtk_dpi *dpi, bool inter)
static void mtk_dpi_config_fb_size(struct mtk_dpi *dpi, u32 width, u32 height) { - mtk_dpi_mask(dpi, DPI_SIZE, width << HSIZE, HSIZE_MASK); - mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, VSIZE_MASK); + mtk_dpi_mask(dpi, DPI_SIZE, width << HSIZE, + dpi->conf->hvsize_mask << HSIZE); + mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, + dpi->conf->hvsize_mask << VSIZE); }
static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi) @@ -836,6 +840,7 @@ static const struct mtk_dpi_conf mt8173_conf = { .is_ck_de_pol = true, .swap_input_support = true, .dimension_mask = HPW_MASK, + .hvsize_mask = HSIZE_MASK, };
static const struct mtk_dpi_conf mt2701_conf = { @@ -848,6 +853,7 @@ static const struct mtk_dpi_conf mt2701_conf = { .is_ck_de_pol = true, .swap_input_support = true, .dimension_mask = HPW_MASK, + .hvsize_mask = HSIZE_MASK, };
static const struct mtk_dpi_conf mt8183_conf = { @@ -859,6 +865,7 @@ static const struct mtk_dpi_conf mt8183_conf = { .is_ck_de_pol = true, .swap_input_support = true, .dimension_mask = HPW_MASK, + .hvsize_mask = HSIZE_MASK, };
static const struct mtk_dpi_conf mt8192_conf = { @@ -870,6 +877,7 @@ static const struct mtk_dpi_conf mt8192_conf = { .is_ck_de_pol = true, .swap_input_support = true, .dimension_mask = HPW_MASK, + .hvsize_mask = HSIZE_MASK, };
static int mtk_dpi_probe(struct platform_device *pdev)
From: Guillaume Ranquet granquet@baylibre.com
Add flexibility by moving the swap shift value to SoC specific config.
Signed-off-by: Guillaume Ranquet granquet@baylibre.com Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com Reviewed-by: Rex-BC Chen rex-bc.chen@mediatek.com Reviewed-by: AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_dpi.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index e1aa62f0e763..f168a24f10ce 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -131,6 +131,7 @@ struct mtk_dpi_yc_limit { * @dimension_mask: Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH * (no shift). * @hvsize_mask: Mask of HSIZE and VSIZE mask (no shift). + * @channel_swap_shift: Shift value of channel swap. */ struct mtk_dpi_conf { unsigned int (*cal_factor)(int clock); @@ -143,6 +144,7 @@ struct mtk_dpi_conf { bool swap_input_support; u32 dimension_mask; u32 hvsize_mask; + u32 channel_swap_shift; };
static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) @@ -373,7 +375,9 @@ static void mtk_dpi_config_channel_swap(struct mtk_dpi *dpi, break; }
- mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << CH_SWAP, CH_SWAP_MASK); + mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, + val << dpi->conf->channel_swap_shift, + CH_SWAP_MASK << dpi->conf->channel_swap_shift); }
static void mtk_dpi_config_yuv422_enable(struct mtk_dpi *dpi, bool enable) @@ -841,6 +845,7 @@ static const struct mtk_dpi_conf mt8173_conf = { .swap_input_support = true, .dimension_mask = HPW_MASK, .hvsize_mask = HSIZE_MASK, + .channel_swap_shift = CH_SWAP, };
static const struct mtk_dpi_conf mt2701_conf = { @@ -854,6 +859,7 @@ static const struct mtk_dpi_conf mt2701_conf = { .swap_input_support = true, .dimension_mask = HPW_MASK, .hvsize_mask = HSIZE_MASK, + .channel_swap_shift = CH_SWAP, };
static const struct mtk_dpi_conf mt8183_conf = { @@ -866,6 +872,7 @@ static const struct mtk_dpi_conf mt8183_conf = { .swap_input_support = true, .dimension_mask = HPW_MASK, .hvsize_mask = HSIZE_MASK, + .channel_swap_shift = CH_SWAP, };
static const struct mtk_dpi_conf mt8192_conf = { @@ -878,6 +885,7 @@ static const struct mtk_dpi_conf mt8192_conf = { .swap_input_support = true, .dimension_mask = HPW_MASK, .hvsize_mask = HSIZE_MASK, + .channel_swap_shift = CH_SWAP, };
static int mtk_dpi_probe(struct platform_device *pdev)
From: Guillaume Ranquet granquet@baylibre.com
Add flexibility by moving the yuv422 en bit to SoC specific config
Signed-off-by: Guillaume Ranquet granquet@baylibre.com Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com Reviewed-by: AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com Reviewed-by: Rex-BC Chen rex-bc.chen@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_dpi.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index f168a24f10ce..3a5555a26cd1 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -132,6 +132,7 @@ struct mtk_dpi_yc_limit { * (no shift). * @hvsize_mask: Mask of HSIZE and VSIZE mask (no shift). * @channel_swap_shift: Shift value of channel swap. + * @yuv422_en_bit: Enable bit of yuv422. */ struct mtk_dpi_conf { unsigned int (*cal_factor)(int clock); @@ -145,6 +146,7 @@ struct mtk_dpi_conf { u32 dimension_mask; u32 hvsize_mask; u32 channel_swap_shift; + u32 yuv422_en_bit; };
static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) @@ -382,7 +384,8 @@ static void mtk_dpi_config_channel_swap(struct mtk_dpi *dpi,
static void mtk_dpi_config_yuv422_enable(struct mtk_dpi *dpi, bool enable) { - mtk_dpi_mask(dpi, DPI_CON, enable ? YUV422_EN : 0, YUV422_EN); + mtk_dpi_mask(dpi, DPI_CON, enable ? dpi->conf->yuv422_en_bit : 0, + dpi->conf->yuv422_en_bit); }
static void mtk_dpi_config_csc_enable(struct mtk_dpi *dpi, bool enable) @@ -846,6 +849,7 @@ static const struct mtk_dpi_conf mt8173_conf = { .dimension_mask = HPW_MASK, .hvsize_mask = HSIZE_MASK, .channel_swap_shift = CH_SWAP, + .yuv422_en_bit = YUV422_EN, };
static const struct mtk_dpi_conf mt2701_conf = { @@ -860,6 +864,7 @@ static const struct mtk_dpi_conf mt2701_conf = { .dimension_mask = HPW_MASK, .hvsize_mask = HSIZE_MASK, .channel_swap_shift = CH_SWAP, + .yuv422_en_bit = YUV422_EN, };
static const struct mtk_dpi_conf mt8183_conf = { @@ -873,6 +878,7 @@ static const struct mtk_dpi_conf mt8183_conf = { .dimension_mask = HPW_MASK, .hvsize_mask = HSIZE_MASK, .channel_swap_shift = CH_SWAP, + .yuv422_en_bit = YUV422_EN, };
static const struct mtk_dpi_conf mt8192_conf = { @@ -886,6 +892,7 @@ static const struct mtk_dpi_conf mt8192_conf = { .dimension_mask = HPW_MASK, .hvsize_mask = HSIZE_MASK, .channel_swap_shift = CH_SWAP, + .yuv422_en_bit = YUV422_EN, };
static int mtk_dpi_probe(struct platform_device *pdev)
From: Guillaume Ranquet granquet@baylibre.com
Add flexibility by moving the csc_enable bit to SoC specific config
Signed-off-by: Guillaume Ranquet granquet@baylibre.com Reviewed-by: AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com Reviewed-by: Rex-BC Chen rex-bc.chen@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_dpi.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 3a5555a26cd1..9e4250356342 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -133,6 +133,7 @@ struct mtk_dpi_yc_limit { * @hvsize_mask: Mask of HSIZE and VSIZE mask (no shift). * @channel_swap_shift: Shift value of channel swap. * @yuv422_en_bit: Enable bit of yuv422. + * @csc_enable_bit: Enable bit of CSC. */ struct mtk_dpi_conf { unsigned int (*cal_factor)(int clock); @@ -147,6 +148,7 @@ struct mtk_dpi_conf { u32 hvsize_mask; u32 channel_swap_shift; u32 yuv422_en_bit; + u32 csc_enable_bit; };
static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) @@ -390,7 +392,8 @@ static void mtk_dpi_config_yuv422_enable(struct mtk_dpi *dpi, bool enable)
static void mtk_dpi_config_csc_enable(struct mtk_dpi *dpi, bool enable) { - mtk_dpi_mask(dpi, DPI_CON, enable ? CSC_ENABLE : 0, CSC_ENABLE); + mtk_dpi_mask(dpi, DPI_CON, enable ? dpi->conf->csc_enable_bit : 0, + dpi->conf->csc_enable_bit); }
static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable) @@ -850,6 +853,7 @@ static const struct mtk_dpi_conf mt8173_conf = { .hvsize_mask = HSIZE_MASK, .channel_swap_shift = CH_SWAP, .yuv422_en_bit = YUV422_EN, + .csc_enable_bit = CSC_ENABLE, };
static const struct mtk_dpi_conf mt2701_conf = { @@ -865,6 +869,7 @@ static const struct mtk_dpi_conf mt2701_conf = { .hvsize_mask = HSIZE_MASK, .channel_swap_shift = CH_SWAP, .yuv422_en_bit = YUV422_EN, + .csc_enable_bit = CSC_ENABLE, };
static const struct mtk_dpi_conf mt8183_conf = { @@ -879,6 +884,7 @@ static const struct mtk_dpi_conf mt8183_conf = { .hvsize_mask = HSIZE_MASK, .channel_swap_shift = CH_SWAP, .yuv422_en_bit = YUV422_EN, + .csc_enable_bit = CSC_ENABLE, };
static const struct mtk_dpi_conf mt8192_conf = { @@ -893,6 +899,7 @@ static const struct mtk_dpi_conf mt8192_conf = { .hvsize_mask = HSIZE_MASK, .channel_swap_shift = CH_SWAP, .yuv422_en_bit = YUV422_EN, + .csc_enable_bit = CSC_ENABLE, };
static int mtk_dpi_probe(struct platform_device *pdev)
Dp_intf supports YUV422 as output format. In MT8195 Chrome project, YUV422 output format is used for 4K resolution.
To support this, it is also needed to support color format transfer. Color format transfer is a new feature for both dpi and dpintf of MT8195.
The input format could be RGB888 and output format for dp_intf should be YUV422. Therefore, we add a mtk_dpi_matrix_sel() helper to update the DPI_MATRIX_SET register depending on the color format.
Signed-off-by: Guillaume Ranquet granquet@baylibre.com Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com --- drivers/gpu/drm/mediatek/mtk_dpi.c | 34 ++++++++++++++++++++++++- drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 3 +++ 2 files changed, 36 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 9e4250356342..438bf3bc5e4a 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -128,6 +128,7 @@ struct mtk_dpi_yc_limit { * @num_output_fmts: Quantity of supported output formats. * @is_ck_de_pol: Support CK/DE polarity. * @swap_input_support: Support input swap function. + * @color_fmt_trans_support: Enable color format transfer. * @dimension_mask: Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH * (no shift). * @hvsize_mask: Mask of HSIZE and VSIZE mask (no shift). @@ -144,6 +145,7 @@ struct mtk_dpi_conf { u32 num_output_fmts; bool is_ck_de_pol; bool swap_input_support; + bool color_fmt_trans_support; u32 dimension_mask; u32 hvsize_mask; u32 channel_swap_shift; @@ -412,6 +414,31 @@ static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi) mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN); }
+static void mtk_dpi_matrix_sel(struct mtk_dpi *dpi, + enum mtk_dpi_out_color_format format) +{ + u32 matrix_sel = 0; + + if (!dpi->conf->color_fmt_trans_support) { + dev_info(dpi->dev, "matrix_sel is not supported.\n"); + return; + } + + switch (format) { + case MTK_DPI_COLOR_FORMAT_YCBCR_422: + case MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL: + case MTK_DPI_COLOR_FORMAT_YCBCR_444: + case MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL: + case MTK_DPI_COLOR_FORMAT_XV_YCC: + if (dpi->mode.hdisplay <= 720) + matrix_sel = 0x2; + break; + default: + break; + } + mtk_dpi_mask(dpi, DPI_MATRIX_SET, matrix_sel, INT_MATRIX_SEL_MASK); +} + static void mtk_dpi_config_color_format(struct mtk_dpi *dpi, enum mtk_dpi_out_color_format format) { @@ -419,6 +446,7 @@ static void mtk_dpi_config_color_format(struct mtk_dpi *dpi, (format == MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL)) { mtk_dpi_config_yuv422_enable(dpi, false); mtk_dpi_config_csc_enable(dpi, true); + mtk_dpi_matrix_sel(dpi, format); if (dpi->conf->swap_input_support) mtk_dpi_config_swap_input(dpi, false); mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_BGR); @@ -426,6 +454,7 @@ static void mtk_dpi_config_color_format(struct mtk_dpi *dpi, (format == MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL)) { mtk_dpi_config_yuv422_enable(dpi, true); mtk_dpi_config_csc_enable(dpi, true); + mtk_dpi_matrix_sel(dpi, format); if (dpi->conf->swap_input_support) mtk_dpi_config_swap_input(dpi, true); else @@ -673,7 +702,10 @@ static int mtk_dpi_bridge_atomic_check(struct drm_bridge *bridge, dpi->bit_num = MTK_DPI_OUT_BIT_NUM_8BITS; dpi->channel_swap = MTK_DPI_OUT_CHANNEL_SWAP_RGB; dpi->yc_map = MTK_DPI_OUT_YC_MAP_RGB; - dpi->color_format = MTK_DPI_COLOR_FORMAT_RGB; + if (out_bus_format == MEDIA_BUS_FMT_YUYV8_1X16) + dpi->color_format = MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL; + else + dpi->color_format = MTK_DPI_COLOR_FORMAT_RGB;
return 0; } diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h index 3a02fabe1662..65fce11316b7 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h @@ -217,4 +217,7 @@
#define EDGE_SEL_EN BIT(5) #define H_FRE_2N BIT(25) + +#define DPI_MATRIX_SET 0xB4 +#define INT_MATRIX_SEL_MASK (0x1F << 0) #endif /* __MTK_DPI_REGS_H */
Il 21/06/22 13:37, Bo-Chen Chen ha scritto:
Dp_intf supports YUV422 as output format. In MT8195 Chrome project, YUV422 output format is used for 4K resolution.
To support this, it is also needed to support color format transfer. Color format transfer is a new feature for both dpi and dpintf of MT8195.
The input format could be RGB888 and output format for dp_intf should be YUV422. Therefore, we add a mtk_dpi_matrix_sel() helper to update the DPI_MATRIX_SET register depending on the color format.
Signed-off-by: Guillaume Ranquet granquet@baylibre.com Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com
drivers/gpu/drm/mediatek/mtk_dpi.c | 34 ++++++++++++++++++++++++- drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 3 +++ 2 files changed, 36 insertions(+), 1 deletion(-)
..snip..
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h index 3a02fabe1662..65fce11316b7 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h @@ -217,4 +217,7 @@
#define EDGE_SEL_EN BIT(5) #define H_FRE_2N BIT(25)
+#define DPI_MATRIX_SET 0xB4 +#define INT_MATRIX_SEL_MASK (0x1F << 0)
Please, change INT_MATRIX_SEL_MASK: that's GENMASK(4, 0).
After that,
Reviewed-by: AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com
#endif /* __MTK_DPI_REGS_H */
MediaTek dpi supports direct connection to pins while dp_intf does not support. Therefore, add a config "support_direct_pin" to control this.
Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com --- drivers/gpu/drm/mediatek/mtk_dpi.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 438bf3bc5e4a..ef7f828a4b1e 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -129,6 +129,8 @@ struct mtk_dpi_yc_limit { * @is_ck_de_pol: Support CK/DE polarity. * @swap_input_support: Support input swap function. * @color_fmt_trans_support: Enable color format transfer. + * @support_direct_pin: Dpi can directly connect pins, and enable this config + * to do this. * @dimension_mask: Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH * (no shift). * @hvsize_mask: Mask of HSIZE and VSIZE mask (no shift). @@ -146,6 +148,7 @@ struct mtk_dpi_conf { bool is_ck_de_pol; bool swap_input_support; bool color_fmt_trans_support; + bool support_direct_pin; u32 dimension_mask; u32 hvsize_mask; u32 channel_swap_shift; @@ -619,11 +622,13 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, mtk_dpi_config_channel_limit(dpi); mtk_dpi_config_bit_num(dpi, dpi->bit_num); mtk_dpi_config_channel_swap(dpi, dpi->channel_swap); - mtk_dpi_config_yc_map(dpi, dpi->yc_map); mtk_dpi_config_color_format(dpi, dpi->color_format); - mtk_dpi_config_2n_h_fre(dpi); - mtk_dpi_dual_edge(dpi); - mtk_dpi_config_disable_edge(dpi); + if (dpi->conf->support_direct_pin) { + mtk_dpi_config_yc_map(dpi, dpi->yc_map); + mtk_dpi_config_2n_h_fre(dpi); + mtk_dpi_dual_edge(dpi); + mtk_dpi_config_disable_edge(dpi); + } mtk_dpi_sw_reset(dpi, false);
return 0; @@ -881,6 +886,7 @@ static const struct mtk_dpi_conf mt8173_conf = { .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol = true, .swap_input_support = true, + .support_direct_pin = true, .dimension_mask = HPW_MASK, .hvsize_mask = HSIZE_MASK, .channel_swap_shift = CH_SWAP, @@ -897,6 +903,7 @@ static const struct mtk_dpi_conf mt2701_conf = { .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol = true, .swap_input_support = true, + .support_direct_pin = true, .dimension_mask = HPW_MASK, .hvsize_mask = HSIZE_MASK, .channel_swap_shift = CH_SWAP, @@ -912,6 +919,7 @@ static const struct mtk_dpi_conf mt8183_conf = { .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), .is_ck_de_pol = true, .swap_input_support = true, + .support_direct_pin = true, .dimension_mask = HPW_MASK, .hvsize_mask = HSIZE_MASK, .channel_swap_shift = CH_SWAP, @@ -927,6 +935,7 @@ static const struct mtk_dpi_conf mt8192_conf = { .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), .is_ck_de_pol = true, .swap_input_support = true, + .support_direct_pin = true, .dimension_mask = HPW_MASK, .hvsize_mask = HSIZE_MASK, .channel_swap_shift = CH_SWAP,
Il 21/06/22 13:37, Bo-Chen Chen ha scritto:
MediaTek dpi supports direct connection to pins while dp_intf does not support. Therefore, add a config "support_direct_pin" to control this.
Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com
drivers/gpu/drm/mediatek/mtk_dpi.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 438bf3bc5e4a..ef7f828a4b1e 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -129,6 +129,8 @@ struct mtk_dpi_yc_limit {
- @is_ck_de_pol: Support CK/DE polarity.
- @swap_input_support: Support input swap function.
- @color_fmt_trans_support: Enable color format transfer.
- @support_direct_pin: Dpi can directly connect pins, and enable this config
to do this.
@support_direct_pin: IP supports direct connection to pins
or
@support_direct_pin: IP has direct connection to DP pins
or
@support_direct_pin: IP connects directly to DP pins
pick one, after which:
Reviewed-by: AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com
On Tue, 2022-06-21 at 14:11 +0200, AngeloGioacchino Del Regno wrote:
Il 21/06/22 13:37, Bo-Chen Chen ha scritto:
MediaTek dpi supports direct connection to pins while dp_intf does not support. Therefore, add a config "support_direct_pin" to control this.
Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com
drivers/gpu/drm/mediatek/mtk_dpi.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 438bf3bc5e4a..ef7f828a4b1e 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -129,6 +129,8 @@ struct mtk_dpi_yc_limit {
- @is_ck_de_pol: Support CK/DE polarity.
- @swap_input_support: Support input swap function.
- @color_fmt_trans_support: Enable color format transfer.
- @support_direct_pin: Dpi can directly connect pins, and enable
this config
to do this.@support_direct_pin: IP supports direct connection to pins
or
@support_direct_pin: IP has direct connection to DP pins
or
@support_direct_pin: IP connects directly to DP pins
pick one, after which:
Reviewed-by: AngeloGioacchino Del Regno < angelogioacchino.delregno@collabora.com>
Hello Angelo,
this is not connect to "DP" pin. This setting is for dpi to connect to panel directly and there is no such usecase for dp_intf.
Therefore, I will use "@support_direct_pin: IP supports direct connection to pins".
Thanks
BRs, Bo-Chen
On Wed, 2022-06-22 at 17:08 +0800, Rex-BC Chen wrote:
On Tue, 2022-06-21 at 14:11 +0200, AngeloGioacchino Del Regno wrote:
Il 21/06/22 13:37, Bo-Chen Chen ha scritto:
MediaTek dpi supports direct connection to pins while dp_intf does not support. Therefore, add a config "support_direct_pin" to control this.
Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com
drivers/gpu/drm/mediatek/mtk_dpi.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 438bf3bc5e4a..ef7f828a4b1e 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -129,6 +129,8 @@ struct mtk_dpi_yc_limit {
- @is_ck_de_pol: Support CK/DE polarity.
- @swap_input_support: Support input swap function.
- @color_fmt_trans_support: Enable color format transfer.
- @support_direct_pin: Dpi can directly connect pins, and
enable this config
to do this.@support_direct_pin: IP supports direct connection to pins
or
@support_direct_pin: IP has direct connection to DP pins
or
@support_direct_pin: IP connects directly to DP pins
pick one, after which:
Reviewed-by: AngeloGioacchino Del Regno < angelogioacchino.delregno@collabora.com>
Hello Angelo,
this is not connect to "DP" pin. This setting is for dpi to connect to panel directly and there is no such usecase for dp_intf.
Therefore, I will use "@support_direct_pin: IP supports direct connection to pins".
Thanks
BRs, Bo-Chen
Hello Angelo,
I think "@support_direct_pin: IP supports direct connection to dpi panels" is more precise for this config. I will use this description.
BRs, Bo-Chen
From: Guillaume Ranquet granquet@baylibre.com
Dpintf is the displayport interface hardware unit. This unit is similar to dpi and can reuse most of the code.
This patch adds support for mt8195-dpintf to this dpi driver. Main differences are: - 4 pixels for one round for dp_intf while dpi is 1 pixel for one round. Therefore, we add a new config "round_pixels" to control setting of pixel clock and timing parameter for dp_intf. - Input of dp_intf is two pixels per round, so we add a new config "input_2pixel" to control this. - Some register contents differ slightly between the two components. To work around this I added register bits/masks with a DPINTF_ prefix and use them where different.
Based on a separate driver for dpintf created by Jitao shi jitao.shi@mediatek.com.
Signed-off-by: Markus Schneider-Pargmann msp@baylibre.com Signed-off-by: Guillaume Ranquet granquet@baylibre.com [Bo-Chen: Modify reviewers' comments.] Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com --- drivers/gpu/drm/mediatek/mtk_dpi.c | 62 +++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 12 ++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 4 ++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 + 5 files changed, 82 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index ef7f828a4b1e..e562f0d55cc2 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -131,6 +131,11 @@ struct mtk_dpi_yc_limit { * @color_fmt_trans_support: Enable color format transfer. * @support_direct_pin: Dpi can directly connect pins, and enable this config * to do this. + * @round_pixels: Dp_intf is 4 pixels for one round while dpi is one pixel for + * one round, so we need to enable this config for dp_intf to do + * corresponding settings. + * @input_2pixel: Input pixel of dp_intf is 2 pixel per round, so enable this + * config to enable this feature. * @dimension_mask: Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH * (no shift). * @hvsize_mask: Mask of HSIZE and VSIZE mask (no shift). @@ -149,6 +154,8 @@ struct mtk_dpi_conf { bool swap_input_support; bool color_fmt_trans_support; bool support_direct_pin; + bool round_pixels; + bool input_2pixel; u32 dimension_mask; u32 hvsize_mask; u32 channel_swap_shift; @@ -560,6 +567,14 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, pll_rate = clk_get_rate(dpi->tvd_clk);
vm.pixelclock = pll_rate / factor; + + /* + * For dp_intf, we need to divide clock by 4 because it's + * 4 pixels for one round while dpi is 1 pixel for one round. + */ + if (dpi->conf->round_pixels) + vm.pixelclock /= 4; + if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) || (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE)) clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2); @@ -581,6 +596,17 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, hsync.sync_width = vm.hsync_len; hsync.back_porch = vm.hback_porch; hsync.front_porch = vm.hfront_porch; + + /* + * For dp_intf, we need to divide everything by 4 because it's + * 4 pixels for one round while dpi is 1 pixel for one round. + */ + if (dpi->conf->round_pixels) { + hsync.sync_width = vm.hsync_len / 4; + hsync.back_porch = vm.hback_porch / 4; + hsync.front_porch = vm.hfront_porch / 4; + } + hsync.shift_half_line = false; vsync_lodd.sync_width = vm.vsync_len; vsync_lodd.back_porch = vm.vback_porch; @@ -629,6 +655,10 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, mtk_dpi_dual_edge(dpi); mtk_dpi_config_disable_edge(dpi); } + if (dpi->conf->input_2pixel) { + mtk_dpi_mask(dpi, DPI_CON, DPINTF_INPUT_2P_EN, + DPINTF_INPUT_2P_EN); + } mtk_dpi_sw_reset(dpi, false);
return 0; @@ -869,6 +899,16 @@ static unsigned int mt8183_calculate_factor(int clock) return 2; }
+static unsigned int mt8195_dpintf_calculate_factor(int clock) +{ + if (clock < 70000) + return 4; + else if (clock < 200000) + return 2; + else + return 1; +} + static const u32 mt8173_output_fmts[] = { MEDIA_BUS_FMT_RGB888_1X24, }; @@ -878,6 +918,11 @@ static const u32 mt8183_output_fmts[] = { MEDIA_BUS_FMT_RGB888_2X12_BE, };
+static const u32 mt8195_output_fmts[] = { + MEDIA_BUS_FMT_RGB888_1X24, + MEDIA_BUS_FMT_YUYV8_1X16, +}; + static const struct mtk_dpi_conf mt8173_conf = { .cal_factor = mt8173_calculate_factor, .reg_h_fre_con = 0xe0, @@ -943,6 +988,20 @@ static const struct mtk_dpi_conf mt8192_conf = { .csc_enable_bit = CSC_ENABLE, };
+static const struct mtk_dpi_conf mt8195_dpintf_conf = { + .cal_factor = mt8195_dpintf_calculate_factor, + .max_clock_khz = 600000, + .output_fmts = mt8195_output_fmts, + .num_output_fmts = ARRAY_SIZE(mt8195_output_fmts), + .round_pixels = true, + .input_2pixel = true, + .dimension_mask = DPINTF_HPW_MASK, + .hvsize_mask = DPINTF_HSIZE_MASK, + .channel_swap_shift = DPINTF_CH_SWAP, + .yuv422_en_bit = DPINTF_YUV422_EN, + .csc_enable_bit = DPINTF_CSC_ENABLE, +}; + static int mtk_dpi_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -1065,6 +1124,9 @@ static const struct of_device_id mtk_dpi_of_ids[] = { { .compatible = "mediatek,mt8192-dpi", .data = &mt8192_conf, }, + { .compatible = "mediatek,mt8195-dp-intf", + .data = &mt8195_dpintf_conf, + }, { }, }; MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids); diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h index 65fce11316b7..9e10b9f3b437 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h @@ -40,9 +40,13 @@ #define FAKE_DE_LEVEN BIT(21) #define FAKE_DE_RODD BIT(22) #define FAKE_DE_REVEN BIT(23) +#define DPINTF_YUV422_EN BIT(24) +#define DPINTF_CSC_ENABLE BIT(26) +#define DPINTF_INPUT_2P_EN BIT(29)
#define DPI_OUTPUT_SETTING 0x14 #define CH_SWAP 0 +#define DPINTF_CH_SWAP 1 #define CH_SWAP_MASK (0x7 << 0) #define SWAP_RGB 0x00 #define SWAP_GBR 0x01 @@ -80,8 +84,10 @@ #define DPI_SIZE 0x18 #define HSIZE 0 #define HSIZE_MASK (0x1FFF << 0) +#define DPINTF_HSIZE_MASK (0xFFFF << 0) #define VSIZE 16 #define VSIZE_MASK (0x1FFF << 16) +#define DPINTF_VSIZE_MASK (0xFFFF << 16)
#define DPI_DDR_SETTING 0x1C #define DDR_EN BIT(0) @@ -93,24 +99,30 @@ #define DPI_TGEN_HWIDTH 0x20 #define HPW 0 #define HPW_MASK (0xFFF << 0) +#define DPINTF_HPW_MASK (0xFFFF << 0)
#define DPI_TGEN_HPORCH 0x24 #define HBP 0 #define HBP_MASK (0xFFF << 0) +#define DPINTF_HBP_MASK (0xFFFF << 0) #define HFP 16 #define HFP_MASK (0xFFF << 16) +#define DPINTF_HFP_MASK (0xFFFF << 16)
#define DPI_TGEN_VWIDTH 0x28 #define DPI_TGEN_VPORCH 0x2C
#define VSYNC_WIDTH_SHIFT 0 #define VSYNC_WIDTH_MASK (0xFFF << 0) +#define DPINTF_VSYNC_WIDTH_MASK (0xFFFF << 0) #define VSYNC_HALF_LINE_SHIFT 16 #define VSYNC_HALF_LINE_MASK BIT(16) #define VSYNC_BACK_PORCH_SHIFT 0 #define VSYNC_BACK_PORCH_MASK (0xFFF << 0) +#define DPINTF_VSYNC_BACK_PORCH_MASK (0xFFFF << 0) #define VSYNC_FRONT_PORCH_SHIFT 16 #define VSYNC_FRONT_PORCH_MASK (0xFFF << 16) +#define DPINTF_VSYNC_FRONT_PORCH_MASK (0xFFFF << 16)
#define DPI_BG_HCNTL 0x30 #define BG_RIGHT (0x1FFF << 0) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 2aab1e1eda36..5bef085714a1 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -427,6 +427,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { [MTK_DISP_RDMA] = "rdma", [MTK_DISP_UFOE] = "ufoe", [MTK_DISP_WDMA] = "wdma", + [MTK_DP_INTF] = "dp-intf", [MTK_DPI] = "dpi", [MTK_DSI] = "dsi", }; @@ -450,6 +451,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX] [DDP_COMPONENT_DRM_OVL_ADAPTOR] = { MTK_DISP_OVL_ADAPTOR, 0, &ddp_ovl_adaptor }, [DDP_COMPONENT_DSC0] = { MTK_DISP_DSC, 0, &ddp_dsc }, [DDP_COMPONENT_DSC1] = { MTK_DISP_DSC, 1, &ddp_dsc }, + [DDP_COMPONENT_DP_INTF0] = { MTK_DP_INTF, 0, &ddp_dpi }, + [DDP_COMPONENT_DP_INTF1] = { MTK_DP_INTF, 1, &ddp_dpi }, [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi }, [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi }, [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi }, @@ -575,6 +578,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, type == MTK_DISP_PWM || type == MTK_DISP_RDMA || type == MTK_DPI || + type == MTK_DP_INTF || type == MTK_DSI) return 0;
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index af9a6671f9c4..3084cc4e2830 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -38,6 +38,7 @@ enum mtk_ddp_comp_type { MTK_DISP_UFOE, MTK_DISP_WDMA, MTK_DPI, + MTK_DP_INTF, MTK_DSI, MTK_DDP_COMP_TYPE_MAX, }; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 78e79c8449c8..a7a0dbbca823 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -788,6 +788,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DPI }, { .compatible = "mediatek,mt8192-dpi", .data = (void *)MTK_DPI }, + { .compatible = "mediatek,mt8195-dp-intf", + .data = (void *)MTK_DP_INTF }, { .compatible = "mediatek,mt2701-dsi", .data = (void *)MTK_DSI }, { .compatible = "mediatek,mt8173-dsi", @@ -931,6 +933,7 @@ static int mtk_drm_probe(struct platform_device *pdev) comp_type == MTK_DISP_OVL_2L || comp_type == MTK_DISP_OVL_ADAPTOR || comp_type == MTK_DISP_RDMA || + comp_type == MTK_DP_INTF || comp_type == MTK_DPI || comp_type == MTK_DSI) { dev_info(dev, "Adding component match for %pOF\n",
Il 21/06/22 13:37, Bo-Chen Chen ha scritto:
From: Guillaume Ranquet granquet@baylibre.com
Dpintf is the displayport interface hardware unit. This unit is similar to dpi and can reuse most of the code.
This patch adds support for mt8195-dpintf to this dpi driver. Main differences are:
- 4 pixels for one round for dp_intf while dpi is 1 pixel for one round. Therefore, we add a new config "round_pixels" to control setting of
Okay, I like where this is going, but "round_pixels" explains itself like "the pixels are round" (which doesn't make sense).
So... is this "4 pixels per iteration" (computation of 4 pixels per iteration), or "outputs 4 pixels at a time"? I can give you some ideas about a better name for this struct member, I think... ...something like "output_4pixel"?
Alternatively, we can do something even cleaner here: u8 pixels_per_round;
...where we define it like...
static const struct mtk_dpi_conf mt8195_dpintf_conf = { .pixels_per_round = 4, .......... }
static const struct mtk_dpi_conf mt8192_conf = { .pixels_per_round = 1, ......... }
... and then, in function mtk_dpi_set_display_mode(), we would have something like
/*
* Depending on the IP version, we may output a different amount
* of pixels for each (choose: round/iteration): divide the clock
* by this number and adjust the display porches accordingly.
*/
vm.pixelclock = pll_rate / factor;
vm.pixelclock /= dpi->conf->pixels_per_round;
......
hsync.sync_width = vm.hsync_len / dpi->conf->pixels_per_round;
hsync.back_porch = vm.hback_porch / dpi->conf->pixels_per_round;
hsync.front_porch = vm.hfront_porch / dpi->conf->pixels_per_round;
This would also eliminate any need to check if the IP has 4 pixels per round or if it has just 1, as in the latter case, we'd be dividing by 1 (hence, we would not be dividing anything).
Do you like this solution? :-)
Cheers, Angelo
pixel clock and timing parameter for dp_intf.
- Input of dp_intf is two pixels per round, so we add a new config "input_2pixel" to control this.
- Some register contents differ slightly between the two components. To work around this I added register bits/masks with a DPINTF_ prefix and use them where different.
Based on a separate driver for dpintf created by Jitao shi jitao.shi@mediatek.com.
Signed-off-by: Markus Schneider-Pargmann msp@baylibre.com Signed-off-by: Guillaume Ranquet granquet@baylibre.com [Bo-Chen: Modify reviewers' comments.] Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com
drivers/gpu/drm/mediatek/mtk_dpi.c | 62 +++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 12 ++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 4 ++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 + 5 files changed, 82 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index ef7f828a4b1e..e562f0d55cc2 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -131,6 +131,11 @@ struct mtk_dpi_yc_limit {
- @color_fmt_trans_support: Enable color format transfer.
- @support_direct_pin: Dpi can directly connect pins, and enable this config
to do this.
- @round_pixels: Dp_intf is 4 pixels for one round while dpi is one pixel for
one round, so we need to enable this config for dp_intf to do
corresponding settings.
- @input_2pixel: Input pixel of dp_intf is 2 pixel per round, so enable this
config to enable this feature.- @dimension_mask: Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH
(no shift).- @hvsize_mask: Mask of HSIZE and VSIZE mask (no shift).
@@ -149,6 +154,8 @@ struct mtk_dpi_conf { bool swap_input_support; bool color_fmt_trans_support; bool support_direct_pin;
- bool round_pixels;
- bool input_2pixel; u32 dimension_mask; u32 hvsize_mask; u32 channel_swap_shift;
@@ -560,6 +567,14 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, pll_rate = clk_get_rate(dpi->tvd_clk);
vm.pixelclock = pll_rate / factor;
- /*
* For dp_intf, we need to divide clock by 4 because it's* 4 pixels for one round while dpi is 1 pixel for one round.*/- if (dpi->conf->round_pixels)
vm.pixelclock /= 4;- if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) || (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE)) clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2);
@@ -581,6 +596,17 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, hsync.sync_width = vm.hsync_len; hsync.back_porch = vm.hback_porch; hsync.front_porch = vm.hfront_porch;
- /*
* For dp_intf, we need to divide everything by 4 because it's* 4 pixels for one round while dpi is 1 pixel for one round.*/- if (dpi->conf->round_pixels) {
hsync.sync_width = vm.hsync_len / 4;hsync.back_porch = vm.hback_porch / 4;hsync.front_porch = vm.hfront_porch / 4;- }
- hsync.shift_half_line = false; vsync_lodd.sync_width = vm.vsync_len; vsync_lodd.back_porch = vm.vback_porch;
@@ -629,6 +655,10 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, mtk_dpi_dual_edge(dpi); mtk_dpi_config_disable_edge(dpi); }
if (dpi->conf->input_2pixel) {
mtk_dpi_mask(dpi, DPI_CON, DPINTF_INPUT_2P_EN,DPINTF_INPUT_2P_EN);} mtk_dpi_sw_reset(dpi, false);
return 0;
@@ -869,6 +899,16 @@ static unsigned int mt8183_calculate_factor(int clock) return 2; }
+static unsigned int mt8195_dpintf_calculate_factor(int clock) +{
- if (clock < 70000)
return 4;- else if (clock < 200000)
return 2;- else
return 1;+}
- static const u32 mt8173_output_fmts[] = { MEDIA_BUS_FMT_RGB888_1X24, };
@@ -878,6 +918,11 @@ static const u32 mt8183_output_fmts[] = { MEDIA_BUS_FMT_RGB888_2X12_BE, };
+static const u32 mt8195_output_fmts[] = {
- MEDIA_BUS_FMT_RGB888_1X24,
- MEDIA_BUS_FMT_YUYV8_1X16,
+};
- static const struct mtk_dpi_conf mt8173_conf = { .cal_factor = mt8173_calculate_factor, .reg_h_fre_con = 0xe0,
@@ -943,6 +988,20 @@ static const struct mtk_dpi_conf mt8192_conf = { .csc_enable_bit = CSC_ENABLE, };
+static const struct mtk_dpi_conf mt8195_dpintf_conf = {
- .cal_factor = mt8195_dpintf_calculate_factor,
- .max_clock_khz = 600000,
- .output_fmts = mt8195_output_fmts,
- .num_output_fmts = ARRAY_SIZE(mt8195_output_fmts),
- .round_pixels = true,
- .input_2pixel = true,
- .dimension_mask = DPINTF_HPW_MASK,
- .hvsize_mask = DPINTF_HSIZE_MASK,
- .channel_swap_shift = DPINTF_CH_SWAP,
- .yuv422_en_bit = DPINTF_YUV422_EN,
- .csc_enable_bit = DPINTF_CSC_ENABLE,
+};
- static int mtk_dpi_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev;
@@ -1065,6 +1124,9 @@ static const struct of_device_id mtk_dpi_of_ids[] = { { .compatible = "mediatek,mt8192-dpi", .data = &mt8192_conf, },
- { .compatible = "mediatek,mt8195-dp-intf",
.data = &mt8195_dpintf_conf,- }, { }, }; MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids);
On Tue, 2022-06-21 at 14:11 +0200, AngeloGioacchino Del Regno wrote:
Il 21/06/22 13:37, Bo-Chen Chen ha scritto:
From: Guillaume Ranquet granquet@baylibre.com
Dpintf is the displayport interface hardware unit. This unit is similar to dpi and can reuse most of the code.
This patch adds support for mt8195-dpintf to this dpi driver. Main differences are:
- 4 pixels for one round for dp_intf while dpi is 1 pixel for one
round. Therefore, we add a new config "round_pixels" to control setting of
Okay, I like where this is going, but "round_pixels" explains itself like "the pixels are round" (which doesn't make sense).
So... is this "4 pixels per iteration" (computation of 4 pixels per iteration), or "outputs 4 pixels at a time"? I can give you some ideas about a better name for this struct member, I think... ...something like "output_4pixel"?
Alternatively, we can do something even cleaner here: u8 pixels_per_round;
...where we define it like...
static const struct mtk_dpi_conf mt8195_dpintf_conf = { .pixels_per_round = 4, .......... }
static const struct mtk_dpi_conf mt8192_conf = { .pixels_per_round = 1, ......... }
... and then, in function mtk_dpi_set_display_mode(), we would have something like
/*
* Depending on the IP version, we may output a differentamount
* of pixels for each (choose: round/iteration): divide theclock
* by this number and adjust the display porches accordingly. */ vm.pixelclock = pll_rate / factor;vm.pixelclock /= dpi->conf->pixels_per_round;
......
hsync.sync_width = vm.hsync_len / dpi->conf->pixels_per_round; hsync.back_porch = vm.hback_porch / dpi->conf-pixels_per_round;
hsync.front_porch = vm.hfront_porch / dpi->conf-pixels_per_round;
This would also eliminate any need to check if the IP has 4 pixels per round or if it has just 1, as in the latter case, we'd be dividing by 1 (hence, we would not be dividing anything).
Do you like this solution? :-)
Cheers, Angelo
Hello Angelo,
Thanks for the advise! After syncing with CK, I will use mothod of "pixels_per_round". This soultion is pretty good and more clear for this config.
Thanks again!
BRs, Bo-Chen
pixel clock and timing parameter for dp_intf.
- Input of dp_intf is two pixels per round, so we add a new
config "input_2pixel" to control this.
- Some register contents differ slightly between the two
components. To work around this I added register bits/masks with a DPINTF_ prefix and use them where different.
Based on a separate driver for dpintf created by Jitao shi jitao.shi@mediatek.com.
Signed-off-by: Markus Schneider-Pargmann msp@baylibre.com Signed-off-by: Guillaume Ranquet granquet@baylibre.com [Bo-Chen: Modify reviewers' comments.] Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com
drivers/gpu/drm/mediatek/mtk_dpi.c | 62 +++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 12 ++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 4 ++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 + 5 files changed, 82 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index ef7f828a4b1e..e562f0d55cc2 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -131,6 +131,11 @@ struct mtk_dpi_yc_limit {
- @color_fmt_trans_support: Enable color format transfer.
- @support_direct_pin: Dpi can directly connect pins, and enable
this config
to do this.
- @round_pixels: Dp_intf is 4 pixels for one round while dpi is
one pixel for
one round, so we need to enable this config fordp_intf to do
corresponding settings.
- @input_2pixel: Input pixel of dp_intf is 2 pixel per round, so
enable this
config to enable this feature.- @dimension_mask: Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and
VSYNC_PORCH
(no shift).- @hvsize_mask: Mask of HSIZE and VSIZE mask (no shift).
@@ -149,6 +154,8 @@ struct mtk_dpi_conf { bool swap_input_support; bool color_fmt_trans_support; bool support_direct_pin;
- bool round_pixels;
- bool input_2pixel; u32 dimension_mask; u32 hvsize_mask; u32 channel_swap_shift;
@@ -560,6 +567,14 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, pll_rate = clk_get_rate(dpi->tvd_clk);
vm.pixelclock = pll_rate / factor;
- /*
* For dp_intf, we need to divide clock by 4 because it's* 4 pixels for one round while dpi is 1 pixel for one round.*/- if (dpi->conf->round_pixels)
vm.pixelclock /= 4;- if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) || (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE)) clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2);
@@ -581,6 +596,17 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, hsync.sync_width = vm.hsync_len; hsync.back_porch = vm.hback_porch; hsync.front_porch = vm.hfront_porch;
- /*
* For dp_intf, we need to divide everything by 4 because it's* 4 pixels for one round while dpi is 1 pixel for one round.*/- if (dpi->conf->round_pixels) {
hsync.sync_width = vm.hsync_len / 4;hsync.back_porch = vm.hback_porch / 4;hsync.front_porch = vm.hfront_porch / 4;- }
- hsync.shift_half_line = false; vsync_lodd.sync_width = vm.vsync_len; vsync_lodd.back_porch = vm.vback_porch;
@@ -629,6 +655,10 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, mtk_dpi_dual_edge(dpi); mtk_dpi_config_disable_edge(dpi); }
if (dpi->conf->input_2pixel) {
mtk_dpi_mask(dpi, DPI_CON, DPINTF_INPUT_2P_EN,DPINTF_INPUT_2P_EN);} mtk_dpi_sw_reset(dpi, false);
return 0;
@@ -869,6 +899,16 @@ static unsigned int mt8183_calculate_factor(int clock) return 2; }
+static unsigned int mt8195_dpintf_calculate_factor(int clock) +{
- if (clock < 70000)
return 4;- else if (clock < 200000)
return 2;- else
return 1;+}
- static const u32 mt8173_output_fmts[] = { MEDIA_BUS_FMT_RGB888_1X24, };
@@ -878,6 +918,11 @@ static const u32 mt8183_output_fmts[] = { MEDIA_BUS_FMT_RGB888_2X12_BE, };
+static const u32 mt8195_output_fmts[] = {
- MEDIA_BUS_FMT_RGB888_1X24,
- MEDIA_BUS_FMT_YUYV8_1X16,
+};
- static const struct mtk_dpi_conf mt8173_conf = { .cal_factor = mt8173_calculate_factor, .reg_h_fre_con = 0xe0,
@@ -943,6 +988,20 @@ static const struct mtk_dpi_conf mt8192_conf = { .csc_enable_bit = CSC_ENABLE, };
+static const struct mtk_dpi_conf mt8195_dpintf_conf = {
- .cal_factor = mt8195_dpintf_calculate_factor,
- .max_clock_khz = 600000,
- .output_fmts = mt8195_output_fmts,
- .num_output_fmts = ARRAY_SIZE(mt8195_output_fmts),
- .round_pixels = true,
- .input_2pixel = true,
- .dimension_mask = DPINTF_HPW_MASK,
- .hvsize_mask = DPINTF_HSIZE_MASK,
- .channel_swap_shift = DPINTF_CH_SWAP,
- .yuv422_en_bit = DPINTF_YUV422_EN,
- .csc_enable_bit = DPINTF_CSC_ENABLE,
+};
- static int mtk_dpi_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev;
@@ -1065,6 +1124,9 @@ static const struct of_device_id mtk_dpi_of_ids[] = { { .compatible = "mediatek,mt8192-dpi", .data = &mt8192_conf, },
- { .compatible = "mediatek,mt8195-dp-intf",
.data = &mt8195_dpintf_conf,- }, { }, }; MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids);
From: Guillaume Ranquet granquet@baylibre.com
Enabling the dpi too early causes glitches on screen.
Move the call to mtk_dpi_enable() at the end of the bridge_enable callback to ensure everything is setup properly before enabling dpi.
Fixes: 9e629c17aa8d ("drm/mediatek: Add DPI sub driver") Signed-off-by: Guillaume Ranquet granquet@baylibre.com Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com --- drivers/gpu/drm/mediatek/mtk_dpi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index e562f0d55cc2..83841d5efb3e 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -532,7 +532,6 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) if (dpi->pinctrl && dpi->pins_dpi) pinctrl_select_state(dpi->pinctrl, dpi->pins_dpi);
- mtk_dpi_enable(dpi); return 0;
err_pixel: @@ -776,6 +775,7 @@ static void mtk_dpi_bridge_enable(struct drm_bridge *bridge)
mtk_dpi_power_on(dpi); mtk_dpi_set_display_mode(dpi, &dpi->mode); + mtk_dpi_enable(dpi); }
static enum drm_mode_status
dri-devel@lists.freedesktop.org
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AngeloGioacchino Del Regno -
Bo-Chen Chen -
CK Hu -
Rex-BC Chen