From: Rahul Sharma Rahul.Sharma@samsung.com
Changelog: v4: * Rename files to follow "phy-exynos-simple" names. * Rename Macros to this convention PHY_EXYNOS_SIMPLE_XXXX. * Added list of phy specifier values to documentation file. * Removed of_match_ptr from driver probe. * Moved unrelated MACROs to driver file from header file.
v3: * Implement lazy-init of PHYs. * Use MACROs instead of numbers to represent phys. * Use regmap interface to access PMU registers.
It is based on "Next" branch in Kishon Vijay Abraham's tree at https://git.kernel.org/cgit/linux/kernel/git/kishon/linux-phy.git/
/* Original Message from Tomasz Stanislawski t.stanislaws@samsung.com */
The Samsung SoCs from Exynos family are enhanced with a bunch of devices that provide functionality of a physical layer for interfaces like USB, HDMI, SATA, etc. They are controlled by a simple interface, often a single bit that enables and/or resets the physical layer.
An IP driver should to control such a controller in an abstract manner. Therefore, such 'enablers' were implemented as clocks in older versions of Linux kernel. With the dawn of PHY subsystems, PHYs become a natural way of exporting the 'enabler' functionality to drivers. However, there is an unexpected consequence. Some of those 1-bit PHYs were implemented as separate drivers. This means that one has to create a struct device, struct phy, its phy provider and 100-150 lines of driver code to basically set one bit.
The DP phy driver is a good example: https://lkml.org/lkml/2013/7/18/53
And simple-phy RFC (shares only driver code but not other resources): https://lkml.org/lkml/2013/10/21/313
To avoid waste of resources I propose to create all such 1-bit phys from Exynos SoC using a single device, driver and phy provider.
This patchset contains a proposed solution.
All comment are welcome.
Hopefully in future the functionality introduced by this patch may be merged into a larger Power Management Unit (PMU) gluer driver. On Samsusng SoC , the PMU part contains a number of register barely linked to power management (like clock gating, clock dividers, CPU resetting, etc.). It may be tempting to create a hybrid driver that export clocks/phys/etc that are controlled by PMU unit.
Alternative solutions might be: * exporting a regmap to the IP driver and allow the driver to control the PHY layer like in the patch: http://thread.gmane.org/gmane.linux.kernel.samsung-soc/28617/focus=28648
* create a dedicated power domain for hdmiphy
Regards, Tomasz Stanislawski
v2: * rename to exynos-simple-phy * fix usage of devm_ioremap() * add documentation for DT bindings * add patches to client drivers
v1: initial version
Tomasz Stanislawski (3): phy: Add exynos-simple-phy driver drm: exynos: hdmi: use hdmiphy as PHY s5p-tv: hdmi: use hdmiphy as PHY
.../devicetree/bindings/phy/samsung-phy.txt | 57 ++++++ drivers/gpu/drm/exynos/exynos_hdmi.c | 11 +- drivers/media/platform/s5p-tv/hdmi_drv.c | 11 +- drivers/phy/Kconfig | 5 + drivers/phy/Makefile | 1 + drivers/phy/phy-exynos-simple.c | 189 ++++++++++++++++++++ include/dt-bindings/phy/phy-exynos-simple.h | 22 +++ 7 files changed, 286 insertions(+), 10 deletions(-) create mode 100644 drivers/phy/phy-exynos-simple.c create mode 100644 include/dt-bindings/phy/phy-exynos-simple.h
From: Tomasz Stanislawski t.stanislaws@samsung.com
Add exynos-simple-phy driver to support a single register PHY interfaces present on Exynos4 SoC.
Signed-off-by: Tomasz Stanislawski t.stanislaws@samsung.com Signed-off-by: Rahul Sharma Rahul.Sharma@samsung.com
--- .../devicetree/bindings/phy/samsung-phy.txt | 57 ++++++ drivers/phy/Kconfig | 5 + drivers/phy/Makefile | 1 + drivers/phy/phy-exynos-simple.c | 189 ++++++++++++++++++++ include/dt-bindings/phy/phy-exynos-simple.h | 22 +++ 5 files changed, 274 insertions(+) create mode 100644 drivers/phy/phy-exynos-simple.c create mode 100644 include/dt-bindings/phy/phy-exynos-simple.h
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt index 2049261..a8d95d6 100644 --- a/Documentation/devicetree/bindings/phy/samsung-phy.txt +++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt @@ -161,3 +161,60 @@ Example: usbdrdphy0 = &usb3_phy0; usbdrdphy1 = &usb3_phy1; }; + +Samsung S5P/EXYNOS SoC series SIMPLE PHY +------------------------------------------------- + +Required properties: +- compatible : should be one of the listed compatibles: + - "samsung,exynos4210-simple-phy" + - "samsung,exynos4412-simple-phy" + - "samsung,exynos5250-simple-phy" + - "samsung,exynos5420-simple-phy" +- samsung,pmureg-phandle - handle to syscon to control PMU registers +- #phy-cells : from the generic phy bindings, must be 1; + +For a compatible PHY, the single cell specifier should be one of these +listed values: + + PHY_EXYNOS_SIMPLE_HDMI 0 + PHY_EXYNOS_SIMPLE_DAC 1 + PHY_EXYNOS_SIMPLE_ADC 2 + PHY_EXYNOS_SIMPLE_PCIE 3 + PHY_EXYNOS_SIMPLE_SATA 4 + +List of supported PHYs for compatible "samsung,exynos4210-simple-phy" are: + PHY_EXYNOS_SIMPLE_HDMI, + PHY_EXYNOS_SIMPLE_DAC, + PHY_EXYNOS_SIMPLE_ADC, + PHY_EXYNOS_SIMPLE_PCIE, + PHY_EXYNOS_SIMPLE_SATA. + +List of supported PHYs for compatible "samsung,exynos4412-simple-phy" are: + PHY_EXYNOS_SIMPLE_HDMI, + PHY_EXYNOS_SIMPLE_ADC. + +List of supported PHYs for compatible "samsung,exynos5250-simple-phy" are: + PHY_EXYNOS_SIMPLE_HDMI, + PHY_EXYNOS_SIMPLE_ADC, + PHY_EXYNOS_SIMPLE_SATA. + +List of supported PHYs for compatible "samsung,exynos5420-simple-phy" are: + PHY_EXYNOS_SIMPLE_HDMI, + PHY_EXYNOS_SIMPLE_ADC. + +Example: +Simple PHY provider node: + + simplephys: simple-phys { + compatible = "samsung,exynos5250-simple-phy"; + samsung,pmu-syscon = <&pmu_system_controller>; + #phy-cells = <1>; + }; + +Other nodes accessing simple PHYs: + + hdmi { + phys = <&simplephys PHY_EXYNOS_SIMPLE_HDMI>; + phy-names = "hdmiphy"; + }; diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 16a2f06..c306ff2 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -178,4 +178,9 @@ config PHY_XGENE help This option enables support for APM X-Gene SoC multi-purpose PHY.
+config PHY_EXYNOS_SIMPLE + tristate "Exynos Simple PHY driver" + help + Support for 1-bit PHY controllers on SoCs from Exynos family. + endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index b4f1d57..cdf0b65 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_GENERIC_PHY) += phy-core.o obj-$(CONFIG_BCM_KONA_USB2_PHY) += phy-bcm-kona-usb2.o obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o +obj-$(CONFIG_PHY_EXYNOS_SIMPLE) += phy-exynos-simple.o obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o obj-$(CONFIG_OMAP_CONTROL_PHY) += phy-omap-control.o obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o diff --git a/drivers/phy/phy-exynos-simple.c b/drivers/phy/phy-exynos-simple.c new file mode 100644 index 0000000..77fc3f7 --- /dev/null +++ b/drivers/phy/phy-exynos-simple.c @@ -0,0 +1,189 @@ +/* + * Exynos Simple PHY driver + * + * Copyright (C) 2013 Samsung Electronics Co., Ltd. + * Author: Tomasz Stanislawski t.stanislaws@samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/phy/phy.h> +#include <linux/mfd/syscon.h> +#include <linux/regmap.h> + +#include <dt-bindings/phy/phy-exynos-simple.h> + +#define EXYNOS_PHY_ENABLE (1 << 0) +#define INVALID (~1) +#define PHY_NR 5 + +struct phy_driver_priv { + struct phy *phys[PHY_NR]; + struct regmap *pmureg; + u32 offsets[PHY_NR]; +}; + +struct phy_driver_data { + u32 index; + u32 offset; +}; + +struct phy_private { + struct regmap *pmureg; + u32 offset; +}; + +static int exynos_phy_power_on(struct phy *phy) +{ + struct phy_private *phy_private = phy_get_drvdata(phy); + + return regmap_update_bits(phy_private->pmureg, phy_private->offset, + EXYNOS_PHY_ENABLE, 1); +} + +static int exynos_phy_power_off(struct phy *phy) +{ + struct phy_private *phy_private = phy_get_drvdata(phy); + + return regmap_update_bits(phy_private->pmureg, phy_private->offset, + EXYNOS_PHY_ENABLE, 0); +} + +static struct phy_ops exynos_phy_ops = { + .power_on = exynos_phy_power_on, + .power_off = exynos_phy_power_off, + .owner = THIS_MODULE, +}; + +static const struct phy_driver_data exynos4210_offsets[] = { + { PHY_EXYNOS_SIMPLE_HDMI, 0x0700 }, /* HDMI_PHY */ + { PHY_EXYNOS_SIMPLE_DAC, 0x070C }, /* DAC_PHY */ + { PHY_EXYNOS_SIMPLE_ADC, 0x0718 }, /* ADC_PHY */ + { PHY_EXYNOS_SIMPLE_PCIE, 0x071C }, /* PCIE_PHY */ + { PHY_EXYNOS_SIMPLE_SATA, 0x0720 }, /* SATA_PHY */ + { INVALID, 0 }, /* End Mark */ +}; + +static const struct phy_driver_data exynos4412_offsets[] = { + { PHY_EXYNOS_SIMPLE_HDMI, 0x0700 }, /* HDMI_PHY */ + { PHY_EXYNOS_SIMPLE_ADC, 0x0718 }, /* ADC_PHY */ + { INVALID, 0 }, /* End Mark */ +}; + +static const struct phy_driver_data exynos5250_offsets[] = { + { PHY_EXYNOS_SIMPLE_HDMI, 0x0700 }, /* HDMI_PHY */ + { PHY_EXYNOS_SIMPLE_ADC, 0x0718 }, /* ADC_PHY */ + { PHY_EXYNOS_SIMPLE_SATA, 0x0724 }, /* SATA_PHY */ + { INVALID, 0 }, /* End Mark */ +}; + +static const struct phy_driver_data exynos5420_offsets[] = { + { PHY_EXYNOS_SIMPLE_HDMI, 0x0700 }, /* HDMI_PHY */ + { PHY_EXYNOS_SIMPLE_ADC, 0x0720 }, /* ADC_PHY */ + { INVALID, 0 }, /* End Mark */ +}; + +static const struct of_device_id exynos_phy_of_match[] = { + { .compatible = "samsung,exynos4210-simple-phy", + .data = exynos4210_offsets}, + { .compatible = "samsung,exynos4412-simple-phy", + .data = exynos4412_offsets}, + { .compatible = "samsung,exynos5250-simple-phy", + .data = exynos5250_offsets}, + { .compatible = "samsung,exynos5420-simple-phy", + .data = exynos5420_offsets}, + { }, +}; +MODULE_DEVICE_TABLE(of, exynos_phy_of_match); + +static struct phy *exynos_phy_xlate(struct device *dev, + struct of_phandle_args *args) +{ + struct phy_driver_priv *priv = dev_get_drvdata(dev); + struct phy_private *phy_private; + int index = args->args[0]; + + /* verify if index and corresponding offset are valid */ + if (index >= PHY_NR || priv->offsets[index] == INVALID) + return ERR_PTR(-ENODEV); + + /* return phy if already allocated */ + if (!IS_ERR_OR_NULL(priv->phys[index])) + return priv->phys[index]; + + priv->phys[index] = devm_phy_create(dev, &exynos_phy_ops, NULL); + if (IS_ERR(priv->phys[index])) { + dev_err(dev, "failed to create PHY %d\n", index); + return priv->phys[index]; + } + + phy_private = devm_kzalloc(dev, sizeof(*phy_private), GFP_KERNEL); + if (!phy_private) + return ERR_PTR(-ENOMEM); + + phy_private->pmureg = priv->pmureg; + phy_private->offset = priv->offsets[index]; + phy_set_drvdata(priv->phys[index], phy_private); + + return priv->phys[index]; +} + +static int exynos_phy_probe(struct platform_device *pdev) +{ + const struct of_device_id *of_id = of_match_device( + exynos_phy_of_match, &pdev->dev); + const struct phy_driver_data *drv_data = of_id->data; + struct device *dev = &pdev->dev; + struct phy_driver_priv *priv; + struct phy_provider *phy_provider; + int i; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + dev_set_drvdata(dev, priv); + + priv->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node, + "samsung,pmu-syscon"); + if (IS_ERR(priv->pmureg)) { + dev_err(dev, "Failed to map PMU register (via syscon)\n"); + return PTR_ERR(priv->pmureg); + } + + /* make all offsets invalid */ + for (i = 0; i < PHY_NR; i++) + priv->offsets[i] = INVALID; + + /* initialize offsets only if available in drv data */ + for (i = 0; drv_data[i].index != INVALID; i++) + priv->offsets[drv_data[i].index] = drv_data[i].offset; + + phy_provider = devm_of_phy_provider_register(dev, exynos_phy_xlate); + if (IS_ERR(phy_provider)) { + dev_err(dev, "failed to register PHY provider\n"); + return PTR_ERR(phy_provider); + } + + return 0; +} + +static struct platform_driver exynos_phy_driver = { + .probe = exynos_phy_probe, + .driver = { + .of_match_table = exynos_phy_of_match, + .name = "exynos-simple-phy", + .owner = THIS_MODULE, + } +}; +module_platform_driver(exynos_phy_driver); + +MODULE_DESCRIPTION("Exynos Simple PHY driver"); +MODULE_AUTHOR("Tomasz Stanislawski t.stanislaws@samsung.com"); +MODULE_LICENSE("GPL v2"); diff --git a/include/dt-bindings/phy/phy-exynos-simple.h b/include/dt-bindings/phy/phy-exynos-simple.h new file mode 100644 index 0000000..0b7ae14 --- /dev/null +++ b/include/dt-bindings/phy/phy-exynos-simple.h @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2013 Samsung Electronics Co., Ltd. + * Author: Tomasz Stanislawski t.stanislaws@samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Device Tree binding constants for Exynos Simple PHY driver + * + */ + +#ifndef _DT_BINDINGS_PHY_EXYNOS_SIMPLE_PHY_H +#define _DT_BINDINGS_PHY_EXYNOS_SIMPLE_PHY_H + +#define PHY_EXYNOS_SIMPLE_HDMI 0 +#define PHY_EXYNOS_SIMPLE_DAC 1 +#define PHY_EXYNOS_SIMPLE_ADC 2 +#define PHY_EXYNOS_SIMPLE_PCIE 3 +#define PHY_EXYNOS_SIMPLE_SATA 4 + +#endif
From: Tomasz Stanislawski t.stanislaws@samsung.com
The HDMIPHY (physical interface) is controlled by a single bit in a power controller's regiter. It was implemented as clock. It was a simple but effective hack.
This patch makes HDMI driver to control HDMIPHY via PHY interface.
Signed-off-by: Tomasz Stanislawski t.stanislaws@samsung.com Signed-off-by: Rahul Sharma Rahul.Sharma@samsung.com --- drivers/gpu/drm/exynos/exynos_hdmi.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c index 9a6d652..ef1cdd0 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c @@ -36,6 +36,7 @@ #include <linux/i2c.h> #include <linux/of_gpio.h> #include <linux/hdmi.h> +#include <linux/phy/phy.h>
#include <drm/exynos_drm.h>
@@ -74,8 +75,8 @@ struct hdmi_resources { struct clk *sclk_hdmi; struct clk *sclk_pixel; struct clk *sclk_hdmiphy; - struct clk *hdmiphy; struct clk *mout_hdmi; + struct phy *hdmiphy; struct regulator_bulk_data *regul_bulk; int regul_count; }; @@ -1854,7 +1855,7 @@ static void hdmi_poweron(struct exynos_drm_display *display) if (regulator_bulk_enable(res->regul_count, res->regul_bulk)) DRM_DEBUG_KMS("failed to enable regulator bulk\n");
- clk_prepare_enable(res->hdmiphy); + phy_power_on(res->hdmiphy); clk_prepare_enable(res->hdmi); clk_prepare_enable(res->sclk_hdmi);
@@ -1881,7 +1882,7 @@ static void hdmi_poweroff(struct exynos_drm_display *display)
clk_disable_unprepare(res->sclk_hdmi); clk_disable_unprepare(res->hdmi); - clk_disable_unprepare(res->hdmiphy); + phy_power_off(res->hdmiphy); regulator_bulk_disable(res->regul_count, res->regul_bulk);
pm_runtime_put_sync(hdata->dev); @@ -1977,9 +1978,9 @@ static int hdmi_resources_init(struct hdmi_context *hdata) DRM_ERROR("failed to get clock 'sclk_hdmiphy'\n"); goto fail; } - res->hdmiphy = devm_clk_get(dev, "hdmiphy"); + res->hdmiphy = devm_phy_get(dev, "hdmiphy"); if (IS_ERR(res->hdmiphy)) { - DRM_ERROR("failed to get clock 'hdmiphy'\n"); + DRM_ERROR("failed to get phy 'hdmiphy'\n"); goto fail; } res->mout_hdmi = devm_clk_get(dev, "mout_hdmi");
From: Tomasz Stanislawski t.stanislaws@samsung.com
The HDMIPHY (physical interface) is controlled by a single bit in a power controller's regiter. It was implemented as clock. It was a simple but effective hack.
This patch makes S5P-HDMI driver to control HDMIPHY via PHY interface.
Signed-off-by: Tomasz Stanislawski t.stanislaws@samsung.com Signed-off-by: Rahul Sharma Rahul.Sharma@samsung.com --- drivers/media/platform/s5p-tv/hdmi_drv.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/media/platform/s5p-tv/hdmi_drv.c b/drivers/media/platform/s5p-tv/hdmi_drv.c index 534722c..8013e52 100644 --- a/drivers/media/platform/s5p-tv/hdmi_drv.c +++ b/drivers/media/platform/s5p-tv/hdmi_drv.c @@ -32,6 +32,7 @@ #include <linux/clk.h> #include <linux/regulator/consumer.h> #include <linux/v4l2-dv-timings.h> +#include <linux/phy/phy.h>
#include <media/s5p_hdmi.h> #include <media/v4l2-common.h> @@ -66,7 +67,7 @@ struct hdmi_resources { struct clk *sclk_hdmi; struct clk *sclk_pixel; struct clk *sclk_hdmiphy; - struct clk *hdmiphy; + struct phy *hdmiphy; struct regulator_bulk_data *regul_bulk; int regul_count; }; @@ -586,7 +587,7 @@ static int hdmi_resource_poweron(struct hdmi_resources *res) if (ret < 0) return ret; /* power-on hdmi physical interface */ - clk_enable(res->hdmiphy); + phy_power_on(res->hdmiphy); /* use VPP as parent clock; HDMIPHY is not working yet */ clk_set_parent(res->sclk_hdmi, res->sclk_pixel); /* turn clocks on */ @@ -600,7 +601,7 @@ static void hdmi_resource_poweroff(struct hdmi_resources *res) /* turn clocks off */ clk_disable(res->sclk_hdmi); /* power-off hdmiphy */ - clk_disable(res->hdmiphy); + phy_power_off(res->hdmiphy); /* turn HDMI power off */ regulator_bulk_disable(res->regul_count, res->regul_bulk); } @@ -784,7 +785,7 @@ static void hdmi_resources_cleanup(struct hdmi_device *hdev) /* kfree is NULL-safe */ kfree(res->regul_bulk); if (!IS_ERR(res->hdmiphy)) - clk_put(res->hdmiphy); + phy_put(res->hdmiphy); if (!IS_ERR(res->sclk_hdmiphy)) clk_put(res->sclk_hdmiphy); if (!IS_ERR(res->sclk_pixel)) @@ -835,7 +836,7 @@ static int hdmi_resources_init(struct hdmi_device *hdev) dev_err(dev, "failed to get clock 'sclk_hdmiphy'\n"); goto fail; } - res->hdmiphy = clk_get(dev, "hdmiphy"); + res->hdmiphy = phy_get(dev, "hdmiphy"); if (IS_ERR(res->hdmiphy)) { dev_err(dev, "failed to get clock 'hdmiphy'\n"); goto fail;
dri-devel@lists.freedesktop.org
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Rahul Sharma