Hello,
This patch series adds support for the DU found in the R8A7793 and R8A7794 SoCs. It mostly consists of DT bindings updates (1/5 and 2/5) with a small driver change in 2/5 to support fixed RGB output routing. Patches 4/5 and 5/5 then add DU nodes to the r8a7793.dtsi and r8a7794.dtsi, with patch 3/5 adding support for the DU0 clock to r8a7794.dtsi.
I will enable DU support for the Gose and Alt board in a later step when I'll have access to the schematics. I won't be able to test that due to lack of hardware though.
The R8A7794 datasheet documents as single DU clock named DU0, while the DU section documents DU0 and DU1 channels. I don't know at this point whether this is a datasheet mistake or if the DU0 clock drives both channels. I've opted for the latter, but I'd appreciate a confirmation.
Laurent Pinchart (5): drm: rcar-du: Add support for the R8A7793 DU drm: rcar-du: Add support for the R8A7794 DU ARM: shmobile: r8a7794: Add DU0 clock ARM: shmobile: r8a7793: Add DU node to device tree ARM: shmobile: r8a7794: Add DU node to device tree
.../devicetree/bindings/video/renesas,du.txt | 14 +++++---- arch/arm/boot/dts/r8a7793.dtsi | 30 +++++++++++++++++++ arch/arm/boot/dts/r8a7794.dtsi | 35 ++++++++++++++++++++-- drivers/gpu/drm/rcar-du/rcar_du_drv.c | 27 ++++++++++++++++- drivers/gpu/drm/rcar-du/rcar_du_group.c | 5 ++-- include/dt-bindings/clock/r8a7794-clock.h | 1 + 6 files changed, 101 insertions(+), 11 deletions(-)
The R8A7793 DU is identical to the R8A7791 and thus only requires a new DT compatible string.
Signed-off-by: Laurent Pinchart laurent.pinchart+renesas@ideasonboard.com --- Documentation/devicetree/bindings/video/renesas,du.txt | 12 +++++++----- drivers/gpu/drm/rcar-du/rcar_du_drv.c | 4 +++- 2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/video/renesas,du.txt b/Documentation/devicetree/bindings/video/renesas,du.txt index c902323928f7..d05be121486f 100644 --- a/Documentation/devicetree/bindings/video/renesas,du.txt +++ b/Documentation/devicetree/bindings/video/renesas,du.txt @@ -5,7 +5,8 @@ Required Properties: - compatible: must be one of the following. - "renesas,du-r8a7779" for R8A7779 (R-Car H1) compatible DU - "renesas,du-r8a7790" for R8A7790 (R-Car H2) compatible DU - - "renesas,du-r8a7791" for R8A7791 (R-Car M2) compatible DU + - "renesas,du-r8a7791" for R8A7791 (R-Car M2-W) compatible DU + - "renesas,du-r8a7793" for R8A7793 (R-Car M2-N) compatible DU
- reg: A list of base address and length of each memory resource, one for each entry in the reg-names property. @@ -22,9 +23,9 @@ Required Properties: - clock-names: Name of the clocks. This property is model-dependent. - R8A7779 uses a single functional clock. The clock doesn't need to be named. - - R8A7790 and R8A7791 use one functional clock per channel and one clock - per LVDS encoder. The functional clocks must be named "du.x" with "x" - being the channel numerical index. The LVDS clocks must be named + - R8A779[013] use one functional clock per channel and one clock per LVDS + encoder (if available). The functional clocks must be named "du.x" with + "x" being the channel numerical index. The LVDS clocks must be named "lvds.x" with "x" being the LVDS encoder numerical index. - In addition to the functional and encoder clocks, all DU versions also support externally supplied pixel clocks. Those clocks are optional. @@ -43,7 +44,8 @@ corresponding to each DU output. ----------------------------------------------------------------------------- R8A7779 (H1) DPAD 0 DPAD 1 - R8A7790 (H2) DPAD LVDS 0 LVDS 1 - R8A7791 (M2) DPAD LVDS 0 - + R8A7791 (M2-W) DPAD LVDS 0 - + R8A7793 (M2-N) DPAD LVDS 0 -
Example: R8A7790 (R-Car H2) DU diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c index cbb7d8530d79..5a7e6dfa5df2 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c @@ -84,12 +84,13 @@ static const struct rcar_du_device_info rcar_du_r8a7790_info = { .num_lvds = 2, };
+/* M2-W (r8a7791) and M2-N (r8a7793) are identical */ static const struct rcar_du_device_info rcar_du_r8a7791_info = { .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK | RCAR_DU_FEATURE_EXT_CTRL_REGS, .num_crtcs = 2, .routes = { - /* R8A7791 has one RGB output, one LVDS output and one + /* R8A779[13] has one RGB output, one LVDS output and one * (currently unsupported) TCON output. */ [RCAR_DU_OUTPUT_DPAD0] = { @@ -110,6 +111,7 @@ static const struct platform_device_id rcar_du_id_table[] = { { "rcar-du-r8a7779", (kernel_ulong_t)&rcar_du_r8a7779_info }, { "rcar-du-r8a7790", (kernel_ulong_t)&rcar_du_r8a7790_info }, { "rcar-du-r8a7791", (kernel_ulong_t)&rcar_du_r8a7791_info }, + { "rcar-du-r8a7793", (kernel_ulong_t)&rcar_du_r8a7791_info }, { } };
The R8A7794 DU has a fixed output routing configuration with one RGB output per CRTC and thus lacks the RGB output routing register field.
Signed-off-by: Laurent Pinchart laurent.pinchart+renesas@ideasonboard.com --- .../devicetree/bindings/video/renesas,du.txt | 4 +++- drivers/gpu/drm/rcar-du/rcar_du_drv.c | 23 ++++++++++++++++++++++ drivers/gpu/drm/rcar-du/rcar_du_group.c | 5 +++-- 3 files changed, 29 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/video/renesas,du.txt b/Documentation/devicetree/bindings/video/renesas,du.txt index d05be121486f..eccd4f4867b2 100644 --- a/Documentation/devicetree/bindings/video/renesas,du.txt +++ b/Documentation/devicetree/bindings/video/renesas,du.txt @@ -7,6 +7,7 @@ Required Properties: - "renesas,du-r8a7790" for R8A7790 (R-Car H2) compatible DU - "renesas,du-r8a7791" for R8A7791 (R-Car M2-W) compatible DU - "renesas,du-r8a7793" for R8A7793 (R-Car M2-N) compatible DU + - "renesas,du-r8a7794" for R8A7794 (R-Car E2) compatible DU
- reg: A list of base address and length of each memory resource, one for each entry in the reg-names property. @@ -23,7 +24,7 @@ Required Properties: - clock-names: Name of the clocks. This property is model-dependent. - R8A7779 uses a single functional clock. The clock doesn't need to be named. - - R8A779[013] use one functional clock per channel and one clock per LVDS + - R8A779[0134] use one functional clock per channel and one clock per LVDS encoder (if available). The functional clocks must be named "du.x" with "x" being the channel numerical index. The LVDS clocks must be named "lvds.x" with "x" being the LVDS encoder numerical index. @@ -46,6 +47,7 @@ corresponding to each DU output. R8A7790 (H2) DPAD LVDS 0 LVDS 1 R8A7791 (M2-W) DPAD LVDS 0 - R8A7793 (M2-N) DPAD LVDS 0 - + R8A7794 (E2) DPAD 0 DPAD 1 -
Example: R8A7790 (R-Car H2) DU diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c index 5a7e6dfa5df2..2b9a7c87467c 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c @@ -107,11 +107,34 @@ static const struct rcar_du_device_info rcar_du_r8a7791_info = { .num_lvds = 1, };
+static const struct rcar_du_device_info rcar_du_r8a7794_info = { + .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK + | RCAR_DU_FEATURE_EXT_CTRL_REGS, + .num_crtcs = 2, + .routes = { + /* R8A7794 has two RGB outputs and one (currently unsupported) + * TCON output. + */ + [RCAR_DU_OUTPUT_DPAD0] = { + .possible_crtcs = BIT(0), + .encoder_type = DRM_MODE_ENCODER_NONE, + .port = 0, + }, + [RCAR_DU_OUTPUT_DPAD1] = { + .possible_crtcs = BIT(1), + .encoder_type = DRM_MODE_ENCODER_NONE, + .port = 1, + }, + }, + .num_lvds = 1, +}; + static const struct platform_device_id rcar_du_id_table[] = { { "rcar-du-r8a7779", (kernel_ulong_t)&rcar_du_r8a7779_info }, { "rcar-du-r8a7790", (kernel_ulong_t)&rcar_du_r8a7790_info }, { "rcar-du-r8a7791", (kernel_ulong_t)&rcar_du_r8a7791_info }, { "rcar-du-r8a7793", (kernel_ulong_t)&rcar_du_r8a7791_info }, + { "rcar-du-r8a7794", (kernel_ulong_t)&rcar_du_r8a7794_info }, { } };
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/rcar-du/rcar_du_group.c index 7fd39a7d91c8..8e2ffe025153 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_group.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c @@ -49,9 +49,10 @@ static void rcar_du_group_setup_defr8(struct rcar_du_group *rgrp) u32 defr8 = DEFR8_CODE | DEFR8_DEFE8;
/* The DEFR8 register for the first group also controls RGB output - * routing to DPAD0 + * routing to DPAD0 for DU instances that support it. */ - if (rgrp->index == 0) + if (rgrp->dev->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs > 1 && + rgrp->index == 0) defr8 |= DEFR8_DRGBS_DU(rgrp->dev->dpad0_source);
rcar_du_group_write(rgrp, DEFR8, defr8);
The DU0 clock is an MSTP clock, child of the CPG ZX clock.
Signed-off-by: Laurent Pinchart laurent.pinchart+renesas@ideasonboard.com --- arch/arm/boot/dts/r8a7794.dtsi | 7 ++++--- include/dt-bindings/clock/r8a7794-clock.h | 1 + 2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index b73819423311..2a0d375e45b3 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -675,19 +675,20 @@ reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, - <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>; + <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, + <&zx_clk>; #clock-cells = <1>; clock-indices = < R8A7794_CLK_EHCI R8A7794_CLK_HSUSB R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1 - R8A7794_CLK_SCIF0 + R8A7794_CLK_SCIF0 R8A7794_CLK_DU0 >; clock-output-names = "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0", - "scif3", "scif2", "scif1", "scif0"; + "scif3", "scif2", "scif1", "scif0", "du0"; }; mstp8_clks: mstp8_clks@e6150990 { compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h index 09da38a58776..a7a7e0370968 100644 --- a/include/dt-bindings/clock/r8a7794-clock.h +++ b/include/dt-bindings/clock/r8a7794-clock.h @@ -79,6 +79,7 @@ #define R8A7794_CLK_SCIF2 19 #define R8A7794_CLK_SCIF1 20 #define R8A7794_CLK_SCIF0 21 +#define R8A7794_CLK_DU0 24
/* MSTP8 */ #define R8A7794_CLK_VIN1 10
On Fri, Jul 17, 2015 at 10:26 AM, Laurent Pinchart laurent.pinchart+renesas@ideasonboard.com wrote:
The DU0 clock is an MSTP clock, child of the CPG ZX clock.
Signed-off-by: Laurent Pinchart laurent.pinchart+renesas@ideasonboard.com
Acked-by: by: Geert Uytterhoeven geert+renesas@glider.be
Gr{oetje,eeting}s,
Geert
-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Add the DU device with a disabled state. Boards that want to enable the DU need to specify the output topology.
Signed-off-by: Laurent Pinchart laurent.pinchart+renesas@ideasonboard.com --- arch/arm/boot/dts/r8a7793.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index c50c5f65388a..2072f55a524a 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -140,6 +140,36 @@ status = "disabled"; };
+ du: display@feb00000 { + compatible = "renesas,du-r8a7793"; + reg = <0 0xfeb00000 0 0x40000>, + <0 0xfeb90000 0 0x1c>; + reg-names = "du", "lvds.0"; + interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>, + <0 268 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7793_CLK_DU0>, + <&mstp7_clks R8A7793_CLK_DU1>, + <&mstp7_clks R8A7793_CLK_LVDS0>; + clock-names = "du.0", "du.1", "lvds.0"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_lvds0: endpoint { + }; + }; + }; + }; + clocks { #address-cells = <2>; #size-cells = <2>;
Add the DU device with a disabled state. Boards that want to enable the DU need to specify the output topology.
Signed-off-by: Laurent Pinchart laurent.pinchart+renesas@ideasonboard.com --- arch/arm/boot/dts/r8a7794.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 2a0d375e45b3..409f6c4b1044 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -401,6 +401,34 @@ status = "disabled"; };
+ du: display@feb00000 { + compatible = "renesas,du-r8a7794"; + reg = <0 0xfeb00000 0 0x40000>; + reg-names = "du"; + interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>, + <0 268 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7794_CLK_DU0>, + <&mstp7_clks R8A7794_CLK_DU0>; + clock-names = "du.0", "du.1"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb0: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_rgb1: endpoint { + }; + }; + }; + }; + clocks { #address-cells = <2>; #size-cells = <2>;
Hi Laurent
This patch series adds support for the DU found in the R8A7793 and R8A7794 SoCs. It mostly consists of DT bindings updates (1/5 and 2/5) with a small driver change in 2/5 to support fixed RGB output routing. Patches 4/5 and 5/5 then add DU nodes to the r8a7793.dtsi and r8a7794.dtsi, with patch 3/5 adding support for the DU0 clock to r8a7794.dtsi.
I will enable DU support for the Gose and Alt board in a later step when I'll have access to the schematics. I won't be able to test that due to lack of hardware though.
The R8A7794 datasheet documents as single DU clock named DU0, while the DU section documents DU0 and DU1 channels. I don't know at this point whether this is a datasheet mistake or if the DU0 clock drives both channels. I've opted for the latter, but I'd appreciate a confirmation.
I will check it. please wait
Hi Laurent, again
This patch series adds support for the DU found in the R8A7793 and R8A7794 SoCs. It mostly consists of DT bindings updates (1/5 and 2/5) with a small driver change in 2/5 to support fixed RGB output routing. Patches 4/5 and 5/5 then add DU nodes to the r8a7793.dtsi and r8a7794.dtsi, with patch 3/5 adding support for the DU0 clock to r8a7794.dtsi.
I will enable DU support for the Gose and Alt board in a later step when I'll have access to the schematics. I won't be able to test that due to lack of hardware though.
The R8A7794 datasheet documents as single DU clock named DU0, while the DU section documents DU0 and DU1 channels. I don't know at this point whether this is a datasheet mistake or if the DU0 clock drives both channels. I've opted for the latter, but I'd appreciate a confirmation.
I will check it. please wait
According to HW team, MSTP page of datasheet seems wrong Maybe you have already tried, but, can you access to MSTPSR1 :: 27bit (for DU1)
Hi Morimoto-san,
Thank you for your quick reply.
On Friday 17 July 2015 09:03:32 Kuninori Morimoto wrote:
Hi Laurent, again
This patch series adds support for the DU found in the R8A7793 and R8A7794 SoCs. It mostly consists of DT bindings updates (1/5 and 2/5) with a small driver change in 2/5 to support fixed RGB output routing. Patches 4/5 and 5/5 then add DU nodes to the r8a7793.dtsi and r8a7794.dtsi, with patch 3/5 adding support for the DU0 clock to r8a7794.dtsi.
I will enable DU support for the Gose and Alt board in a later step when I'll have access to the schematics. I won't be able to test that due to lack of hardware though.
The R8A7794 datasheet documents as single DU clock named DU0, while the DU section documents DU0 and DU1 channels. I don't know at this point whether this is a datasheet mistake or if the DU0 clock drives both channels. I've opted for the latter, but I'd appreciate a confirmation.
I will check it. please wait
According to HW team, MSTP page of datasheet seems wrong Maybe you have already tried, but, can you access to MSTPSR1 :: 27bit (for DU1)
I would try if I had access to an Alt board :-)
Magnus, do you have an Alt board I could access remotely ?
Hi Laurent,
On Fri, Jul 17, 2015 at 6:06 PM, Laurent Pinchart laurent.pinchart@ideasonboard.com wrote:
Hi Morimoto-san,
Thank you for your quick reply.
On Friday 17 July 2015 09:03:32 Kuninori Morimoto wrote:
Hi Laurent, again
This patch series adds support for the DU found in the R8A7793 and R8A7794 SoCs. It mostly consists of DT bindings updates (1/5 and 2/5) with a small driver change in 2/5 to support fixed RGB output routing. Patches 4/5 and 5/5 then add DU nodes to the r8a7793.dtsi and r8a7794.dtsi, with patch 3/5 adding support for the DU0 clock to r8a7794.dtsi.
I will enable DU support for the Gose and Alt board in a later step when I'll have access to the schematics. I won't be able to test that due to lack of hardware though.
The R8A7794 datasheet documents as single DU clock named DU0, while the DU section documents DU0 and DU1 channels. I don't know at this point whether this is a datasheet mistake or if the DU0 clock drives both channels. I've opted for the latter, but I'd appreciate a confirmation.
I will check it. please wait
According to HW team, MSTP page of datasheet seems wrong Maybe you have already tried, but, can you access to MSTPSR1 :: 27bit (for DU1)
I would try if I had access to an Alt board :-)
Magnus, do you have an Alt board I could access remotely ?
Not sure if it is hooked up right now, but I will make sure you can get access sometime soon.
Cheers,
/ magnus
dri-devel@lists.freedesktop.org
-
Geert Uytterhoeven -
Kuninori Morimoto -
Laurent Pinchart -
Laurent Pinchart -
Magnus Damm