[drm-tip:drm-tip 899/925] drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c:54:6: error: implicit declaration of function 'regmap_field_read_poll_timeout' - dri-devel - freedesktop.org experimental mailing list

11 Oct 2017


      tree:   git://anongit.freedesktop.org/drm/drm-tip drm-tip
head:   36e0e803d3d7fb3d74e9086ad7c749123661589e
commit: 939d749ad6649c4123daf63a8bc053ea97ad2218 [899/925] drm/sun4i: hdmi: Add support for controller hardware variants
config: arm-defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        git checkout 939d749ad6649c4123daf63a8bc053ea97ad2218
        # save the attached .config to linux build tree
        make.cross ARCH=arm
Note: the drm-tip/drm-tip HEAD 36e0e803d3d7fb3d74e9086ad7c749123661589e builds fine.
      It only hurts bisectibility.
All error/warnings (new ones prefixed by >>):
drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c: In function 'fifo_transfer':
...
...
drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c:54:6: error: implicit declaration of function 'regmap_field_read_poll_timeout' [-Werror=implicit-function-declaration]
if (regmap_field_read_poll_timeout(hdmi->field_ddc_int_status, reg,
         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
...
...
drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c:54:6: warning: 'reg' is used uninitialized in this function [-Wuninitialized]
if (regmap_field_read_poll_timeout(hdmi->field_ddc_int_status, reg,
         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
            reg & mask, len * byte_time_ns,
            ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
            100000))
            ~~~~~~~
   drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c: In function 'sun4i_hdmi_i2c_xfer':
...
...
drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c:171:6: warning: 'reg' may be used uninitialized in this function [-Wmaybe-uninitialized]
if (regmap_field_read_poll_timeout(hdmi->field_ddc_reset,
         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
            reg, !reg, 100, 2000)) {
            ~~~~~~~~~~~~~~~~~~~~~
   cc1: some warnings being treated as errors
vim +/regmap_field_read_poll_timeout +54 drivers/gpu/drm/sun4i/sun4i_hdmi_i2c.c
28	
    29	static int fifo_transfer(struct sun4i_hdmi *hdmi, u8 *buf, int len, bool read)
    30	{
    31		/*
    32		 * 1 byte takes 9 clock cycles (8 bits + 1 ACK) = 90 us for 100 kHz
    33		 * clock. As clock rate is fixed, just round it up to 100 us.
    34		 */
    35		const unsigned long byte_time_ns = 100;
    36		const u32 mask = SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK |
    37				 SUN4I_HDMI_DDC_INT_STATUS_FIFO_REQUEST |
    38				 SUN4I_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE;
    39		u32 reg;
    40		/*
    41		 * If threshold is inclusive, then the FIFO may only have
    42		 * RX_THRESHOLD number of bytes, instead of RX_THRESHOLD + 1.
    43		 */
    44		int read_len = RX_THRESHOLD +
    45			(hdmi->variant->ddc_fifo_thres_incl ? 0 : 1);
    46	
    47		/*
    48		 * Limit transfer length by FIFO threshold or FIFO size.
    49		 * For TX the threshold is for an empty FIFO.
    50		 */
    51		len = min_t(int, len, read ? read_len : SUN4I_HDMI_DDC_FIFO_SIZE);
    52	
    53		/* Wait until error, FIFO request bit set or transfer complete */
...
54		if (regmap_field_read_poll_timeout(hdmi->field_ddc_int_status, reg,
55						   reg & mask, len * byte_time_ns,
    56						   100000))
    57			return -ETIMEDOUT;
    58	
    59		if (reg & SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK)
    60			return -EIO;
    61	
    62		if (read)
    63			readsb(hdmi->base + hdmi->variant->ddc_fifo_reg, buf, len);
    64		else
    65			writesb(hdmi->base + hdmi->variant->ddc_fifo_reg, buf, len);
    66	
    67		/* Clear FIFO request bit by forcing a write to that bit */
    68		regmap_field_force_write(hdmi->field_ddc_int_status,
    69					 SUN4I_HDMI_DDC_INT_STATUS_FIFO_REQUEST);
    70	
    71		return len;
    72	}
    73	
    74	static int xfer_msg(struct sun4i_hdmi *hdmi, struct i2c_msg *msg)
    75	{
    76		int i, len;
    77		u32 reg;
    78	
    79		/* Set FIFO direction */
    80		if (hdmi->variant->ddc_fifo_has_dir) {
    81			reg = readl(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG);
    82			reg &= ~SUN4I_HDMI_DDC_CTRL_FIFO_DIR_MASK;
    83			reg |= (msg->flags & I2C_M_RD) ?
    84			       SUN4I_HDMI_DDC_CTRL_FIFO_DIR_READ :
    85			       SUN4I_HDMI_DDC_CTRL_FIFO_DIR_WRITE;
    86			writel(reg, hdmi->base + SUN4I_HDMI_DDC_CTRL_REG);
    87		}
    88	
    89		/* Clear address register (not cleared by soft reset) */
    90		regmap_field_write(hdmi->field_ddc_addr_reg, 0);
    91	
    92		/* Set I2C address */
    93		regmap_field_write(hdmi->field_ddc_slave_addr, msg->addr);
    94	
    95		/*
    96		 * Set FIFO RX/TX thresholds and clear FIFO
    97		 *
    98		 * If threshold is inclusive, we can set the TX threshold to
    99		 * 0 instead of 1.
   100		 */
   101		regmap_field_write(hdmi->field_ddc_fifo_tx_thres,
   102				   hdmi->variant->ddc_fifo_thres_incl ? 0 : 1);
   103		regmap_field_write(hdmi->field_ddc_fifo_rx_thres, RX_THRESHOLD);
   104		regmap_field_write(hdmi->field_ddc_fifo_clear, 1);
   105		if (regmap_field_read_poll_timeout(hdmi->field_ddc_fifo_clear,
   106						   reg, !reg, 100, 2000))
   107			return -EIO;
   108	
   109		/* Set transfer length */
   110		regmap_field_write(hdmi->field_ddc_byte_count, msg->len);
   111	
   112		/* Set command */
   113		regmap_field_write(hdmi->field_ddc_cmd,
   114				   msg->flags & I2C_M_RD ?
   115				   SUN4I_HDMI_DDC_CMD_IMPLICIT_READ :
   116				   SUN4I_HDMI_DDC_CMD_IMPLICIT_WRITE);
   117	
   118		/* Clear interrupt status bits by forcing a write */
   119		regmap_field_force_write(hdmi->field_ddc_int_status,
   120					 SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK |
   121					 SUN4I_HDMI_DDC_INT_STATUS_FIFO_REQUEST |
   122					 SUN4I_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE);
   123	
   124		/* Start command */
   125		regmap_field_write(hdmi->field_ddc_start, 1);
   126	
   127		/* Transfer bytes */
   128		for (i = 0; i < msg->len; i += len) {
   129			len = fifo_transfer(hdmi, msg->buf + i, msg->len - i,
   130					    msg->flags & I2C_M_RD);
   131			if (len <= 0)
   132				return len;
   133		}
   134	
   135		/* Wait for command to finish */
   136		if (regmap_field_read_poll_timeout(hdmi->field_ddc_start,
   137						   reg, !reg, 100, 100000))
   138			return -EIO;
   139	
   140		/* Check for errors */
   141		regmap_field_read(hdmi->field_ddc_int_status, &reg);
   142		if ((reg & SUN4I_HDMI_DDC_INT_STATUS_ERROR_MASK) ||
   143		    !(reg & SUN4I_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE)) {
   144			return -EIO;
   145		}
   146	
   147		return 0;
   148	}
   149	
   150	static int sun4i_hdmi_i2c_xfer(struct i2c_adapter *adap,
   151				       struct i2c_msg *msgs, int num)
   152	{
   153		struct sun4i_hdmi *hdmi = i2c_get_adapdata(adap);
   154		u32 reg;
   155		int err, i, ret = num;
   156	
   157		for (i = 0; i < num; i++) {
   158			if (!msgs[i].len)
   159				return -EINVAL;
   160			if (msgs[i].len > SUN4I_HDMI_DDC_BYTE_COUNT_MAX)
   161				return -EINVAL;
   162		}
   163	
   164		/* DDC clock needs to be enabled for the module to work */
   165		clk_prepare_enable(hdmi->ddc_clk);
   166		clk_set_rate(hdmi->ddc_clk, 100000);
   167	
   168		/* Reset I2C controller */
   169		regmap_field_write(hdmi->field_ddc_en, 1);
   170		regmap_field_write(hdmi->field_ddc_reset, 1);
...
171		if (regmap_field_read_poll_timeout(hdmi->field_ddc_reset,
172						   reg, !reg, 100, 2000)) {
   173			clk_disable_unprepare(hdmi->ddc_clk);
   174			return -EIO;
   175		}
   176	
   177		regmap_field_write(hdmi->field_ddc_sck_en, 1);
   178		regmap_field_write(hdmi->field_ddc_sda_en, 1);
   179	
   180		for (i = 0; i < num; i++) {
   181			err = xfer_msg(hdmi, &msgs[i]);
   182			if (err) {
   183				ret = err;
   184				break;
   185			}
   186		}
   187	
   188		clk_disable_unprepare(hdmi->ddc_clk);
   189		return ret;
   190	}
   191
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