From: Ville Syrjälä ville.syrjala@linux.intel.com
Fix a div-by-zero on gen2, and make the L-shaped memory detection actually work on cl/ctg. Atm the SWIZZLE_UNKNOWN stuff just trips some GEM_BUG_ONs. This doesn't fix those but since I populate all my memory channels symmetrically I get to avoid the GEM_BUG_ONs by correctly detecting that I don't have an L-shaped memory configuration.
Ville Syrjälä (4): drm/i915: Avoid div-by-zero on gen2 drm/i915: Read C0DRB3/C1DRB3 as 16 bits again drm/i915: Give C0DRB3/C1DRB3 a _BW suffix drm/i915: Rewrite CL/CTG L-shaped memory detection
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +- drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 19 ++++++++++--------- drivers/gpu/drm/i915/i915_debugfs.c | 16 ++++++++++++---- drivers/gpu/drm/i915/i915_reg.h | 8 ++++++-- 4 files changed, 29 insertions(+), 16 deletions(-)
From: Ville Syrjälä ville.syrjala@linux.intel.com
Gen2 tiles are 2KiB in size so i915_gem_object_get_tile_row_size() can in fact return <4KiB, which leads to div-by-zero here. Avoid that.
Not sure i915_gem_object_get_tile_row_size() is entirely sane anyway since it doesn't account for the different tile layouts on i8xx/i915...
I'm not able to hit this before commit 6846895fde05 ("drm/i915: Replace PIN_NONFAULT with calls to PIN_NOEVICT") and it looks like I also need to run recent version of Mesa. With those in place xonotic trips on this quite easily on my 85x.
Cc: stable@vger.kernel.org Reviewed-by: Chris Wilson chris@chris-wilson.co.uk Signed-off-by: Ville Syrjälä ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c index 2561a2f1e54f..8598a1c78a4c 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c @@ -189,7 +189,7 @@ compute_partial_view(const struct drm_i915_gem_object *obj, struct i915_ggtt_view view;
if (i915_gem_object_is_tiled(obj)) - chunk = roundup(chunk, tile_row_pages(obj)); + chunk = roundup(chunk, tile_row_pages(obj) ?: 1);
view.type = I915_GGTT_VIEW_PARTIAL; view.partial.offset = rounddown(page_offset, chunk);
From: Ville Syrjälä ville.syrjala@linux.intel.com
We've defined C0DRB3/C0DRB3 as 16 bit registers, so access them as such.
Fixes: 1c8242c3a4b2 ("drm/i915: Use unchecked writes for setting up the fences") Reviewed-by: Chris Wilson chris@chris-wilson.co.uk Signed-off-by: Ville Syrjälä ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c index e72b7a0dc316..8a322594210c 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c @@ -653,8 +653,8 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt) * banks of memory are paired and unswizzled on the * uneven portion, so leave that as unknown. */ - if (intel_uncore_read(uncore, C0DRB3) == - intel_uncore_read(uncore, C1DRB3)) { + if (intel_uncore_read16(uncore, C0DRB3) == + intel_uncore_read16(uncore, C1DRB3)) { swizzle_x = I915_BIT_6_SWIZZLE_9_10; swizzle_y = I915_BIT_6_SWIZZLE_9; }
From: Ville Syrjälä ville.syrjala@linux.intel.com
These are the 965g/g45/g33 specific DRB registers. Give them a suitable suffix so we can add their counterparts for other platforms.
Reviewed-by: Chris Wilson chris@chris-wilson.co.uk Signed-off-by: Ville Syrjälä ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 4 ++-- drivers/gpu/drm/i915/i915_debugfs.c | 4 ++-- drivers/gpu/drm/i915/i915_reg.h | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c index 8a322594210c..0fa6c38893f7 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c @@ -653,8 +653,8 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt) * banks of memory are paired and unswizzled on the * uneven portion, so leave that as unknown. */ - if (intel_uncore_read16(uncore, C0DRB3) == - intel_uncore_read16(uncore, C1DRB3)) { + if (intel_uncore_read16(uncore, C0DRB3_BW) == + intel_uncore_read16(uncore, C1DRB3_BW)) { swizzle_x = I915_BIT_6_SWIZZLE_9_10; swizzle_y = I915_BIT_6_SWIZZLE_9; } diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index b654b7498bcd..8dd374691102 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -622,9 +622,9 @@ static int i915_swizzle_info(struct seq_file *m, void *data) seq_printf(m, "DDC2 = 0x%08x\n", intel_uncore_read(uncore, DCC2)); seq_printf(m, "C0DRB3 = 0x%04x\n", - intel_uncore_read16(uncore, C0DRB3)); + intel_uncore_read16(uncore, C0DRB3_BW)); seq_printf(m, "C1DRB3 = 0x%04x\n", - intel_uncore_read16(uncore, C1DRB3)); + intel_uncore_read16(uncore, C1DRB3_BW)); } else if (INTEL_GEN(dev_priv) >= 6) { seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", intel_uncore_read(uncore, MAD_DIMM_C0)); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 66a902b3bb8e..0587b2455ea1 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3787,8 +3787,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define CSHRDDR3CTL_DDR3 (1 << 2)
/* 965 MCH register controlling DRAM channel configuration */ -#define C0DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x206) -#define C1DRB3 _MMIO(MCHBAR_MIRROR_BASE + 0x606) +#define C0DRB3_BW _MMIO(MCHBAR_MIRROR_BASE + 0x206) +#define C1DRB3_BW _MMIO(MCHBAR_MIRROR_BASE + 0x606)
/* snb MCH registers for reading the DRAM channel configuration */ #define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
From: Ville Syrjälä ville.syrjala@linux.intel.com
Currently we try to detect a symmetric memory configurations using a magic DCC2_MODIFIED_ENHANCED_DISABLE bit. That bit is either only set on a very specific subset of machines or it just does not exist (it's not mentioned in any public chipset datasheets I've found). As it happens my CL/CTG machines never set said bit, even if I populate the channels with identical sticks.
So let's do the L-shaped memory detection the same way as the desktop variants, ie. just look at the DRAM rank boundary registers to see if both channels have an identical size.
With this my CL/CTG no longer claim L-shaped memory when I use identical sticks. Also tested with non-matching sticks just to make sure the L-shaped memory is still properly detected.
And for completeness let's update the debugfs code to dump the correct set of registers on each platform.
Cc: Chris Wilson chris@chris-wilson.co.uk Signed-off-by: Ville Syrjälä ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 15 ++++++++------- drivers/gpu/drm/i915/i915_debugfs.c | 16 ++++++++++++---- drivers/gpu/drm/i915/i915_reg.h | 4 ++++ 3 files changed, 24 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c index 0fa6c38893f7..754f20768de5 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c @@ -693,14 +693,15 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt) swizzle_x = I915_BIT_6_SWIZZLE_9_10_17; swizzle_y = I915_BIT_6_SWIZZLE_9_17; } - break; - }
- /* check for L-shaped memory aka modified enhanced addressing */ - if (IS_GEN(i915, 4) && - !(intel_uncore_read(uncore, DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) { - swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; - swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; + /* check for L-shaped memory aka modified enhanced addressing */ + if (IS_GEN(i915, 4) && + intel_uncore_read16(uncore, C0DRB3_CL) != + intel_uncore_read16(uncore, C1DRB3_CL)) { + swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; + swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; + } + break; }
if (dcc == 0xffffffff) { diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 8dd374691102..6de11ffcde38 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -621,10 +621,18 @@ static int i915_swizzle_info(struct seq_file *m, void *data) intel_uncore_read(uncore, DCC)); seq_printf(m, "DDC2 = 0x%08x\n", intel_uncore_read(uncore, DCC2)); - seq_printf(m, "C0DRB3 = 0x%04x\n", - intel_uncore_read16(uncore, C0DRB3_BW)); - seq_printf(m, "C1DRB3 = 0x%04x\n", - intel_uncore_read16(uncore, C1DRB3_BW)); + + if (IS_G45(dev_priv) || IS_I965G(dev_priv) || IS_G33(dev_priv)) { + seq_printf(m, "C0DRB3 = 0x%04x\n", + intel_uncore_read16(uncore, C0DRB3_BW)); + seq_printf(m, "C1DRB3 = 0x%04x\n", + intel_uncore_read16(uncore, C1DRB3_BW)); + } else if (IS_GEN(dev_priv, 4)) { + seq_printf(m, "C0DRB3 = 0x%04x\n", + intel_uncore_read16(uncore, C0DRB3_CL)); + seq_printf(m, "C1DRB3 = 0x%04x\n", + intel_uncore_read16(uncore, C1DRB3_CL)); + } } else if (INTEL_GEN(dev_priv) >= 6) { seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", intel_uncore_read(uncore, MAD_DIMM_C0)); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0587b2455ea1..055c258179a1 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3790,6 +3790,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define C0DRB3_BW _MMIO(MCHBAR_MIRROR_BASE + 0x206) #define C1DRB3_BW _MMIO(MCHBAR_MIRROR_BASE + 0x606)
+/* 965gm,ctg DRAM channel configuration */ +#define C0DRB3_CL _MMIO(MCHBAR_MIRROR_BASE + 0x1206) +#define C1DRB3_CL _MMIO(MCHBAR_MIRROR_BASE + 0x1306) + /* snb MCH registers for reading the DRAM channel configuration */ #define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004) #define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
On Wed, Apr 21, 2021 at 06:34:01PM +0300, Ville Syrjala wrote:
From: Ville Syrjälä ville.syrjala@linux.intel.com
Currently we try to detect a symmetric memory configurations using a magic DCC2_MODIFIED_ENHANCED_DISABLE bit. That bit is either only set on a very specific subset of machines or it just does not exist (it's not mentioned in any public chipset datasheets I've found). As it happens my CL/CTG machines never set said bit, even if I populate the channels with identical sticks.
So let's do the L-shaped memory detection the same way as the desktop variants, ie. just look at the DRAM rank boundary registers to see if both channels have an identical size.
With this my CL/CTG no longer claim L-shaped memory when I use identical sticks. Also tested with non-matching sticks just to make sure the L-shaped memory is still properly detected.
And for completeness let's update the debugfs code to dump the correct set of registers on each platform.
Cc: Chris Wilson chris@chris-wilson.co.uk Signed-off-by: Ville Syrjälä ville.syrjala@linux.intel.com
Did you check this with the swapping igt? I have some vague memories of bug reports where somehow the machine was acting like it's L-shaped memory despite that banks were populated equally. I've iirc tried all kinds of tricks to figure it out, all to absolutely no avail.
tbh I'd just not touch this, not really worth it. -Daniel
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 15 ++++++++------- drivers/gpu/drm/i915/i915_debugfs.c | 16 ++++++++++++---- drivers/gpu/drm/i915/i915_reg.h | 4 ++++ 3 files changed, 24 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c index 0fa6c38893f7..754f20768de5 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c @@ -693,14 +693,15 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt) swizzle_x = I915_BIT_6_SWIZZLE_9_10_17; swizzle_y = I915_BIT_6_SWIZZLE_9_17; }
break;}/* check for L-shaped memory aka modified enhanced addressing */if (IS_GEN(i915, 4) &&!(intel_uncore_read(uncore, DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) {swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
/* check for L-shaped memory aka modified enhanced addressing */if (IS_GEN(i915, 4) &&intel_uncore_read16(uncore, C0DRB3_CL) !=intel_uncore_read16(uncore, C1DRB3_CL)) {swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;}break;}
if (dcc == 0xffffffff) {
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 8dd374691102..6de11ffcde38 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -621,10 +621,18 @@ static int i915_swizzle_info(struct seq_file *m, void *data) intel_uncore_read(uncore, DCC)); seq_printf(m, "DDC2 = 0x%08x\n", intel_uncore_read(uncore, DCC2));
seq_printf(m, "C0DRB3 = 0x%04x\n",intel_uncore_read16(uncore, C0DRB3_BW));seq_printf(m, "C1DRB3 = 0x%04x\n",intel_uncore_read16(uncore, C1DRB3_BW));
if (IS_G45(dev_priv) || IS_I965G(dev_priv) || IS_G33(dev_priv)) {seq_printf(m, "C0DRB3 = 0x%04x\n",intel_uncore_read16(uncore, C0DRB3_BW));seq_printf(m, "C1DRB3 = 0x%04x\n",intel_uncore_read16(uncore, C1DRB3_BW));} else if (IS_GEN(dev_priv, 4)) {seq_printf(m, "C0DRB3 = 0x%04x\n",intel_uncore_read16(uncore, C0DRB3_CL));seq_printf(m, "C1DRB3 = 0x%04x\n",intel_uncore_read16(uncore, C1DRB3_CL));}diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0587b2455ea1..055c258179a1 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3790,6 +3790,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define C0DRB3_BW _MMIO(MCHBAR_MIRROR_BASE + 0x206) #define C1DRB3_BW _MMIO(MCHBAR_MIRROR_BASE + 0x606)
+/* 965gm,ctg DRAM channel configuration */ +#define C0DRB3_CL _MMIO(MCHBAR_MIRROR_BASE + 0x1206) +#define C1DRB3_CL _MMIO(MCHBAR_MIRROR_BASE + 0x1306)
/* snb MCH registers for reading the DRAM channel configuration */ #define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
#define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
2.26.3
Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Thu, Apr 22, 2021 at 11:49:43AM +0200, Daniel Vetter wrote:
On Wed, Apr 21, 2021 at 06:34:01PM +0300, Ville Syrjala wrote:
From: Ville Syrjälä ville.syrjala@linux.intel.com
Currently we try to detect a symmetric memory configurations using a magic DCC2_MODIFIED_ENHANCED_DISABLE bit. That bit is either only set on a very specific subset of machines or it just does not exist (it's not mentioned in any public chipset datasheets I've found). As it happens my CL/CTG machines never set said bit, even if I populate the channels with identical sticks.
So let's do the L-shaped memory detection the same way as the desktop variants, ie. just look at the DRAM rank boundary registers to see if both channels have an identical size.
With this my CL/CTG no longer claim L-shaped memory when I use identical sticks. Also tested with non-matching sticks just to make sure the L-shaped memory is still properly detected.
And for completeness let's update the debugfs code to dump the correct set of registers on each platform.
Cc: Chris Wilson chris@chris-wilson.co.uk Signed-off-by: Ville Syrjälä ville.syrjala@linux.intel.com
Did you check this with the swapping igt? I have some vague memories of bug reports where somehow the machine was acting like it's L-shaped memory despite that banks were populated equally. I've iirc tried all kinds of tricks to figure it out, all to absolutely no avail.
Did you have a specific test in mind? I ran a bunch of things that seemed swizzle related. All passed just fine.
Chris did have similar concerns and suggested we should have better tests. I guess what I should try to do is some selftests which make sure we test both high and low physical addresses and check the swizzle pattern is as expected. But haven't found the time to do that yet.
tbh I'd just not touch this, not really worth it.
It's totally worth it to get gen4 machines working again.
-Daniel
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 15 ++++++++------- drivers/gpu/drm/i915/i915_debugfs.c | 16 ++++++++++++---- drivers/gpu/drm/i915/i915_reg.h | 4 ++++ 3 files changed, 24 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c index 0fa6c38893f7..754f20768de5 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c @@ -693,14 +693,15 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt) swizzle_x = I915_BIT_6_SWIZZLE_9_10_17; swizzle_y = I915_BIT_6_SWIZZLE_9_17; }
break;}/* check for L-shaped memory aka modified enhanced addressing */if (IS_GEN(i915, 4) &&!(intel_uncore_read(uncore, DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) {swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
/* check for L-shaped memory aka modified enhanced addressing */if (IS_GEN(i915, 4) &&intel_uncore_read16(uncore, C0DRB3_CL) !=intel_uncore_read16(uncore, C1DRB3_CL)) {swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;}break;}
if (dcc == 0xffffffff) {
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 8dd374691102..6de11ffcde38 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -621,10 +621,18 @@ static int i915_swizzle_info(struct seq_file *m, void *data) intel_uncore_read(uncore, DCC)); seq_printf(m, "DDC2 = 0x%08x\n", intel_uncore_read(uncore, DCC2));
seq_printf(m, "C0DRB3 = 0x%04x\n",intel_uncore_read16(uncore, C0DRB3_BW));seq_printf(m, "C1DRB3 = 0x%04x\n",intel_uncore_read16(uncore, C1DRB3_BW));
if (IS_G45(dev_priv) || IS_I965G(dev_priv) || IS_G33(dev_priv)) {seq_printf(m, "C0DRB3 = 0x%04x\n",intel_uncore_read16(uncore, C0DRB3_BW));seq_printf(m, "C1DRB3 = 0x%04x\n",intel_uncore_read16(uncore, C1DRB3_BW));} else if (IS_GEN(dev_priv, 4)) {seq_printf(m, "C0DRB3 = 0x%04x\n",intel_uncore_read16(uncore, C0DRB3_CL));seq_printf(m, "C1DRB3 = 0x%04x\n",intel_uncore_read16(uncore, C1DRB3_CL));}diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0587b2455ea1..055c258179a1 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3790,6 +3790,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define C0DRB3_BW _MMIO(MCHBAR_MIRROR_BASE + 0x206) #define C1DRB3_BW _MMIO(MCHBAR_MIRROR_BASE + 0x606)
+/* 965gm,ctg DRAM channel configuration */ +#define C0DRB3_CL _MMIO(MCHBAR_MIRROR_BASE + 0x1206) +#define C1DRB3_CL _MMIO(MCHBAR_MIRROR_BASE + 0x1306)
/* snb MCH registers for reading the DRAM channel configuration */ #define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
#define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
2.26.3
Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
-- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch
On Thu, Apr 22, 2021 at 04:11:22PM +0300, Ville Syrjälä wrote:
On Thu, Apr 22, 2021 at 11:49:43AM +0200, Daniel Vetter wrote:
On Wed, Apr 21, 2021 at 06:34:01PM +0300, Ville Syrjala wrote:
From: Ville Syrjälä ville.syrjala@linux.intel.com
Currently we try to detect a symmetric memory configurations using a magic DCC2_MODIFIED_ENHANCED_DISABLE bit. That bit is either only set on a very specific subset of machines or it just does not exist (it's not mentioned in any public chipset datasheets I've found). As it happens my CL/CTG machines never set said bit, even if I populate the channels with identical sticks.
So let's do the L-shaped memory detection the same way as the desktop variants, ie. just look at the DRAM rank boundary registers to see if both channels have an identical size.
With this my CL/CTG no longer claim L-shaped memory when I use identical sticks. Also tested with non-matching sticks just to make sure the L-shaped memory is still properly detected.
And for completeness let's update the debugfs code to dump the correct set of registers on each platform.
Cc: Chris Wilson chris@chris-wilson.co.uk Signed-off-by: Ville Syrjälä ville.syrjala@linux.intel.com
Did you check this with the swapping igt? I have some vague memories of bug reports where somehow the machine was acting like it's L-shaped memory despite that banks were populated equally. I've iirc tried all kinds of tricks to figure it out, all to absolutely no avail.
Did you have a specific test in mind? I ran a bunch of things that seemed swizzle related. All passed just fine.
gem_tiled_swapping should be the one. It tries to cycle your entire system memory through tiled buffers into swap and out of it. -Daniel
Chris did have similar concerns and suggested we should have better tests. I guess what I should try to do is some selftests which make sure we test both high and low physical addresses and check the swizzle pattern is as expected. But haven't found the time to do that yet.
tbh I'd just not touch this, not really worth it.
It's totally worth it to get gen4 machines working again.
-Daniel
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 15 ++++++++------- drivers/gpu/drm/i915/i915_debugfs.c | 16 ++++++++++++---- drivers/gpu/drm/i915/i915_reg.h | 4 ++++ 3 files changed, 24 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c index 0fa6c38893f7..754f20768de5 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c @@ -693,14 +693,15 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt) swizzle_x = I915_BIT_6_SWIZZLE_9_10_17; swizzle_y = I915_BIT_6_SWIZZLE_9_17; }
break;}/* check for L-shaped memory aka modified enhanced addressing */if (IS_GEN(i915, 4) &&!(intel_uncore_read(uncore, DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) {swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
/* check for L-shaped memory aka modified enhanced addressing */if (IS_GEN(i915, 4) &&intel_uncore_read16(uncore, C0DRB3_CL) !=intel_uncore_read16(uncore, C1DRB3_CL)) {swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;}break;}
if (dcc == 0xffffffff) {
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 8dd374691102..6de11ffcde38 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -621,10 +621,18 @@ static int i915_swizzle_info(struct seq_file *m, void *data) intel_uncore_read(uncore, DCC)); seq_printf(m, "DDC2 = 0x%08x\n", intel_uncore_read(uncore, DCC2));
seq_printf(m, "C0DRB3 = 0x%04x\n",intel_uncore_read16(uncore, C0DRB3_BW));seq_printf(m, "C1DRB3 = 0x%04x\n",intel_uncore_read16(uncore, C1DRB3_BW));
if (IS_G45(dev_priv) || IS_I965G(dev_priv) || IS_G33(dev_priv)) {seq_printf(m, "C0DRB3 = 0x%04x\n",intel_uncore_read16(uncore, C0DRB3_BW));seq_printf(m, "C1DRB3 = 0x%04x\n",intel_uncore_read16(uncore, C1DRB3_BW));} else if (IS_GEN(dev_priv, 4)) {seq_printf(m, "C0DRB3 = 0x%04x\n",intel_uncore_read16(uncore, C0DRB3_CL));seq_printf(m, "C1DRB3 = 0x%04x\n",intel_uncore_read16(uncore, C1DRB3_CL));}diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0587b2455ea1..055c258179a1 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3790,6 +3790,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define C0DRB3_BW _MMIO(MCHBAR_MIRROR_BASE + 0x206) #define C1DRB3_BW _MMIO(MCHBAR_MIRROR_BASE + 0x606)
+/* 965gm,ctg DRAM channel configuration */ +#define C0DRB3_CL _MMIO(MCHBAR_MIRROR_BASE + 0x1206) +#define C1DRB3_CL _MMIO(MCHBAR_MIRROR_BASE + 0x1306)
/* snb MCH registers for reading the DRAM channel configuration */ #define MAD_DIMM_C0 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5004)
#define MAD_DIMM_C1 _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5008)
2.26.3
Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
-- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch
-- Ville Syrjälä Intel
On Mon, Apr 26, 2021 at 06:08:59PM +0200, Daniel Vetter wrote:
On Thu, Apr 22, 2021 at 04:11:22PM +0300, Ville Syrjälä wrote:
On Thu, Apr 22, 2021 at 11:49:43AM +0200, Daniel Vetter wrote:
On Wed, Apr 21, 2021 at 06:34:01PM +0300, Ville Syrjala wrote:
From: Ville Syrjälä ville.syrjala@linux.intel.com
Currently we try to detect a symmetric memory configurations using a magic DCC2_MODIFIED_ENHANCED_DISABLE bit. That bit is either only set on a very specific subset of machines or it just does not exist (it's not mentioned in any public chipset datasheets I've found). As it happens my CL/CTG machines never set said bit, even if I populate the channels with identical sticks.
So let's do the L-shaped memory detection the same way as the desktop variants, ie. just look at the DRAM rank boundary registers to see if both channels have an identical size.
With this my CL/CTG no longer claim L-shaped memory when I use identical sticks. Also tested with non-matching sticks just to make sure the L-shaped memory is still properly detected.
And for completeness let's update the debugfs code to dump the correct set of registers on each platform.
Cc: Chris Wilson chris@chris-wilson.co.uk Signed-off-by: Ville Syrjälä ville.syrjala@linux.intel.com
Did you check this with the swapping igt? I have some vague memories of bug reports where somehow the machine was acting like it's L-shaped memory despite that banks were populated equally. I've iirc tried all kinds of tricks to figure it out, all to absolutely no avail.
Did you have a specific test in mind? I ran a bunch of things that seemed swizzle related. All passed just fine.
gem_tiled_swapping should be the one. It tries to cycle your entire system memory through tiled buffers into swap and out of it.
Passes with symmetric config, fails with L-shaped config (if I hack out the L-shape detection of course). So seems pretty solid.
A kernel based self test that looks at the physical address would still be nice I suppose. Though depending on the size of your RAM sticks figuring out where exactly the switchover from two channels to one channels happens probably requires a bit of work due to the PCI hole/etc.
Both my cl and ctg report this btw: bit6 swizzle for X-tiling = bit9/bit10/bit11 bit6 swizzle for Y-tiling = bit9/bit11 so unfortunately can't be sure the other swizzle modes would be correctly detected.
On Mon, Apr 26, 2021 at 08:18:39PM +0300, Ville Syrjälä wrote:
On Mon, Apr 26, 2021 at 06:08:59PM +0200, Daniel Vetter wrote:
On Thu, Apr 22, 2021 at 04:11:22PM +0300, Ville Syrjälä wrote:
On Thu, Apr 22, 2021 at 11:49:43AM +0200, Daniel Vetter wrote:
On Wed, Apr 21, 2021 at 06:34:01PM +0300, Ville Syrjala wrote:
From: Ville Syrjälä ville.syrjala@linux.intel.com
Currently we try to detect a symmetric memory configurations using a magic DCC2_MODIFIED_ENHANCED_DISABLE bit. That bit is either only set on a very specific subset of machines or it just does not exist (it's not mentioned in any public chipset datasheets I've found). As it happens my CL/CTG machines never set said bit, even if I populate the channels with identical sticks.
So let's do the L-shaped memory detection the same way as the desktop variants, ie. just look at the DRAM rank boundary registers to see if both channels have an identical size.
With this my CL/CTG no longer claim L-shaped memory when I use identical sticks. Also tested with non-matching sticks just to make sure the L-shaped memory is still properly detected.
And for completeness let's update the debugfs code to dump the correct set of registers on each platform.
Cc: Chris Wilson chris@chris-wilson.co.uk Signed-off-by: Ville Syrjälä ville.syrjala@linux.intel.com
Did you check this with the swapping igt? I have some vague memories of bug reports where somehow the machine was acting like it's L-shaped memory despite that banks were populated equally. I've iirc tried all kinds of tricks to figure it out, all to absolutely no avail.
Did you have a specific test in mind? I ran a bunch of things that seemed swizzle related. All passed just fine.
gem_tiled_swapping should be the one. It tries to cycle your entire system memory through tiled buffers into swap and out of it.
Passes with symmetric config, fails with L-shaped config (if I hack out the L-shape detection of course). So seems pretty solid.
A kernel based self test that looks at the physical address would still be nice I suppose. Though depending on the size of your RAM sticks figuring out where exactly the switchover from two channels to one channels happens probably requires a bit of work due to the PCI hole/etc.
Both my cl and ctg report this btw: bit6 swizzle for X-tiling = bit9/bit10/bit11 bit6 swizzle for Y-tiling = bit9/bit11 so unfortunately can't be sure the other swizzle modes would be correctly detected.
I think testing-wise this is as good as it gets. -Daniel
On Tue, Apr 27, 2021 at 10:58:07AM +0200, Daniel Vetter wrote:
On Mon, Apr 26, 2021 at 08:18:39PM +0300, Ville Syrjälä wrote:
On Mon, Apr 26, 2021 at 06:08:59PM +0200, Daniel Vetter wrote:
On Thu, Apr 22, 2021 at 04:11:22PM +0300, Ville Syrjälä wrote:
On Thu, Apr 22, 2021 at 11:49:43AM +0200, Daniel Vetter wrote:
On Wed, Apr 21, 2021 at 06:34:01PM +0300, Ville Syrjala wrote:
From: Ville Syrjälä ville.syrjala@linux.intel.com
Currently we try to detect a symmetric memory configurations using a magic DCC2_MODIFIED_ENHANCED_DISABLE bit. That bit is either only set on a very specific subset of machines or it just does not exist (it's not mentioned in any public chipset datasheets I've found). As it happens my CL/CTG machines never set said bit, even if I populate the channels with identical sticks.
So let's do the L-shaped memory detection the same way as the desktop variants, ie. just look at the DRAM rank boundary registers to see if both channels have an identical size.
With this my CL/CTG no longer claim L-shaped memory when I use identical sticks. Also tested with non-matching sticks just to make sure the L-shaped memory is still properly detected.
And for completeness let's update the debugfs code to dump the correct set of registers on each platform.
Cc: Chris Wilson chris@chris-wilson.co.uk Signed-off-by: Ville Syrjälä ville.syrjala@linux.intel.com
Did you check this with the swapping igt? I have some vague memories of bug reports where somehow the machine was acting like it's L-shaped memory despite that banks were populated equally. I've iirc tried all kinds of tricks to figure it out, all to absolutely no avail.
Did you have a specific test in mind? I ran a bunch of things that seemed swizzle related. All passed just fine.
gem_tiled_swapping should be the one. It tries to cycle your entire system memory through tiled buffers into swap and out of it.
Passes with symmetric config, fails with L-shaped config (if I hack out the L-shape detection of course). So seems pretty solid.
A kernel based self test that looks at the physical address would still be nice I suppose. Though depending on the size of your RAM sticks figuring out where exactly the switchover from two channels to one channels happens probably requires a bit of work due to the PCI hole/etc.
Both my cl and ctg report this btw: bit6 swizzle for X-tiling = bit9/bit10/bit11 bit6 swizzle for Y-tiling = bit9/bit11 so unfortunately can't be sure the other swizzle modes would be correctly detected.
I think testing-wise this is as good as it gets.
So what do we think about putting this in? Currently this only works by sheer luck more or less. On my machines we have a false positive which is safe now that the pin quirk got fixed, but if some other machines have a false negative then things are not going to go so well.
On Thu, Apr 22, 2021 at 11:49:43AM +0200, Daniel Vetter wrote:
On Wed, Apr 21, 2021 at 06:34:01PM +0300, Ville Syrjala wrote:
From: Ville Syrjälä ville.syrjala@linux.intel.com
Currently we try to detect a symmetric memory configurations using a magic DCC2_MODIFIED_ENHANCED_DISABLE bit. That bit is either only set on a very specific subset of machines or it just does not exist (it's not mentioned in any public chipset datasheets I've found). As it happens my CL/CTG machines never set said bit, even if I populate the channels with identical sticks.
So let's do the L-shaped memory detection the same way as the desktop variants, ie. just look at the DRAM rank boundary registers to see if both channels have an identical size.
With this my CL/CTG no longer claim L-shaped memory when I use identical sticks. Also tested with non-matching sticks just to make sure the L-shaped memory is still properly detected.
And for completeness let's update the debugfs code to dump the correct set of registers on each platform.
Cc: Chris Wilson chris@chris-wilson.co.uk Signed-off-by: Ville Syrjälä ville.syrjala@linux.intel.com
Did you check this with the swapping igt? I have some vague memories of bug reports where somehow the machine was acting like it's L-shaped memory despite that banks were populated equally. I've iirc tried all kinds of tricks to figure it out, all to absolutely no avail.
BTW looking at the patches/dumps in eg. https://bugs.freedesktop.org/show_bug.cgi?id=28813 I can't immediately see a single thing that is actually using the correct register offsets for cl/ctg. So I'm a bit sceptical about how well this was researched in the past.
dri-devel@lists.freedesktop.org
-
Daniel Vetter -
Ville Syrjala -
Ville Syrjälä