From: Jerome Glisse jglisse@redhat.com
Force the use of cached memory when evicting from vram on non agp hardware. Also force write combine on agp hw. This is to insure the minimum cache type change when allocating memory and improving memory eviction especialy on pci/pcie hw.
Signed-off-by: Jerome Glisse jglisse@redhat.com --- drivers/gpu/drm/radeon/radeon_object.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c index b91118c..3f9f3bb 100644 --- a/drivers/gpu/drm/radeon/radeon_object.c +++ b/drivers/gpu/drm/radeon/radeon_object.c @@ -88,10 +88,20 @@ void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) if (domain & RADEON_GEM_DOMAIN_VRAM) rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_VRAM; - if (domain & RADEON_GEM_DOMAIN_GTT) - rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; - if (domain & RADEON_GEM_DOMAIN_CPU) - rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; + if (domain & RADEON_GEM_DOMAIN_GTT) { + if (rbo->rdev->flags & RADEON_IS_AGP) { + rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT; + } else { + rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT; + } + } + if (domain & RADEON_GEM_DOMAIN_CPU) { + if (rbo->rdev->flags & RADEON_IS_AGP) { + rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT; + } else { + rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT; + } + } if (!c) rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; rbo->placement.num_placement = c;
On Wed, Nov 28, 2012 at 1:47 PM, j.glisse@gmail.com wrote:
From: Jerome Glisse jglisse@redhat.com
Force the use of cached memory when evicting from vram on non agp hardware. Also force write combine on agp hw. This is to insure the minimum cache type change when allocating memory and improving memory eviction especialy on pci/pcie hw.
Signed-off-by: Jerome Glisse jglisse@redhat.com
drivers/gpu/drm/radeon/radeon_object.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c index b91118c..3f9f3bb 100644 --- a/drivers/gpu/drm/radeon/radeon_object.c +++ b/drivers/gpu/drm/radeon/radeon_object.c @@ -88,10 +88,20 @@ void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) if (domain & RADEON_GEM_DOMAIN_VRAM) rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_VRAM;
if (domain & RADEON_GEM_DOMAIN_GTT)rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;if (domain & RADEON_GEM_DOMAIN_CPU)rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
if (domain & RADEON_GEM_DOMAIN_GTT) {if (rbo->rdev->flags & RADEON_IS_AGP) {rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT;} else {rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;}}if (domain & RADEON_GEM_DOMAIN_CPU) {if (rbo->rdev->flags & RADEON_IS_AGP) {rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT;} else {rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;}} if (!c) rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; rbo->placement.num_placement = c;-- 1.7.11.7
Anyone ? Bueller ?
Cheers, Jerome
On Wed, Nov 28, 2012 at 1:47 PM, j.glisse@gmail.com wrote:
From: Jerome Glisse jglisse@redhat.com
Force the use of cached memory when evicting from vram on non agp hardware. Also force write combine on agp hw. This is to insure the minimum cache type change when allocating memory and improving memory eviction especialy on pci/pcie hw.
Makes sense to me.
Reviewed-by: Alex Deucher alexander.deucher@amd.com
Signed-off-by: Jerome Glisse jglisse@redhat.com
drivers/gpu/drm/radeon/radeon_object.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c index b91118c..3f9f3bb 100644 --- a/drivers/gpu/drm/radeon/radeon_object.c +++ b/drivers/gpu/drm/radeon/radeon_object.c @@ -88,10 +88,20 @@ void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) if (domain & RADEON_GEM_DOMAIN_VRAM) rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_VRAM;
if (domain & RADEON_GEM_DOMAIN_GTT)rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;if (domain & RADEON_GEM_DOMAIN_CPU)rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
if (domain & RADEON_GEM_DOMAIN_GTT) {if (rbo->rdev->flags & RADEON_IS_AGP) {rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT;} else {rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;}}if (domain & RADEON_GEM_DOMAIN_CPU) {if (rbo->rdev->flags & RADEON_IS_AGP) {rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT;} else {rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;}} if (!c) rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; rbo->placement.num_placement = c;-- 1.7.11.7
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Jerome Glisse