From: Matt Atwood matthew.s.atwood@intel.com
This bit was added to DP Training Aux RD interval with DP 1.3. Via descriptiion of the spec this field indicates the panels true capabilities are described in DPCD address space 02200h through 022FFh.
v2: version comment update v3: version comment correction, commit message update
Signed-off-by: Matt Atwood matthew.s.atwood@intel.com --- include/drm/drm_dp_helper.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index c01564991a9f..a03e65042c8e 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -123,8 +123,9 @@ # define DP_FRAMING_CHANGE_CAP (1 << 1) # define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */
-#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ -# define DP_TRAINING_AUX_RD_MASK 0x7F /* XXX 1.2? */ +#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ +# define DP_TRAINING_AUX_RD_MASK 0x7F /* DP 1.3 */ +# define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT (1 << 7)/* DP 1.3 */
#define DP_ADAPTER_CAP 0x00f /* 1.2 */ # define DP_FORCE_LOAD_SENSE_CAP (1 << 0)
From: Matt Atwood matthew.s.atwood@intel.com
According to DP spec (2.9.3.1 of DP 1.4) if EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in DPCD 02200h through 0220Fh shall contain the DPRX's true capability. These values will match 00000h through 0000Fh, except for DPCD_REV, MAX_LINK_RATE, DOWN_STREAM_PORT_PRESENT.
Read from DPCD once for all 3 values as this is an expensive operation. Spec mentions that all of address space 02200h through 0220Fh should contain the right information however currently only 3 values can differ.
There is no address space in the intel_dp->dpcd struct for addresses 02200h through 0220Fh, and since so much of the data is a identical, simply overwrite the values stored in 00000h through 0000Fh with the values that can be overwritten from addresses 02200h through 0220Fh.
This patch helps with backward compatibility for devices pre DP1.3.
v2: read only dpcd values which can be affected, remove incorrect check, split into drm include changes into separate patch, commit message, verbose debugging statements during overwrite. v3: white space fixes v4: make path dependent on DPCD revision > 1.2
Signed-off-by: Matt Atwood matthew.s.atwood@intel.com --- drivers/gpu/drm/i915/intel_dp.c | 38 +++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index dde92e4af5d3..9d7e1d0b1487 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -3738,6 +3738,44 @@ intel_dp_read_dpcd(struct intel_dp *intel_dp) sizeof(intel_dp->dpcd)) < 0) return false; /* aux transfer failed */
+ if (intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] & + DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT && + intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_13) { + uint8_t dpcd_ext[6]; + + DRM_DEBUG_KMS("DPCD: Extended Receiver Capability Field Present, accessing 02200h through 022FFh\n"); + + if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV, + &dpcd_ext, sizeof(dpcd_ext)) < 0) + return false; /* aux transfer failed */ + + if (memcmp(&intel_dp->dpcd[DP_DPCD_REV], &dpcd_ext[DP_DPCD_REV], + sizeof(u8))) { + DRM_DEBUG_KMS("DPCD: new value for DPCD Revision previous value %2x new value %2x\n", + intel_dp->dpcd[DP_DPCD_REV], + dpcd_ext[DP_DPCD_REV]); + memcpy(&intel_dp->dpcd[DP_DPCD_REV], + &dpcd_ext[DP_DPCD_REV], + sizeof(u8)); + } + if (memcmp(&intel_dp->dpcd[DP_MAX_LINK_RATE], + &dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8))) { + DRM_DEBUG_KMS("DPCD: new value for DPCD Max Link Rate previous value %2x new value %2x\n", + intel_dp->dpcd[DP_MAX_LINK_RATE], + dpcd_ext[DP_MAX_LINK_RATE]); + memcpy(&intel_dp->dpcd[DP_MAX_LINK_RATE], + &dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8)); + } + if (memcmp(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT], + &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT], sizeof(u8))) { + DRM_DEBUG_KMS("DPCD: new value for DPCD Downstream Port Present previous value %2x new value %2x\n", + intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT], + dpcd_ext[DP_DOWNSTREAMPORT_PRESENT]); + memcpy(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT], + &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT], + sizeof(u8)); + } + } DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
return intel_dp->dpcd[DP_DPCD_REV] != 0;
On Fri, Jul 20, 2018 at 09:18:12AM -0700, matthew.s.atwood@intel.com wrote:
From: Matt Atwood matthew.s.atwood@intel.com
According to DP spec (2.9.3.1 of DP 1.4) if EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in DPCD 02200h through 0220Fh shall contain the DPRX's true capability. These values will match 00000h through 0000Fh, except for DPCD_REV, MAX_LINK_RATE, DOWN_STREAM_PORT_PRESENT.
Read from DPCD once for all 3 values as this is an expensive operation. Spec mentions that all of address space 02200h through 0220Fh should contain the right information however currently only 3 values can differ.
There is no address space in the intel_dp->dpcd struct for addresses 02200h through 0220Fh, and since so much of the data is a identical, simply overwrite the values stored in 00000h through 0000Fh with the values that can be overwritten from addresses 02200h through 0220Fh.
This patch helps with backward compatibility for devices pre DP1.3.
v2: read only dpcd values which can be affected, remove incorrect check, split into drm include changes into separate patch, commit message, verbose debugging statements during overwrite. v3: white space fixes v4: make path dependent on DPCD revision > 1.2
Signed-off-by: Matt Atwood matthew.s.atwood@intel.com
drivers/gpu/drm/i915/intel_dp.c | 38 +++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index dde92e4af5d3..9d7e1d0b1487 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -3738,6 +3738,44 @@ intel_dp_read_dpcd(struct intel_dp *intel_dp) sizeof(intel_dp->dpcd)) < 0) return false; /* aux transfer failed */
- if (intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT &&intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_13) {
wrong order... you don't need to read those bits if ! rev >= 1.3
uint8_t dpcd_ext[6];DRM_DEBUG_KMS("DPCD: Extended Receiver Capability Field Present, accessing 02200h through 022FFh\n");if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,&dpcd_ext, sizeof(dpcd_ext)) < 0)return false; /* aux transfer failed */if (memcmp(&intel_dp->dpcd[DP_DPCD_REV], &dpcd_ext[DP_DPCD_REV],sizeof(u8))) {DRM_DEBUG_KMS("DPCD: new value for DPCD Revision previous value %2x new value %2x\n",intel_dp->dpcd[DP_DPCD_REV],dpcd_ext[DP_DPCD_REV]);memcpy(&intel_dp->dpcd[DP_DPCD_REV],&dpcd_ext[DP_DPCD_REV],sizeof(u8));}if (memcmp(&intel_dp->dpcd[DP_MAX_LINK_RATE],&dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8))) {DRM_DEBUG_KMS("DPCD: new value for DPCD Max Link Rate previous value %2x new value %2x\n",intel_dp->dpcd[DP_MAX_LINK_RATE],dpcd_ext[DP_MAX_LINK_RATE]);memcpy(&intel_dp->dpcd[DP_MAX_LINK_RATE],&dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8));}if (memcmp(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],&dpcd_ext[DP_DOWNSTREAMPORT_PRESENT], sizeof(u8))) {DRM_DEBUG_KMS("DPCD: new value for DPCD Downstream Port Present previous value %2x new value %2x\n",intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],dpcd_ext[DP_DOWNSTREAMPORT_PRESENT]);memcpy(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],&dpcd_ext[DP_DOWNSTREAMPORT_PRESENT],sizeof(u8));}} DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
return intel_dp->dpcd[DP_DPCD_REV] != 0;
-- 2.17.1
On Fri, Jul 20, 2018 at 09:18:12AM -0700, matthew.s.atwood@intel.com wrote:
From: Matt Atwood matthew.s.atwood@intel.com
According to DP spec (2.9.3.1 of DP 1.4) if EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in DPCD 02200h through 0220Fh shall contain the DPRX's true capability. These values will match 00000h through 0000Fh, except for DPCD_REV, MAX_LINK_RATE, DOWN_STREAM_PORT_PRESENT.
Read from DPCD once for all 3 values as this is an expensive operation. Spec mentions that all of address space 02200h through 0220Fh should contain the right information however currently only 3 values can differ.
There is no address space in the intel_dp->dpcd struct for addresses 02200h through 0220Fh, and since so much of the data is a identical, simply overwrite the values stored in 00000h through 0000Fh with the values that can be overwritten from addresses 02200h through 0220Fh.
This patch helps with backward compatibility for devices pre DP1.3.
v2: read only dpcd values which can be affected, remove incorrect check, split into drm include changes into separate patch, commit message, verbose debugging statements during overwrite. v3: white space fixes v4: make path dependent on DPCD revision > 1.2
Signed-off-by: Matt Atwood matthew.s.atwood@intel.com
drivers/gpu/drm/i915/intel_dp.c | 38 +++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index dde92e4af5d3..9d7e1d0b1487 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -3738,6 +3738,44 @@ intel_dp_read_dpcd(struct intel_dp *intel_dp) sizeof(intel_dp->dpcd)) < 0) return false; /* aux transfer failed */
- if (intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT &&intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_13) {
Like I had mentioned earlier, this check for DP_DPCD_REV is not required infact if the extended reciever cap field is present its likely that the correct REV is present in the different offset and the original DP_DPCD_REV indicates the legacy or older REV number. This is waht i observed when I tested this earlier on DP 1.4 sink and had to remove this REV check since the original REV register was advertising it as DP 1.1 sink.
Manasi
uint8_t dpcd_ext[6];DRM_DEBUG_KMS("DPCD: Extended Receiver Capability Field Present, accessing 02200h through 022FFh\n");if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,&dpcd_ext, sizeof(dpcd_ext)) < 0)return false; /* aux transfer failed */if (memcmp(&intel_dp->dpcd[DP_DPCD_REV], &dpcd_ext[DP_DPCD_REV],sizeof(u8))) {DRM_DEBUG_KMS("DPCD: new value for DPCD Revision previous value %2x new value %2x\n",intel_dp->dpcd[DP_DPCD_REV],dpcd_ext[DP_DPCD_REV]);memcpy(&intel_dp->dpcd[DP_DPCD_REV],&dpcd_ext[DP_DPCD_REV],sizeof(u8));}if (memcmp(&intel_dp->dpcd[DP_MAX_LINK_RATE],&dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8))) {DRM_DEBUG_KMS("DPCD: new value for DPCD Max Link Rate previous value %2x new value %2x\n",intel_dp->dpcd[DP_MAX_LINK_RATE],dpcd_ext[DP_MAX_LINK_RATE]);memcpy(&intel_dp->dpcd[DP_MAX_LINK_RATE],&dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8));}if (memcmp(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],&dpcd_ext[DP_DOWNSTREAMPORT_PRESENT], sizeof(u8))) {DRM_DEBUG_KMS("DPCD: new value for DPCD Downstream Port Present previous value %2x new value %2x\n",intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],dpcd_ext[DP_DOWNSTREAMPORT_PRESENT]);memcpy(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],&dpcd_ext[DP_DOWNSTREAMPORT_PRESENT],sizeof(u8));}} DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
return intel_dp->dpcd[DP_DPCD_REV] != 0;
-- 2.17.1
On Fri, Jul 20, 2018 at 09:18:11AM -0700, matthew.s.atwood@intel.com wrote:
From: Matt Atwood matthew.s.atwood@intel.com
This bit was added to DP Training Aux RD interval with DP 1.3. Via descriptiion of the spec this field indicates the panels true capabilities are described in DPCD address space 02200h through 022FFh.
v2: version comment update v3: version comment correction, commit message update
Signed-off-by: Matt Atwood matthew.s.atwood@intel.com
include/drm/drm_dp_helper.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index c01564991a9f..a03e65042c8e 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -123,8 +123,9 @@ # define DP_FRAMING_CHANGE_CAP (1 << 1) # define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */
-#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ -# define DP_TRAINING_AUX_RD_MASK 0x7F /* XXX 1.2? */ +#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ +# define DP_TRAINING_AUX_RD_MASK 0x7F /* DP 1.3 */ +# define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT (1 << 7)/* DP 1.3 */
^ missing a space here
#define DP_ADAPTER_CAP 0x00f /* 1.2 */
# define DP_FORCE_LOAD_SENSE_CAP (1 << 0)
2.17.1
dri-devel@lists.freedesktop.org
-
Manasi Navare -
matthew.s.atwood＠intel.com -
Rodrigo Vivi