Hi,

On 12/7/21 17:51, Ramalingam C wrote:

From: Stuart Summers stuart.summers@intel.com

Add a new platform flag, has_64k_pages, for platforms supporting base page sizes of 64k.

Signed-off-by: Stuart Summers stuart.summers@intel.com Signed-off-by: Ramalingam C ramalingam.c@intel.com Reviewed-by: Lucas De Marchi lucas.demarchi@intel.com

---

drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_pci.c | 2 ++ drivers/gpu/drm/i915/intel_device_info.h | 1 + 3 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 85bb8d3107f0..6132163e1cb3 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1528,6 +1528,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_MSLICES(dev_priv) \ (INTEL_INFO(dev_priv)->has_mslices)

+#define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)

Could we please have some documentation of the exact meaning of this flag. Like, smallest page size of LMEM is 64K. Hardware supports 64k pages etc?

for future reference.

/Thomas

#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)

#define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i)) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 6aaa7c644c9b..634282edadb7 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -1029,6 +1029,7 @@ static const struct intel_device_info xehpsdv_info = { DGFX_FEATURES, PLATFORM(INTEL_XEHPSDV), .display = { },

• .has_64k_pages = 1, .pipe_mask = 0, .platform_engine_mask = BIT(RCS0) | BIT(BCS0) |

@@ -1047,6 +1048,7 @@ static const struct intel_device_info dg2_info = { .graphics.rel = 55, .media.rel = 55, PLATFORM(INTEL_DG2),

• .has_64k_pages = 1, .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VECS1) |

diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 669f0d26c3c3..f38ac5bd837b 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -123,6 +123,7 @@ enum intel_ppgtt_type { func(is_dgfx); \ /* Keep has_* in alphabetical order */ \ func(has_64bit_reloc); \

• func(has_64k_pages); \ func(gpu_reset_clobbers_display); \ func(has_reset_engine); \ func(has_global_mocs); \

On 12/8/21 13:59, Matthew Auld wrote:

On Wed, 8 Dec 2021 at 12:43, Thomas Hellström (Intel) thomas_os@shipmail.org wrote:

...

Hi,

On 12/7/21 17:51, Ramalingam C wrote:

...

From: Stuart Summers stuart.summers@intel.com

Add a new platform flag, has_64k_pages, for platforms supporting base page sizes of 64k.

Signed-off-by: Stuart Summers stuart.summers@intel.com Signed-off-by: Ramalingam C ramalingam.c@intel.com Reviewed-by: Lucas De Marchi lucas.demarchi@intel.com

---

drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_pci.c | 2 ++ drivers/gpu/drm/i915/intel_device_info.h | 1 + 3 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 85bb8d3107f0..6132163e1cb3 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1528,6 +1528,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_MSLICES(dev_priv) \ (INTEL_INFO(dev_priv)->has_mslices)

+#define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)

Could we please have some documentation of the exact meaning of this flag. Like, smallest page size of LMEM is 64K. Hardware supports 64k pages etc?

Something like: "Set if the device requires 64K GTT page sizes or larger for device local memory access. Also implies that we require or at least support the compact PT layout for the ppGTT when using 64K GTT pages."

Sounds great.

Thanks,

Thomas

On 12/7/21 17:51, Ramalingam C wrote:

From: Matthew Auld matthew.auld@intel.com

LMEM should be allocated at 64K granularity, since 4K page support will eventually be dropped for LMEM when using the PPGTT.

Signed-off-by: Matthew Auld matthew.auld@intel.com Signed-off-by: Stuart Summers stuart.summers@intel.com Signed-off-by: Ramalingam C ramalingam.c@intel.com Cc: Joonas Lahtinen joonas.lahtinen@linux.intel.com Cc: Rodrigo Vivi rodrigo.vivi@intel.com Reviewed-by: Lucas De Marchi lucas.demarchi@intel.com

Reviewed-by: Thomas Hellstrom thomas.hellstrom@linux.intel.com

---

drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 6 +++++- drivers/gpu/drm/i915/gt/intel_region_lmem.c | 5 ++++- 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c index bce03d74a0b4..ba90ab47d838 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c @@ -780,6 +780,7 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type, struct intel_uncore *uncore = &i915->uncore; struct pci_dev *pdev = to_pci_dev(i915->drm.dev); struct intel_memory_region *mem;

• resource_size_t min_page_size; resource_size_t io_start; resource_size_t lmem_size; u64 lmem_base;

@@ -791,8 +792,11 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type, lmem_size = pci_resource_len(pdev, 2) - lmem_base; io_start = pci_resource_start(pdev, 2) + lmem_base;

• min_page_size = HAS_64K_PAGES(i915) ? I915_GTT_PAGE_SIZE_64K :

• 				I915_GTT_PAGE_SIZE_4K;
  

• mem = intel_memory_region_create(i915, lmem_base, lmem_size,

• 			 I915_GTT_PAGE_SIZE_4K, io_start,
  

• 			 min_page_size, io_start,
  		 type, instance,
  		 &i915_region_stolen_lmem_ops);
  

  if (IS_ERR(mem))

diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c index 9ea49e0a27c0..fde2dcb59809 100644 --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c @@ -197,6 +197,7 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt) struct intel_uncore *uncore = gt->uncore; struct pci_dev *pdev = to_pci_dev(i915->drm.dev); struct intel_memory_region *mem;

• resource_size_t min_page_size; resource_size_t io_start; resource_size_t lmem_size; int err;

@@ -211,10 +212,12 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt) if (GEM_WARN_ON(lmem_size > pci_resource_len(pdev, 2))) return ERR_PTR(-ENODEV);

• min_page_size = HAS_64K_PAGES(i915) ? I915_GTT_PAGE_SIZE_64K :

• 				I915_GTT_PAGE_SIZE_4K;
  

  mem = intel_memory_region_create(i915, 0, lmem_size,

• 			 I915_GTT_PAGE_SIZE_4K,
  

• 			 min_page_size,
  		 io_start,
  		 INTEL_MEMORY_LOCAL,
  		 0,
  

On 12/7/21 17:51, Ramalingam C wrote:

From: Matthew Auld matthew.auld@intel.com

On some platforms the hw has dropped support for 4K GTT pages when dealing with LMEM, and due to the design of 64K GTT pages in the hw, we can only mark the *entire* page-table as operating in 64K GTT mode, since the enable bit is still on the pde, and not the pte. And since we we

we we

still need to allow 4K GTT pages for SMEM objects, we can't have a "normal" 4K page-table with scratch pointing to LMEM, since that's undefined from the hw pov. The simplest solution is to just move the 64K scratch page to SMEM on such platforms and call it a day, since that should work for all configurations.

Signed-off-by: Matthew Auld matthew.auld@intel.com Signed-off-by: Ramalingam C ramalingam.c@intel.com

LGTM.

Reviewed-by: Thomas Hellström thomas.hellstrom@linux.intel.com

---

drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 1 + drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 23 +++++++++++++++++++++-- drivers/gpu/drm/i915/gt/intel_ggtt.c | 3 +++ drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +- drivers/gpu/drm/i915/gt/intel_gtt.h | 2 ++ drivers/gpu/drm/i915/selftests/mock_gtt.c | 2 ++ 6 files changed, 30 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c index 4a166d25fe60..c0d149f04949 100644 --- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c @@ -454,6 +454,7 @@ struct i915_ppgtt *gen6_ppgtt_create(struct intel_gt *gt) ppgtt->base.vm.cleanup = gen6_ppgtt_cleanup;

ppgtt->base.vm.alloc_pt_dma = alloc_pt_dma;

• ppgtt->base.vm.alloc_scratch_dma = alloc_pt_dma; ppgtt->base.vm.pte_encode = ggtt->vm.pte_encode;

  err = gen6_ppgtt_init_scratch(ppgtt);

diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c index 95c02096a61b..b012c50f7ce7 100644 --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c @@ -776,10 +776,29 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt, */ ppgtt->vm.has_read_only = !IS_GRAPHICS_VER(gt->i915, 11, 12);

• if (HAS_LMEM(gt->i915))

• if (HAS_LMEM(gt->i915)) { ppgtt->vm.alloc_pt_dma = alloc_pt_lmem;

• else

• /*
  

•  * On some platforms the hw has dropped support for 4K GTT pages
  

•  * when dealing with LMEM, and due to the design of 64K GTT
  

•  * pages in the hw, we can only mark the *entire* page-table as
  

•  * operating in 64K GTT mode, since the enable bit is still on
  

•  * the pde, and not the pte. And since we still need to allow
  

•  * 4K GTT pages for SMEM objects, we can't have a "normal" 4K
  

•  * page-table with scratch pointing to LMEM, since that's
  

•  * undefined from the hw pov. The simplest solution is to just
  

•  * move the 64K scratch page to SMEM on such platforms and call
  

•  * it a day, since that should work for all configurations.
  

•  */
  

• if (HAS_64K_PAGES(gt->i915))
  

• 	ppgtt->vm.alloc_scratch_dma = alloc_pt_dma;
  

• else
  

• 	ppgtt->vm.alloc_scratch_dma = alloc_pt_lmem;
  

• } else { ppgtt->vm.alloc_pt_dma = alloc_pt_dma;

• ppgtt->vm.alloc_scratch_dma = alloc_pt_dma;
  

• }

  err = gen8_init_scratch(&ppgtt->vm); if (err)

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c index cbc6d2b1fd9e..d85a1050f4a8 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c @@ -941,6 +941,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt) size = gen8_get_total_gtt_size(snb_gmch_ctl);

ggtt->vm.alloc_pt_dma = alloc_pt_dma;

• ggtt->vm.alloc_scratch_dma = alloc_pt_dma; ggtt->vm.lmem_pt_obj_flags = I915_BO_ALLOC_PM_EARLY;

  ggtt->vm.total = (size / sizeof(gen8_pte_t)) * I915_GTT_PAGE_SIZE;

@@ -1094,6 +1095,7 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt) ggtt->vm.total = (size / sizeof(gen6_pte_t)) * I915_GTT_PAGE_SIZE;

ggtt->vm.alloc_pt_dma = alloc_pt_dma;

• ggtt->vm.alloc_scratch_dma = alloc_pt_dma;

  ggtt->vm.clear_range = nop_clear_range; if (!HAS_FULL_PPGTT(i915) || intel_scanout_needs_vtd_wa(i915))

@@ -1146,6 +1148,7 @@ static int i915_gmch_probe(struct i915_ggtt *ggtt) (struct resource)DEFINE_RES_MEM(gmadr_base, ggtt->mappable_end);

ggtt->vm.alloc_pt_dma = alloc_pt_dma;

• ggtt->vm.alloc_scratch_dma = alloc_pt_dma;

  if (needs_idle_maps(i915)) { drm_notice(&i915->drm,

diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c index 0dd254cb1f69..1428e2b9075a 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.c +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c @@ -301,7 +301,7 @@ int setup_scratch_page(struct i915_address_space *vm) do { struct drm_i915_gem_object *obj;

• obj = vm->alloc_pt_dma(vm, size);
  

• obj = vm->alloc_scratch_dma(vm, size);
  

  if (IS_ERR(obj)) goto skip;

diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h index 51afe66d00f2..15b98321e89a 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.h +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h @@ -268,6 +268,8 @@ struct i915_address_space {

struct drm_i915_gem_object * (*alloc_pt_dma)(struct i915_address_space *vm, int sz);

• struct drm_i915_gem_object *

• (*alloc_scratch_dma)(struct i915_address_space *vm, int sz);
  
  

  u64 (*pte_encode)(dma_addr_t addr, enum i915_cache_level level,

diff --git a/drivers/gpu/drm/i915/selftests/mock_gtt.c b/drivers/gpu/drm/i915/selftests/mock_gtt.c index cc047ec594f9..32ca8962d0ab 100644 --- a/drivers/gpu/drm/i915/selftests/mock_gtt.c +++ b/drivers/gpu/drm/i915/selftests/mock_gtt.c @@ -78,6 +78,7 @@ struct i915_ppgtt *mock_ppgtt(struct drm_i915_private *i915, const char *name) i915_address_space_init(&ppgtt->vm, VM_CLASS_PPGTT);

ppgtt->vm.alloc_pt_dma = alloc_pt_dma;

• ppgtt->vm.alloc_scratch_dma = alloc_pt_dma;

  ppgtt->vm.clear_range = mock_clear_range; ppgtt->vm.insert_page = mock_insert_page;

@@ -118,6 +119,7 @@ void mock_init_ggtt(struct drm_i915_private *i915, struct i915_ggtt *ggtt) ggtt->vm.total = 4096 * PAGE_SIZE;

ggtt->vm.alloc_pt_dma = alloc_pt_dma;

• ggtt->vm.alloc_scratch_dma = alloc_pt_dma;

  ggtt->vm.clear_range = mock_clear_range; ggtt->vm.insert_page = mock_insert_page;

On 12/7/21 17:51, Ramalingam C wrote:

From: Matthew Auld matthew.auld@intel.com

If the device needs 64K minimum GTT pages for device local-memory, like on XEHPSDV, then we need to fail the allocation if we can't meet it, instead of falling back to 4K pages, otherwise we can't safely support the insertion of device local-memory pages for this vm, since the HW expects the correct physical alignment and size for every PTE, if we mark the page-table as 64K GTT mode.

Signed-off-by: Matthew Auld matthew.auld@intel.com Signed-off-by: Ramalingam C ramalingam.c@intel.com

---

drivers/gpu/drm/i915/gt/intel_gtt.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c index 1428e2b9075a..869b771a5fdc 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.c +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c @@ -337,6 +337,18 @@ int setup_scratch_page(struct i915_address_space *vm) if (size == I915_GTT_PAGE_SIZE_4K) return -ENOMEM;

• /*
  

•  * If we need 64K minimum GTT pages for device local-memory,
  

•  * like on XEHPSDV, then we need to fail the allocation here,
  

•  * otherwise we can't safely support the insertion of
  

•  * local-memory pages for this vm, since the HW expects the
  

•  * correct physical alignment and size when the page-table is
  

•  * operating in 64K GTT mode, which includes any scratch PTEs,
  

•  * since userpsace can still touch them.
  

s/userpsace/userspace/

LGTM.

Reviewed-by: Thomas Hellström thomas.hellstrom@linux.intel.com

•  */
  

• if (HAS_64K_PAGES(vm->i915))
  

• 	return -ENOMEM;
  

• size = I915_GTT_PAGE_SIZE_4K; } while (1); }