On 2021-07-21 19:42, Bjorn Andersson wrote:

reg was defined as one region covering the entire DP block, but the memory map is actually split in 4 regions and obviously the size of these regions differs between platforms.

Switch the reg to require that all four regions are specified instead. It is expected that the implementation will handle existing DTBs, even though the schema defines the new layout.

Signed-off-by: Bjorn Andersson bjorn.andersson@linaro.org

---

.../bindings/display/msm/dp-controller.yaml | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index 64d8d9e5e47a..a6e41be038fc 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -19,7 +19,11 @@ properties: - qcom,sc7180-dp

reg:

• maxItems: 1

• items:

•  - description: ahb register block
  

•  - description: aux register block
  

•  - description: link register block
  

•  - description: p0 register block
  

Do you also want to add the p1 register block here?

interrupts: maxItems: 1 @@ -100,7 +104,10 @@ examples:

 displayport-controller@ae90000 {
     compatible = "qcom,sc7180-dp";

•    reg = <0xae90000 0x1400>;
  

•    reg = <0xae90000 0x200>,
  

•          <0xae90200 0x200>,
  

•          <0xae90400 0xc00>,
  

•          <0xae91000 0x400>;
  

here too?

     interrupt-parent = <&mdss>;
     interrupts = <12>;
     clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,

On 2021-07-21 19:42, Bjorn Andersson wrote:

The non-devres version of ioremap is used, which requires manual cleanup. But the code paths leading here is mixed with other devres users, so rely on this for ioremap as well to simplify the code.

Signed-off-by: Bjorn Andersson bjorn.andersson@linaro.org

Reviewed-by: Abhinav Kumar abhinavk@codeaurora.org

---

drivers/gpu/drm/msm/dp/dp_parser.c | 29 ++++------------------------- 1 file changed, 4 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c b/drivers/gpu/drm/msm/dp/dp_parser.c index 0519dd3ac3c3..c064ced78278 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.c +++ b/drivers/gpu/drm/msm/dp/dp_parser.c @@ -32,7 +32,7 @@ static int msm_dss_ioremap(struct platform_device *pdev, }

io_data->len = (u32)resource_size(res);

• io_data->base = ioremap(res->start, io_data->len);

• io_data->base = devm_ioremap(&pdev->dev, res->start, io_data->len); if (!io_data->base) { DRM_ERROR("%pS->%s: ioremap failed\n", __builtin_return_address(0), __func__);

@@ -42,22 +42,6 @@ static int msm_dss_ioremap(struct platform_device *pdev, return 0; }

-static void msm_dss_iounmap(struct dss_io_data *io_data) -{

• if (io_data->base) {

• iounmap(io_data->base);
  

• io_data->base = NULL;
  

• }
• io_data->len = 0;

-}

-static void dp_parser_unmap_io_resources(struct dp_parser *parser) -{

• struct dp_io *io = &parser->io;
• msm_dss_iounmap(&io->dp_controller);

-}

static int dp_parser_ctrl_res(struct dp_parser *parser) { int rc = 0; @@ -67,19 +51,14 @@ static int dp_parser_ctrl_res(struct dp_parser *parser) rc = msm_dss_ioremap(pdev, &io->dp_controller); if (rc) { DRM_ERROR("unable to remap dp io resources, rc=%d\n", rc);

• goto err;
  

• return rc;
  

  }

  io->phy = devm_phy_get(&pdev->dev, "dp");

• if (IS_ERR(io->phy)) {

• rc = PTR_ERR(io->phy);
  

• goto err;
  

• }

• if (IS_ERR(io->phy))

• return PTR_ERR(io->phy);
  
  

  return 0;

-err:

• dp_parser_unmap_io_resources(parser);
• return rc;

}

static int dp_parser_misc(struct dp_parser *parser)

Quoting Bjorn Andersson (2021-07-21 19:42:25)

In order to deal with multiple memory ranges in the following commit change the ioremap wrapper to not poke directly into the dss_io_data struct.

Signed-off-by: Bjorn Andersson bjorn.andersson@linaro.org

drivers/gpu/drm/msm/dp/dp_parser.c | 28 ++++++++++++++-------------- drivers/gpu/drm/msm/dp/dp_parser.h | 2 +- 2 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c b/drivers/gpu/drm/msm/dp/dp_parser.c index c064ced78278..e68dacef547c 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.c +++ b/drivers/gpu/drm/msm/dp/dp_parser.c @@ -19,39 +19,39 @@ static const struct dp_regulator_cfg sdm845_dp_reg_cfg = { }, };

-static int msm_dss_ioremap(struct platform_device *pdev,

•                           struct dss_io_data *io_data)
  

+static void __iomem *dp_ioremap(struct platform_device *pdev, int idx, size_t *len) { struct resource *res = NULL;

Can we drop assignment to NULL too?

•   void __iomem *base;
  
  

•   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  

•   res = platform_get_resource(pdev, IORESOURCE_MEM, idx);
    if (!res) {
            DRM_ERROR("%pS->%s: msm_dss_get_res failed\n",
                    __builtin_return_address(0), __func__);
  

•           return -ENODEV;
  

•           return ERR_PTR(-ENODEV);
    }
  
  

•   io_data->len = (u32)resource_size(res);
  

•   io_data->base = devm_ioremap(&pdev->dev, res->start, io_data->len);
  

•   if (!io_data->base) {
  

•   base = devm_ioremap_resource(&pdev->dev, res);
  

•   if (!base) {
  

devm_ioremap_resource() returns an ERR_PTR on failure, not NULL.

            DRM_ERROR("%pS->%s: ioremap failed\n",
                    __builtin_return_address(0), __func__);

•           return -EIO;
  

•           return ERR_PTR(-EIO);
    }
  
  

•   return 0;
  

•   *len = resource_size(res);
  

•   return base;
  

}

static int dp_parser_ctrl_res(struct dp_parser *parser) {

•   int rc = 0;
    struct platform_device *pdev = parser->pdev;
    struct dp_io *io = &parser->io;
  

•   struct dss_io_data *dss = &io->dp_controller;
  
  

•   rc = msm_dss_ioremap(pdev, &io->dp_controller);
  

•   if (rc) {
  

•           DRM_ERROR("unable to remap dp io resources, rc=%d\n", rc);
  

•           return rc;
  

•   dss->base = dp_ioremap(pdev, 0, &dss->len);
  

•   if (IS_ERR(dss->base)) {
  

•           DRM_ERROR("unable to remap dp io region: %pe\n", dss->base);
  

•           return PTR_ERR(dss->base);
    }
  
    io->phy = devm_phy_get(&pdev->dev, "dp");
  

On 2021-07-21 19:42, Bjorn Andersson wrote:

Not all platforms has DP_P0 at offset 0x1000 from the beginning of the DP block. So dss_io_data into representing each of the sub-regions, to make it possible in the next patch to specify each of the sub-regions individually.

Signed-off-by: Bjorn Andersson bjorn.andersson@linaro.org

Same comments as Stephen on this https://patchwork.freedesktop.org/patch/445655/

---

drivers/gpu/drm/msm/dp/dp_catalog.c | 64 +++++++++-------------------- drivers/gpu/drm/msm/dp/dp_parser.c | 30 ++++++++++++-- drivers/gpu/drm/msm/dp/dp_parser.h | 10 ++++- 3 files changed, 54 insertions(+), 50 deletions(-)

diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c index ca96e3514790..23458b0ddc37 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -24,15 +24,6 @@ #define DP_INTERRUPT_STATUS_ACK_SHIFT 1 #define DP_INTERRUPT_STATUS_MASK_SHIFT 2

-#define MSM_DP_CONTROLLER_AHB_OFFSET 0x0000 -#define MSM_DP_CONTROLLER_AHB_SIZE 0x0200 -#define MSM_DP_CONTROLLER_AUX_OFFSET 0x0200 -#define MSM_DP_CONTROLLER_AUX_SIZE 0x0200 -#define MSM_DP_CONTROLLER_LINK_OFFSET 0x0400 -#define MSM_DP_CONTROLLER_LINK_SIZE 0x0C00 -#define MSM_DP_CONTROLLER_P0_OFFSET 0x1000 -#define MSM_DP_CONTROLLER_P0_SIZE 0x0400

#define DP_INTERRUPT_STATUS1 \ (DP_INTR_AUX_I2C_DONE| \ DP_INTR_WRONG_ADDR | DP_INTR_TIMEOUT | \ @@ -66,82 +57,77 @@ void dp_catalog_snapshot(struct dp_catalog *dp_catalog, struct msm_disp_state *d { struct dp_catalog_private *catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog);

• struct dss_io_data *dss = &catalog->io->dp_controller;

• msm_disp_snapshot_add_block(disp_state,

catalog->io->dp_controller.len,

• 	catalog->io->dp_controller.base, "dp_ctrl");
  

• msm_disp_snapshot_add_block(disp_state, dss->ahb_len, dss->ahb,

"dp_ahb");

• msm_disp_snapshot_add_block(disp_state, dss->aux_len, dss->aux,

"dp_aux");

• msm_disp_snapshot_add_block(disp_state, dss->link_len, dss->link,

"dp_link");

• msm_disp_snapshot_add_block(disp_state, dss->p0_len, dss->p0,

"dp_p0"); }

static inline u32 dp_read_aux(struct dp_catalog_private *catalog, u32 offset) {

• offset += MSM_DP_CONTROLLER_AUX_OFFSET;
• return readl_relaxed(catalog->io->dp_controller.base + offset);

• return readl_relaxed(catalog->io->dp_controller.aux + offset);

}

static inline void dp_write_aux(struct dp_catalog_private *catalog, u32 offset, u32 data) {

• offset += MSM_DP_CONTROLLER_AUX_OFFSET; /*
  • To make sure aux reg writes happens before any other operation,
  • this function uses writel() instread of writel_relaxed()
  */
• writel(data, catalog->io->dp_controller.base + offset);

• writel(data, catalog->io->dp_controller.aux + offset);

}

static inline u32 dp_read_ahb(struct dp_catalog_private *catalog, u32 offset) {

• offset += MSM_DP_CONTROLLER_AHB_OFFSET;
• return readl_relaxed(catalog->io->dp_controller.base + offset);

• return readl_relaxed(catalog->io->dp_controller.ahb + offset);

}

static inline void dp_write_ahb(struct dp_catalog_private *catalog, u32 offset, u32 data) {

• offset += MSM_DP_CONTROLLER_AHB_OFFSET; /*
  • To make sure phy reg writes happens before any other operation,
  • this function uses writel() instread of writel_relaxed()
  */
• writel(data, catalog->io->dp_controller.base + offset);

• writel(data, catalog->io->dp_controller.ahb + offset);

}

static inline void dp_write_p0(struct dp_catalog_private *catalog, u32 offset, u32 data) {

• offset += MSM_DP_CONTROLLER_P0_OFFSET; /*
  • To make sure interface reg writes happens before any other

operation, * this function uses writel() instread of writel_relaxed() */

• writel(data, catalog->io->dp_controller.base + offset);

• writel(data, catalog->io->dp_controller.p0 + offset);

}

static inline u32 dp_read_p0(struct dp_catalog_private *catalog, u32 offset) {

• offset += MSM_DP_CONTROLLER_P0_OFFSET; /*
  • To make sure interface reg writes happens before any other

operation, * this function uses writel() instread of writel_relaxed() */

• return readl_relaxed(catalog->io->dp_controller.base + offset);

• return readl_relaxed(catalog->io->dp_controller.p0 + offset);

}

static inline u32 dp_read_link(struct dp_catalog_private *catalog, u32 offset) {

• offset += MSM_DP_CONTROLLER_LINK_OFFSET;
• return readl_relaxed(catalog->io->dp_controller.base + offset);

• return readl_relaxed(catalog->io->dp_controller.link + offset);

}

static inline void dp_write_link(struct dp_catalog_private *catalog, u32 offset, u32 data) {

• offset += MSM_DP_CONTROLLER_LINK_OFFSET; /*
  • To make sure link reg writes happens before any other operation,
  • this function uses writel() instread of writel_relaxed()
  */
• writel(data, catalog->io->dp_controller.base + offset);

• writel(data, catalog->io->dp_controller.link + offset);

}

/* aux related catalog functions */ @@ -276,29 +262,21 @@ static void dump_regs(void __iomem *base, int len)

void dp_catalog_dump_regs(struct dp_catalog *dp_catalog) {

• u32 offset, len; struct dp_catalog_private *catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog);

• struct dss_io_data *io = &catalog->io->dp_controller;

  pr_info("AHB regs\n");

• offset = MSM_DP_CONTROLLER_AHB_OFFSET;
• len = MSM_DP_CONTROLLER_AHB_SIZE;
• dump_regs(catalog->io->dp_controller.base + offset, len);

• dump_regs(io->ahb, io->ahb_len);

  pr_info("AUXCLK regs\n");

• offset = MSM_DP_CONTROLLER_AUX_OFFSET;
• len = MSM_DP_CONTROLLER_AUX_SIZE;
• dump_regs(catalog->io->dp_controller.base + offset, len);

• dump_regs(io->aux, io->aux_len);

  pr_info("LCLK regs\n");

• offset = MSM_DP_CONTROLLER_LINK_OFFSET;
• len = MSM_DP_CONTROLLER_LINK_SIZE;
• dump_regs(catalog->io->dp_controller.base + offset, len);

• dump_regs(io->link, io->link_len);

  pr_info("P0CLK regs\n");

• offset = MSM_DP_CONTROLLER_P0_OFFSET;
• len = MSM_DP_CONTROLLER_P0_SIZE;
• dump_regs(catalog->io->dp_controller.base + offset, len);

• dump_regs(io->p0, io->p0_len);

}

u32 dp_catalog_aux_get_irq(struct dp_catalog *dp_catalog) @@ -492,8 +470,7 @@ int dp_catalog_ctrl_set_pattern(struct dp_catalog *dp_catalog, bit = BIT(pattern - 1) << DP_MAINLINK_READY_LINK_TRAINING_SHIFT;

/* Poll for mainlink ready status */

• ret = readx_poll_timeout(readl, catalog->io->dp_controller.base +

• 			MSM_DP_CONTROLLER_LINK_OFFSET +
  

• ret = readx_poll_timeout(readl, catalog->io->dp_controller.link + REG_DP_MAINLINK_READY, data, data & bit, POLLING_SLEEP_US, POLLING_TIMEOUT_US);

@@ -540,8 +517,7 @@ bool dp_catalog_ctrl_mainlink_ready(struct dp_catalog *dp_catalog) struct dp_catalog_private, dp_catalog);

/* Poll for mainlink ready status */

• ret = readl_poll_timeout(catalog->io->dp_controller.base +

• 		MSM_DP_CONTROLLER_LINK_OFFSET +
  

• ret = readl_poll_timeout(catalog->io->dp_controller.link + REG_DP_MAINLINK_READY, data, data & DP_MAINLINK_READY_FOR_VIDEO, POLLING_SLEEP_US, POLLING_TIMEOUT_US);

diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c b/drivers/gpu/drm/msm/dp/dp_parser.c index e68dacef547c..1a10901ae574 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.c +++ b/drivers/gpu/drm/msm/dp/dp_parser.c @@ -11,6 +11,15 @@ #include "dp_parser.h" #include "dp_reg.h"

+#define DP_DEFAULT_AHB_OFFSET 0x0000 +#define DP_DEFAULT_AHB_SIZE 0x0200 +#define DP_DEFAULT_AUX_OFFSET 0x0200 +#define DP_DEFAULT_AUX_SIZE 0x0200 +#define DP_DEFAULT_LINK_OFFSET 0x0400 +#define DP_DEFAULT_LINK_SIZE 0x0C00 +#define DP_DEFAULT_P0_OFFSET 0x1000 +#define DP_DEFAULT_P0_SIZE 0x0400

static const struct dp_regulator_cfg sdm845_dp_reg_cfg = { .num = 2, .regs = { @@ -48,12 +57,25 @@ static int dp_parser_ctrl_res(struct dp_parser *parser) struct dp_io *io = &parser->io; struct dss_io_data *dss = &io->dp_controller;

• dss->base = dp_ioremap(pdev, 0, &dss->len);
• if (IS_ERR(dss->base)) {

• DRM_ERROR("unable to remap dp io region: %pe\n", dss->base);
  

• return PTR_ERR(dss->base);
  

• dss->ahb = dp_ioremap(pdev, 0, &dss->ahb_len);

• if (IS_ERR(dss->ahb)) {

• DRM_ERROR("unable to remap ahb region: %pe\n", dss->ahb);
  

• return PTR_ERR(dss->ahb);
  

  }

• if (dss->ahb_len < DP_DEFAULT_P0_OFFSET + DP_DEFAULT_P0_SIZE) {

• DRM_ERROR("legacy memory region not large enough\n");
  

• return -EINVAL;
  

• }

• dss->ahb_len = DP_DEFAULT_AHB_SIZE;

• dss->aux = dss->ahb + DP_DEFAULT_AUX_OFFSET;

• dss->aux_len = DP_DEFAULT_AUX_SIZE;

• dss->link = dss->ahb + DP_DEFAULT_LINK_OFFSET;

• dss->link_len = DP_DEFAULT_LINK_SIZE;

• dss->p0 = dss->ahb + DP_DEFAULT_P0_OFFSET;

• dss->p0_len = DP_DEFAULT_P0_SIZE;

• io->phy = devm_phy_get(&pdev->dev, "dp"); if (IS_ERR(io->phy)) return PTR_ERR(io->phy);

diff --git a/drivers/gpu/drm/msm/dp/dp_parser.h b/drivers/gpu/drm/msm/dp/dp_parser.h index dc62e70b1640..3266b529c090 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.h +++ b/drivers/gpu/drm/msm/dp/dp_parser.h @@ -26,8 +26,14 @@ enum dp_pm_type { };

struct dss_io_data {

• size_t len;
• void __iomem *base;

• void __iomem *ahb;
• size_t ahb_len;
• void __iomem *aux;
• size_t aux_len;
• void __iomem *link;
• size_t link_len;
• void __iomem *p0;
• size_t p0_len;

};

static inline const char *dp_parser_pm_name(enum dp_pm_type module)