The value of pipe_id and queue_id are not used under certain circumstances, so just delete.
Signed-off-by: Tian Tao tiantao6@hisilicon.com --- drivers/gpu/drm/radeon/cik.c | 4 ---- 1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index 8b7a4f7..42a8afa 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c @@ -7948,8 +7948,6 @@ int cik_irq_process(struct radeon_device *rdev) DRM_ERROR("Illegal register access in command stream\n"); /* XXX check the bitfield order! */ me_id = (ring_id & 0x60) >> 5; - pipe_id = (ring_id & 0x18) >> 3; - queue_id = (ring_id & 0x7) >> 0; switch (me_id) { case 0: /* This results in a full GPU reset, but all we need to do is soft @@ -7971,8 +7969,6 @@ int cik_irq_process(struct radeon_device *rdev) DRM_ERROR("Illegal instruction in command stream\n"); /* XXX check the bitfield order! */ me_id = (ring_id & 0x60) >> 5; - pipe_id = (ring_id & 0x18) >> 3; - queue_id = (ring_id & 0x7) >> 0; switch (me_id) { case 0: /* This results in a full GPU reset, but all we need to do is soft
On Mon, Apr 12, 2021 at 11:26 PM Tian Tao tiantao6@hisilicon.com wrote:
The value of pipe_id and queue_id are not used under certain circumstances, so just delete.
Signed-off-by: Tian Tao tiantao6@hisilicon.com
Applied. Thanks!
Alex
drivers/gpu/drm/radeon/cik.c | 4 ---- 1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index 8b7a4f7..42a8afa 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c @@ -7948,8 +7948,6 @@ int cik_irq_process(struct radeon_device *rdev) DRM_ERROR("Illegal register access in command stream\n"); /* XXX check the bitfield order! */ me_id = (ring_id & 0x60) >> 5;
pipe_id = (ring_id & 0x18) >> 3;
queue_id = (ring_id & 0x7) >> 0; switch (me_id) { case 0: /* This results in a full GPU reset, but all we need to do is soft
@@ -7971,8 +7969,6 @@ int cik_irq_process(struct radeon_device *rdev) DRM_ERROR("Illegal instruction in command stream\n"); /* XXX check the bitfield order! */ me_id = (ring_id & 0x60) >> 5;
pipe_id = (ring_id & 0x18) >> 3;
queue_id = (ring_id & 0x7) >> 0; switch (me_id) { case 0: /* This results in a full GPU reset, but all we need to do is soft
-- 2.7.4
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