Hi,
We are developing a custom board, in which we are using the rk3399 soc. We have LVDS displays, and use TI SN65dsi84 bridge as a mipi-lvds bridge. The bridge demands the DSI data lanes be in LP-11 state (stop state). We developed support for the bridge as a DRM bridge module. It gets called in the places we want, but the problem is the data lanes, no in LP-11. Instead, they seem to be lowish, until data starts (they seem to visit LP-11 a a short time, like 5ms before data stream. This is not enough and not under our control. We would like to demand the mipi dhpy into LP-11 (or make sure it stays there from powerup/reset). And after configuring bridge, let the data leave LP-11.
Documentation states that the data should be LP-11 upon phy reset. How come it is not? And, while booting, we se a couple of set mode calls, during which the phy is configured. During the phy init, there's code to wait for the phy enter stop state. First time the phy status says it has entered stop state. But second time the wait timeouts (after 10ms or so). With oscilloscope anything like LP-11 isn't observed.
Has someone successfully integrated SN65dsi8x with rk3399 ? Does someone have information on howto command the phy wrt stop states and how it should behave?
Thanks in advance, Mika Penttilä Nextfour
On 27.01.2020 17:18, Mika Penttilä wrote:
Hi,
We are developing a custom board, in which we are using the rk3399 soc. We have LVDS displays, and use TI SN65dsi84 bridge as a mipi-lvds bridge. The bridge demands the DSI data lanes be in LP-11 state (stop state). We developed support for the bridge as a DRM bridge module. It gets called in the places we want, but the problem is the data lanes, no in LP-11. Instead, they seem to be lowish, until data starts (they seem to visit LP-11 a a short time, like 5ms before data stream. This is not enough and not under our control. We would like to demand the mipi dhpy into LP-11 (or make sure it stays there from powerup/reset). And after configuring bridge, let the data leave LP-11.
Documentation states that the data should be LP-11 upon phy reset. How come it is not? And, while booting, we se a couple of set mode calls, during which the phy is configured. During the phy init, there's code to wait for the phy enter stop state. First time the phy status says it has entered stop state. But second time the wait timeouts (after 10ms or so). With oscilloscope anything like LP-11 isn't observed.
Has someone successfully integrated SN65dsi8x with rk3399 ? Does someone have information on howto command the phy wrt stop states and how it should behave?
I am not familiar neither with rk3399, neither sn65dsi84 so I cannot tell about these chips,
but generally power-on on mipi source (rk3399 or external mipi phy) should drive LP-11 state.
So I would look into rk3389-mipi driver, mipi-phy code (especially if there is external phy), maybe regulators powering display pipeline, maybe some gpios, voltage level shifters, power domains, SoCs external interfaces isolation configuration ???
Additionally you should study all wires on board's schematics regarding display pipeline.
Without the code or documentation is hard to say more what is going on here.
Regards
Andrzej
Thanks in advance, Mika Penttilä Nextfour
dri-devel mailing list dri-devel@lists.freedesktop.org https://protect2.fireeye.com/url?k=c52bdf84-98f8863a-c52a54cb-0cc47a31ba82-d...
Hi,
We are developing a custom board based on the rk3399 soc. We need two displays, and would like to use the two mipi DSI interfaces ff960000.mipi and ff968000.mipi, simultaneously, independently, both with an own touch controller, 4 lanes per display.
Question, is this a possible scenario, concerning rk3399 and mipi dphys. So two fully independent, no dual modes, master-slaves etc.
Thanks in advance, Mika Penttilä Nextfour
dri-devel@lists.freedesktop.org
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Andrzej Hajda -
Mika Penttilä