The dpi/dpintf driver and the added helper functions are required for the DisplayPort driver to work.
This series is separated from [1] which is original from Guillaume. The display port driver is [2].
Changes for v12: 1. Remove pll_gate. 2. Add more detailed commit message. 3. Separate tvd_clk patch and yuv422 output support from add dpintf support patch 4. Remove limit patch and use common driver codes to determine this.
Changes for v11: 1. Rename ck_cg to pll_gate. 2. Add some commit message to clarify the modification reason. 3. Fix some driver order and modify for reviewers' comments.
[1]:https://lore.kernel.org/all/20220523104758.29531-1-granquet@baylibre.com/ [2]:https://lore.kernel.org/all/20220610105522.13449-1-rex-bc.chen@mediatek.com/
Bo-Chen Chen (3): drm/mediatek: dpi: Add support for quantization range drm/mediatek: dpi: Add tvd_clk enable/disable flow drm/mediatek: dpi: Add YUV422 output support
Guillaume Ranquet (10): drm/mediatek: dpi: implement a CK/DE pol toggle in SoC config drm/mediatek: dpi: implement a swap_input toggle in SoC config drm/mediatek: dpi: move dimension mask to SoC config drm/mediatek: dpi: move hvsize_mask to SoC config drm/mediatek: dpi: move swap_shift to SoC config drm/mediatek: dpi: move the yuv422_en_bit to SoC config drm/mediatek: dpi: move the csc_enable bit to SoC config drm/mediatek: dpi: Add dpintf support drm/mediatek: dpi: Only enable dpi after the bridge is enabled drm/mediatek: dpi: Add matrix_sel helper
Markus Schneider-Pargmann (1): dt-bindings: mediatek,dpi: Add DP_INTF compatible
.../display/mediatek/mediatek,dpi.yaml | 11 +- drivers/gpu/drm/mediatek/mtk_dpi.c | 248 +++++++++++++++--- drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 16 ++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 4 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 + 6 files changed, 235 insertions(+), 48 deletions(-)
From: Markus Schneider-Pargmann msp@baylibre.com
DP_INTF is similar to DPI but does not have the exact same feature set or register layouts.
DP_INTF is the sink of the display pipeline that is connected to the DisplayPort controller and encoder unit. It takes the same clocks as DPI.
In this patch, we also do these string replacement: - s/mediatek/MediaTek/ in title. - s/Mediatek/MediaTek/ in description.
Signed-off-by: Markus Schneider-Pargmann msp@baylibre.com Signed-off-by: Guillaume Ranquet granquet@baylibre.com [Bo-Chen: Modify reviewers' comments.] Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com --- .../bindings/display/mediatek/mediatek,dpi.yaml | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml index 77ee1b923991..d72f74632038 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml @@ -4,16 +4,16 @@ $id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml#
-title: mediatek DPI Controller Device Tree Bindings +title: MediaTek DPI and DP_INTF Controller
maintainers: - CK Hu ck.hu@mediatek.com - Jitao shi jitao.shi@mediatek.com
description: | - The Mediatek DPI function block is a sink of the display subsystem and - provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel - output bus. + The MediaTek DPI and DP_INTF function blocks are a sink of the display + subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a + parallel output bus.
properties: compatible: @@ -24,6 +24,7 @@ properties: - mediatek,mt8183-dpi - mediatek,mt8186-dpi - mediatek,mt8192-dpi + - mediatek,mt8195-dp_intf
reg: maxItems: 1 @@ -55,7 +56,7 @@ properties: $ref: /schemas/graph.yaml#/properties/port description: Output port node. This port should be connected to the input port of an - attached HDMI or LVDS encoder chip. + attached HDMI, LVDS or DisplayPort encoder chip.
required: - compatible
On Mon, Jun 20, 2022 at 08:10:15PM +0800, Bo-Chen Chen wrote:
From: Markus Schneider-Pargmann msp@baylibre.com
DP_INTF is similar to DPI but does not have the exact same feature set or register layouts.
DP_INTF is the sink of the display pipeline that is connected to the DisplayPort controller and encoder unit. It takes the same clocks as DPI.
In this patch, we also do these string replacement:
- s/mediatek/MediaTek/ in title.
- s/Mediatek/MediaTek/ in description.
Signed-off-by: Markus Schneider-Pargmann msp@baylibre.com Signed-off-by: Guillaume Ranquet granquet@baylibre.com [Bo-Chen: Modify reviewers' comments.] Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com
.../bindings/display/mediatek/mediatek,dpi.yaml | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml index 77ee1b923991..d72f74632038 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml @@ -4,16 +4,16 @@ $id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml#
-title: mediatek DPI Controller Device Tree Bindings +title: MediaTek DPI and DP_INTF Controller
maintainers:
- CK Hu ck.hu@mediatek.com
- Jitao shi jitao.shi@mediatek.com
description: |
- The Mediatek DPI function block is a sink of the display subsystem and
- provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel
- output bus.
- The MediaTek DPI and DP_INTF function blocks are a sink of the display
- subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a
- parallel output bus.
properties: compatible: @@ -24,6 +24,7 @@ properties: - mediatek,mt8183-dpi - mediatek,mt8186-dpi - mediatek,mt8192-dpi
- mediatek,mt8195-dp_intf
Underscores are frowned upon in the compatibles. See Section 2.3.1 of the device tree spec:
The compatible string should consist only of lowercase letters, digits and dashes, and should start with a letter. A single comma is typically only used following a vendor prefix. Underscores should not be used.
Maxime
On Mon, 2022-06-20 at 14:25 +0200, Maxime Ripard wrote:
On Mon, Jun 20, 2022 at 08:10:15PM +0800, Bo-Chen Chen wrote:
From: Markus Schneider-Pargmann msp@baylibre.com
DP_INTF is similar to DPI but does not have the exact same feature set or register layouts.
DP_INTF is the sink of the display pipeline that is connected to the DisplayPort controller and encoder unit. It takes the same clocks as DPI.
In this patch, we also do these string replacement:
- s/mediatek/MediaTek/ in title.
- s/Mediatek/MediaTek/ in description.
Signed-off-by: Markus Schneider-Pargmann msp@baylibre.com Signed-off-by: Guillaume Ranquet granquet@baylibre.com [Bo-Chen: Modify reviewers' comments.] Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com
.../bindings/display/mediatek/mediatek,dpi.yaml | 11 ++++++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.y aml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.y aml index 77ee1b923991..d72f74632038 100644
a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.y aml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.y aml @@ -4,16 +4,16 @@ $id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml#
-title: mediatek DPI Controller Device Tree Bindings +title: MediaTek DPI and DP_INTF Controller
maintainers:
- CK Hu ck.hu@mediatek.com
- Jitao shi jitao.shi@mediatek.com
description: |
- The Mediatek DPI function block is a sink of the display
subsystem and
- provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a
parallel
- output bus.
- The MediaTek DPI and DP_INTF function blocks are a sink of the
display
- subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422
pixel data on a
- parallel output bus.
properties: compatible: @@ -24,6 +24,7 @@ properties: - mediatek,mt8183-dpi - mediatek,mt8186-dpi - mediatek,mt8192-dpi
- mediatek,mt8195-dp_intfUnderscores are frowned upon in the compatibles. See Section 2.3.1 of the device tree spec:
The compatible string should consist only of lowercase letters, digits and dashes, and should start with a letter. A single comma is typically only used following a vendor prefix. Underscores should not be used.
Maxime
Hello Maxime,
Thanks for review. I will modify this compatible as "mediatek,mt8195-dp-intf"
BRs, Bo-Chen
For RGB colorimetry, CTA-861 support both limited and full range data when receiving video with RGB color space. We use drm_default_rgb_quant_range() to determine the correct setting.
Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com --- drivers/gpu/drm/mediatek/mtk_dpi.c | 34 ++++++++++++++++++------------ 1 file changed, 21 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index e61cd67b978f..21ad5623b568 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -235,16 +235,30 @@ static void mtk_dpi_config_fb_size(struct mtk_dpi *dpi, u32 width, u32 height) mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, VSIZE_MASK); }
-static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi, - struct mtk_dpi_yc_limit *limit) +static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi) { - mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_bottom << Y_LIMINT_BOT, + struct mtk_dpi_yc_limit limit; + + if (drm_default_rgb_quant_range(&dpi->mode) == + HDMI_QUANTIZATION_RANGE_LIMITED) { + limit.y_bottom = 0x10; + limit.y_top = 0xfe0; + limit.c_bottom = 0x10; + limit.c_top = 0xfe0; + } else { + limit.y_bottom = 0; + limit.y_top = 0xfff; + limit.c_bottom = 0; + limit.c_top = 0xfff; + } + + mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit.y_bottom << Y_LIMINT_BOT, Y_LIMINT_BOT_MASK); - mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_top << Y_LIMINT_TOP, + mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit.y_top << Y_LIMINT_TOP, Y_LIMINT_TOP_MASK); - mtk_dpi_mask(dpi, DPI_C_LIMIT, limit->c_bottom << C_LIMIT_BOT, + mtk_dpi_mask(dpi, DPI_C_LIMIT, limit.c_bottom << C_LIMIT_BOT, C_LIMIT_BOT_MASK); - mtk_dpi_mask(dpi, DPI_C_LIMIT, limit->c_top << C_LIMIT_TOP, + mtk_dpi_mask(dpi, DPI_C_LIMIT, limit.c_top << C_LIMIT_TOP, C_LIMIT_TOP_MASK); }
@@ -449,7 +463,6 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, struct drm_display_mode *mode) { - struct mtk_dpi_yc_limit limit; struct mtk_dpi_polarities dpi_pol; struct mtk_dpi_sync_param hsync; struct mtk_dpi_sync_param vsync_lodd = { 0 }; @@ -484,11 +497,6 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n", pll_rate, vm.pixelclock);
- limit.c_bottom = 0x0010; - limit.c_top = 0x0FE0; - limit.y_bottom = 0x0010; - limit.y_top = 0x0FE0; - dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING; dpi_pol.de_pol = MTK_DPI_POLARITY_RISING; dpi_pol.hsync_pol = vm.flags & DISPLAY_FLAGS_HSYNC_HIGH ? @@ -536,7 +544,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, else mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive);
- mtk_dpi_config_channel_limit(dpi, &limit); + mtk_dpi_config_channel_limit(dpi); mtk_dpi_config_bit_num(dpi, dpi->bit_num); mtk_dpi_config_channel_swap(dpi, dpi->channel_swap); mtk_dpi_config_yc_map(dpi, dpi->yc_map);
Hi, Bo-Chen:
On Mon, 2022-06-20 at 20:10 +0800, Bo-Chen Chen wrote:
For RGB colorimetry, CTA-861 support both limited and full range data when receiving video with RGB color space. We use drm_default_rgb_quant_range() to determine the correct setting.
Reviewed-by: CK Hu ck.hu@mediatek.com
Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com
drivers/gpu/drm/mediatek/mtk_dpi.c | 34 ++++++++++++++++++--------
1 file changed, 21 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index e61cd67b978f..21ad5623b568 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -235,16 +235,30 @@ static void mtk_dpi_config_fb_size(struct mtk_dpi *dpi, u32 width, u32 height) mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, VSIZE_MASK); }
-static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi,
struct mtk_dpi_yc_limit*limit) +static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi) {
- mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_bottom << Y_LIMINT_BOT,
- struct mtk_dpi_yc_limit limit;
- if (drm_default_rgb_quant_range(&dpi->mode) ==
HDMI_QUANTIZATION_RANGE_LIMITED) {limit.y_bottom = 0x10;limit.y_top = 0xfe0;limit.c_bottom = 0x10;limit.c_top = 0xfe0;- } else {
limit.y_bottom = 0;limit.y_top = 0xfff;limit.c_bottom = 0;limit.c_top = 0xfff;- }
- mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit.y_bottom << Y_LIMINT_BOT, Y_LIMINT_BOT_MASK);
- mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_top << Y_LIMINT_TOP,
- mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit.y_top << Y_LIMINT_TOP, Y_LIMINT_TOP_MASK);
- mtk_dpi_mask(dpi, DPI_C_LIMIT, limit->c_bottom << C_LIMIT_BOT,
- mtk_dpi_mask(dpi, DPI_C_LIMIT, limit.c_bottom << C_LIMIT_BOT, C_LIMIT_BOT_MASK);
- mtk_dpi_mask(dpi, DPI_C_LIMIT, limit->c_top << C_LIMIT_TOP,
- mtk_dpi_mask(dpi, DPI_C_LIMIT, limit.c_top << C_LIMIT_TOP, C_LIMIT_TOP_MASK);
}
@@ -449,7 +463,6 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, struct drm_display_mode *mode) {
- struct mtk_dpi_yc_limit limit; struct mtk_dpi_polarities dpi_pol; struct mtk_dpi_sync_param hsync; struct mtk_dpi_sync_param vsync_lodd = { 0 };
@@ -484,11 +497,6 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n", pll_rate, vm.pixelclock);
- limit.c_bottom = 0x0010;
- limit.c_top = 0x0FE0;
- limit.y_bottom = 0x0010;
- limit.y_top = 0x0FE0;
- dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING; dpi_pol.de_pol = MTK_DPI_POLARITY_RISING; dpi_pol.hsync_pol = vm.flags & DISPLAY_FLAGS_HSYNC_HIGH ?
@@ -536,7 +544,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, else mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive);
- mtk_dpi_config_channel_limit(dpi, &limit);
- mtk_dpi_config_channel_limit(dpi); mtk_dpi_config_bit_num(dpi, dpi->bit_num); mtk_dpi_config_channel_swap(dpi, dpi->channel_swap); mtk_dpi_config_yc_map(dpi, dpi->yc_map);
From: Guillaume Ranquet granquet@baylibre.com
Dp_intf does not support CK/DE polarity because the polarity information is not used for eDP and DP while dp_intf is only for eDP and DP. Therefore, we add a bit of flexibility to support SoCs without CK/DE pol support.
Signed-off-by: Guillaume Ranquet granquet@baylibre.com [Bo-Chen: Add modification reason in commit message.] Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com Reviewed-by: AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com Reviewed-by: Rex-BC Chen rex-bc.chen@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_dpi.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 21ad5623b568..c88d64889402 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -125,6 +125,7 @@ struct mtk_dpi_conf { bool edge_sel_en; const u32 *output_fmts; u32 num_output_fmts; + bool is_ck_de_pol; };
static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) @@ -210,13 +211,20 @@ static void mtk_dpi_config_pol(struct mtk_dpi *dpi, struct mtk_dpi_polarities *dpi_pol) { unsigned int pol; + unsigned int mask;
- pol = (dpi_pol->ck_pol == MTK_DPI_POLARITY_RISING ? 0 : CK_POL) | - (dpi_pol->de_pol == MTK_DPI_POLARITY_RISING ? 0 : DE_POL) | - (dpi_pol->hsync_pol == MTK_DPI_POLARITY_RISING ? 0 : HSYNC_POL) | + mask = HSYNC_POL | VSYNC_POL; + pol = (dpi_pol->hsync_pol == MTK_DPI_POLARITY_RISING ? 0 : HSYNC_POL) | (dpi_pol->vsync_pol == MTK_DPI_POLARITY_RISING ? 0 : VSYNC_POL); - mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, pol, - CK_POL | DE_POL | HSYNC_POL | VSYNC_POL); + if (dpi->conf->is_ck_de_pol) { + mask |= CK_POL | DE_POL; + pol |= (dpi_pol->ck_pol == MTK_DPI_POLARITY_RISING ? + 0 : CK_POL) | + (dpi_pol->de_pol == MTK_DPI_POLARITY_RISING ? + 0 : DE_POL); + } + + mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, pol, mask); }
static void mtk_dpi_config_3d(struct mtk_dpi *dpi, bool en_3d) @@ -804,6 +812,7 @@ static const struct mtk_dpi_conf mt8173_conf = { .max_clock_khz = 300000, .output_fmts = mt8173_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), + .is_ck_de_pol = true, };
static const struct mtk_dpi_conf mt2701_conf = { @@ -813,6 +822,7 @@ static const struct mtk_dpi_conf mt2701_conf = { .max_clock_khz = 150000, .output_fmts = mt8173_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), + .is_ck_de_pol = true, };
static const struct mtk_dpi_conf mt8183_conf = { @@ -821,6 +831,7 @@ static const struct mtk_dpi_conf mt8183_conf = { .max_clock_khz = 100000, .output_fmts = mt8183_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), + .is_ck_de_pol = true, };
static const struct mtk_dpi_conf mt8192_conf = { @@ -829,6 +840,7 @@ static const struct mtk_dpi_conf mt8192_conf = { .max_clock_khz = 150000, .output_fmts = mt8183_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), + .is_ck_de_pol = true, };
static int mtk_dpi_probe(struct platform_device *pdev)
From: Guillaume Ranquet granquet@baylibre.com
The hardware design of dp_intf does not support input swap, so we add a bit of flexibility to support SoCs without swap_input support. We also add a warning message if the hardware is not supported and it needs to swap input.
Signed-off-by: Guillaume Ranquet granquet@baylibre.com [Bo-Chen: Add modification reason in commit message.] Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com Reviewed-by: AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com Reviewed-by: Rex-BC Chen rex-bc.chen@mediatek.com --- drivers/gpu/drm/mediatek/mtk_dpi.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index c88d64889402..5aab3029c54d 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -126,6 +126,7 @@ struct mtk_dpi_conf { const u32 *output_fmts; u32 num_output_fmts; bool is_ck_de_pol; + bool swap_input_support; };
static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) @@ -390,18 +391,24 @@ static void mtk_dpi_config_color_format(struct mtk_dpi *dpi, (format == MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL)) { mtk_dpi_config_yuv422_enable(dpi, false); mtk_dpi_config_csc_enable(dpi, true); - mtk_dpi_config_swap_input(dpi, false); + if (dpi->conf->swap_input_support) + mtk_dpi_config_swap_input(dpi, false); mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_BGR); } else if ((format == MTK_DPI_COLOR_FORMAT_YCBCR_422) || (format == MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL)) { mtk_dpi_config_yuv422_enable(dpi, true); mtk_dpi_config_csc_enable(dpi, true); - mtk_dpi_config_swap_input(dpi, true); + if (dpi->conf->swap_input_support) + mtk_dpi_config_swap_input(dpi, true); + else + dev_warn(dpi->dev, + "Failed to swap input, hw is not supported.\n"); mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB); } else { mtk_dpi_config_yuv422_enable(dpi, false); mtk_dpi_config_csc_enable(dpi, false); - mtk_dpi_config_swap_input(dpi, false); + if (dpi->conf->swap_input_support) + mtk_dpi_config_swap_input(dpi, false); mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB); } } @@ -813,6 +820,7 @@ static const struct mtk_dpi_conf mt8173_conf = { .output_fmts = mt8173_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol = true, + .swap_input_support = true, };
static const struct mtk_dpi_conf mt2701_conf = { @@ -823,6 +831,7 @@ static const struct mtk_dpi_conf mt2701_conf = { .output_fmts = mt8173_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol = true, + .swap_input_support = true, };
static const struct mtk_dpi_conf mt8183_conf = { @@ -832,6 +841,7 @@ static const struct mtk_dpi_conf mt8183_conf = { .output_fmts = mt8183_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), .is_ck_de_pol = true, + .swap_input_support = true, };
static const struct mtk_dpi_conf mt8192_conf = { @@ -841,6 +851,7 @@ static const struct mtk_dpi_conf mt8192_conf = { .output_fmts = mt8183_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), .is_ck_de_pol = true, + .swap_input_support = true, };
static int mtk_dpi_probe(struct platform_device *pdev)
Hi, Bo-Chen:
On Mon, 2022-06-20 at 20:10 +0800, Bo-Chen Chen wrote:
From: Guillaume Ranquet granquet@baylibre.com
The hardware design of dp_intf does not support input swap, so we add a bit of flexibility to support SoCs without swap_input support. We also add a warning message if the hardware is not supported and it needs to swap input.
Reviewed-by: CK Hu ck.hu@mediatek.com
Signed-off-by: Guillaume Ranquet granquet@baylibre.com [Bo-Chen: Add modification reason in commit message.] Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com Reviewed-by: AngeloGioacchino Del Regno < angelogioacchino.delregno@collabora.com> Reviewed-by: Rex-BC Chen rex-bc.chen@mediatek.com
drivers/gpu/drm/mediatek/mtk_dpi.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index c88d64889402..5aab3029c54d 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -126,6 +126,7 @@ struct mtk_dpi_conf { const u32 *output_fmts; u32 num_output_fmts; bool is_ck_de_pol;
- bool swap_input_support;
};
static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) @@ -390,18 +391,24 @@ static void mtk_dpi_config_color_format(struct mtk_dpi *dpi, (format == MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL)) { mtk_dpi_config_yuv422_enable(dpi, false); mtk_dpi_config_csc_enable(dpi, true);
mtk_dpi_config_swap_input(dpi, false);
if (dpi->conf->swap_input_support)mtk_dpi_config_swap_input(dpi, false);MTK_DPI_OUT_CHANNEL_SWAP_BGR); } else if ((format == MTK_DPI_COLOR_FORMAT_YCBCR_422) || (format == MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL)) { mtk_dpi_config_yuv422_enable(dpi, true); mtk_dpi_config_csc_enable(dpi, true);
mtk_dpi_config_swap_input(dpi, true);
if (dpi->conf->swap_input_support)mtk_dpi_config_swap_input(dpi, true);elsedev_warn(dpi->dev,"Failed to swap input, hw is notsupported.\n"); mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB); } else { mtk_dpi_config_yuv422_enable(dpi, false); mtk_dpi_config_csc_enable(dpi, false);
mtk_dpi_config_swap_input(dpi, false);
if (dpi->conf->swap_input_support)mtk_dpi_config_swap_input(dpi, false);MTK_DPI_OUT_CHANNEL_SWAP_RGB); } } @@ -813,6 +820,7 @@ static const struct mtk_dpi_conf mt8173_conf = { .output_fmts = mt8173_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol = true,
- .swap_input_support = true,
};
static const struct mtk_dpi_conf mt2701_conf = { @@ -823,6 +831,7 @@ static const struct mtk_dpi_conf mt2701_conf = { .output_fmts = mt8173_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol = true,
- .swap_input_support = true,
};
static const struct mtk_dpi_conf mt8183_conf = { @@ -832,6 +841,7 @@ static const struct mtk_dpi_conf mt8183_conf = { .output_fmts = mt8183_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), .is_ck_de_pol = true,
- .swap_input_support = true,
};
static const struct mtk_dpi_conf mt8192_conf = { @@ -841,6 +851,7 @@ static const struct mtk_dpi_conf mt8192_conf = { .output_fmts = mt8183_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), .is_ck_de_pol = true,
- .swap_input_support = true,
};
static int mtk_dpi_probe(struct platform_device *pdev)
From: Guillaume Ranquet granquet@baylibre.com
Add flexibility by moving the dimension mask to the SoC config
Signed-off-by: Guillaume Ranquet granquet@baylibre.com Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com Reviewed-by: AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com Reviewed-by: Rex-BC Chen rex-bc.chen@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_dpi.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 5aab3029c54d..da3859dffd1d 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -127,6 +127,8 @@ struct mtk_dpi_conf { u32 num_output_fmts; bool is_ck_de_pol; bool swap_input_support; + /* Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH (no shift) */ + u32 dimension_mask; };
static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) @@ -155,30 +157,30 @@ static void mtk_dpi_disable(struct mtk_dpi *dpi) static void mtk_dpi_config_hsync(struct mtk_dpi *dpi, struct mtk_dpi_sync_param *sync) { - mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH, - sync->sync_width << HPW, HPW_MASK); - mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, - sync->back_porch << HBP, HBP_MASK); + mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH, sync->sync_width << HPW, + dpi->conf->dimension_mask << HPW); + mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->back_porch << HBP, + dpi->conf->dimension_mask << HBP); mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->front_porch << HFP, - HFP_MASK); + dpi->conf->dimension_mask << HFP); }
static void mtk_dpi_config_vsync(struct mtk_dpi *dpi, struct mtk_dpi_sync_param *sync, u32 width_addr, u32 porch_addr) { - mtk_dpi_mask(dpi, width_addr, - sync->sync_width << VSYNC_WIDTH_SHIFT, - VSYNC_WIDTH_MASK); mtk_dpi_mask(dpi, width_addr, sync->shift_half_line << VSYNC_HALF_LINE_SHIFT, VSYNC_HALF_LINE_MASK); + mtk_dpi_mask(dpi, width_addr, + sync->sync_width << VSYNC_WIDTH_SHIFT, + dpi->conf->dimension_mask << VSYNC_WIDTH_SHIFT); mtk_dpi_mask(dpi, porch_addr, sync->back_porch << VSYNC_BACK_PORCH_SHIFT, - VSYNC_BACK_PORCH_MASK); + dpi->conf->dimension_mask << VSYNC_BACK_PORCH_SHIFT); mtk_dpi_mask(dpi, porch_addr, sync->front_porch << VSYNC_FRONT_PORCH_SHIFT, - VSYNC_FRONT_PORCH_MASK); + dpi->conf->dimension_mask << VSYNC_FRONT_PORCH_SHIFT); }
static void mtk_dpi_config_vsync_lodd(struct mtk_dpi *dpi, @@ -821,6 +823,7 @@ static const struct mtk_dpi_conf mt8173_conf = { .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol = true, .swap_input_support = true, + .dimension_mask = HPW_MASK, };
static const struct mtk_dpi_conf mt2701_conf = { @@ -832,6 +835,7 @@ static const struct mtk_dpi_conf mt2701_conf = { .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol = true, .swap_input_support = true, + .dimension_mask = HPW_MASK, };
static const struct mtk_dpi_conf mt8183_conf = { @@ -842,6 +846,7 @@ static const struct mtk_dpi_conf mt8183_conf = { .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), .is_ck_de_pol = true, .swap_input_support = true, + .dimension_mask = HPW_MASK, };
static const struct mtk_dpi_conf mt8192_conf = { @@ -852,6 +857,7 @@ static const struct mtk_dpi_conf mt8192_conf = { .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), .is_ck_de_pol = true, .swap_input_support = true, + .dimension_mask = HPW_MASK, };
static int mtk_dpi_probe(struct platform_device *pdev)
From: Guillaume Ranquet granquet@baylibre.com
Add flexibility by moving the hvsize mask to SoC specific config.
Signed-off-by: Guillaume Ranquet granquet@baylibre.com Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com Reviewed-by: AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com Reviewed-by: Rex-BC Chen rex-bc.chen@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_dpi.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index da3859dffd1d..f9c7c258d2af 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -129,6 +129,8 @@ struct mtk_dpi_conf { bool swap_input_support; /* Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH (no shift) */ u32 dimension_mask; + /* HSIZE and VSIZE mask (no shift) */ + u32 hvsize_mask; };
static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) @@ -242,8 +244,10 @@ static void mtk_dpi_config_interface(struct mtk_dpi *dpi, bool inter)
static void mtk_dpi_config_fb_size(struct mtk_dpi *dpi, u32 width, u32 height) { - mtk_dpi_mask(dpi, DPI_SIZE, width << HSIZE, HSIZE_MASK); - mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, VSIZE_MASK); + mtk_dpi_mask(dpi, DPI_SIZE, width << HSIZE, + dpi->conf->hvsize_mask << HSIZE); + mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, + dpi->conf->hvsize_mask << VSIZE); }
static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi) @@ -824,6 +828,7 @@ static const struct mtk_dpi_conf mt8173_conf = { .is_ck_de_pol = true, .swap_input_support = true, .dimension_mask = HPW_MASK, + .hvsize_mask = HSIZE_MASK, };
static const struct mtk_dpi_conf mt2701_conf = { @@ -836,6 +841,7 @@ static const struct mtk_dpi_conf mt2701_conf = { .is_ck_de_pol = true, .swap_input_support = true, .dimension_mask = HPW_MASK, + .hvsize_mask = HSIZE_MASK, };
static const struct mtk_dpi_conf mt8183_conf = { @@ -847,6 +853,7 @@ static const struct mtk_dpi_conf mt8183_conf = { .is_ck_de_pol = true, .swap_input_support = true, .dimension_mask = HPW_MASK, + .hvsize_mask = HSIZE_MASK, };
static const struct mtk_dpi_conf mt8192_conf = { @@ -858,6 +865,7 @@ static const struct mtk_dpi_conf mt8192_conf = { .is_ck_de_pol = true, .swap_input_support = true, .dimension_mask = HPW_MASK, + .hvsize_mask = HSIZE_MASK, };
static int mtk_dpi_probe(struct platform_device *pdev)
From: Guillaume Ranquet granquet@baylibre.com
Add flexibility by moving the swap shift value to SoC specific config.
Signed-off-by: Guillaume Ranquet granquet@baylibre.com Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com Reviewed-by: Rex-BC Chen rex-bc.chen@mediatek.com Reviewed-by: AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_dpi.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index f9c7c258d2af..fcd3941f8003 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -131,6 +131,7 @@ struct mtk_dpi_conf { u32 dimension_mask; /* HSIZE and VSIZE mask (no shift) */ u32 hvsize_mask; + u32 channel_swap_shift; };
static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) @@ -361,7 +362,9 @@ static void mtk_dpi_config_channel_swap(struct mtk_dpi *dpi, break; }
- mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << CH_SWAP, CH_SWAP_MASK); + mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, + val << dpi->conf->channel_swap_shift, + CH_SWAP_MASK << dpi->conf->channel_swap_shift); }
static void mtk_dpi_config_yuv422_enable(struct mtk_dpi *dpi, bool enable) @@ -829,6 +832,7 @@ static const struct mtk_dpi_conf mt8173_conf = { .swap_input_support = true, .dimension_mask = HPW_MASK, .hvsize_mask = HSIZE_MASK, + .channel_swap_shift = CH_SWAP, };
static const struct mtk_dpi_conf mt2701_conf = { @@ -842,6 +846,7 @@ static const struct mtk_dpi_conf mt2701_conf = { .swap_input_support = true, .dimension_mask = HPW_MASK, .hvsize_mask = HSIZE_MASK, + .channel_swap_shift = CH_SWAP, };
static const struct mtk_dpi_conf mt8183_conf = { @@ -854,6 +859,7 @@ static const struct mtk_dpi_conf mt8183_conf = { .swap_input_support = true, .dimension_mask = HPW_MASK, .hvsize_mask = HSIZE_MASK, + .channel_swap_shift = CH_SWAP, };
static const struct mtk_dpi_conf mt8192_conf = { @@ -866,6 +872,7 @@ static const struct mtk_dpi_conf mt8192_conf = { .swap_input_support = true, .dimension_mask = HPW_MASK, .hvsize_mask = HSIZE_MASK, + .channel_swap_shift = CH_SWAP, };
static int mtk_dpi_probe(struct platform_device *pdev)
From: Guillaume Ranquet granquet@baylibre.com
Add flexibility by moving the yuv422 en bit to SoC specific config
Signed-off-by: Guillaume Ranquet granquet@baylibre.com Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com Reviewed-by: AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com Reviewed-by: Rex-BC Chen rex-bc.chen@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_dpi.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index fcd3941f8003..c0ee6b18a057 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -132,6 +132,7 @@ struct mtk_dpi_conf { /* HSIZE and VSIZE mask (no shift) */ u32 hvsize_mask; u32 channel_swap_shift; + u32 yuv422_en_bit; };
static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) @@ -369,7 +370,8 @@ static void mtk_dpi_config_channel_swap(struct mtk_dpi *dpi,
static void mtk_dpi_config_yuv422_enable(struct mtk_dpi *dpi, bool enable) { - mtk_dpi_mask(dpi, DPI_CON, enable ? YUV422_EN : 0, YUV422_EN); + mtk_dpi_mask(dpi, DPI_CON, enable ? dpi->conf->yuv422_en_bit : 0, + dpi->conf->yuv422_en_bit); }
static void mtk_dpi_config_csc_enable(struct mtk_dpi *dpi, bool enable) @@ -833,6 +835,7 @@ static const struct mtk_dpi_conf mt8173_conf = { .dimension_mask = HPW_MASK, .hvsize_mask = HSIZE_MASK, .channel_swap_shift = CH_SWAP, + .yuv422_en_bit = YUV422_EN, };
static const struct mtk_dpi_conf mt2701_conf = { @@ -847,6 +850,7 @@ static const struct mtk_dpi_conf mt2701_conf = { .dimension_mask = HPW_MASK, .hvsize_mask = HSIZE_MASK, .channel_swap_shift = CH_SWAP, + .yuv422_en_bit = YUV422_EN, };
static const struct mtk_dpi_conf mt8183_conf = { @@ -860,6 +864,7 @@ static const struct mtk_dpi_conf mt8183_conf = { .dimension_mask = HPW_MASK, .hvsize_mask = HSIZE_MASK, .channel_swap_shift = CH_SWAP, + .yuv422_en_bit = YUV422_EN, };
static const struct mtk_dpi_conf mt8192_conf = { @@ -873,6 +878,7 @@ static const struct mtk_dpi_conf mt8192_conf = { .dimension_mask = HPW_MASK, .hvsize_mask = HSIZE_MASK, .channel_swap_shift = CH_SWAP, + .yuv422_en_bit = YUV422_EN, };
static int mtk_dpi_probe(struct platform_device *pdev)
From: Guillaume Ranquet granquet@baylibre.com
Add flexibility by moving the csc_enable bit to SoC specific config
Signed-off-by: Guillaume Ranquet granquet@baylibre.com Reviewed-by: AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com Reviewed-by: Rex-BC Chen rex-bc.chen@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_dpi.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index c0ee6b18a057..e186870ba3bc 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -133,6 +133,7 @@ struct mtk_dpi_conf { u32 hvsize_mask; u32 channel_swap_shift; u32 yuv422_en_bit; + u32 csc_enable_bit; };
static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) @@ -376,7 +377,8 @@ static void mtk_dpi_config_yuv422_enable(struct mtk_dpi *dpi, bool enable)
static void mtk_dpi_config_csc_enable(struct mtk_dpi *dpi, bool enable) { - mtk_dpi_mask(dpi, DPI_CON, enable ? CSC_ENABLE : 0, CSC_ENABLE); + mtk_dpi_mask(dpi, DPI_CON, enable ? dpi->conf->csc_enable_bit : 0, + dpi->conf->csc_enable_bit); }
static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable) @@ -836,6 +838,7 @@ static const struct mtk_dpi_conf mt8173_conf = { .hvsize_mask = HSIZE_MASK, .channel_swap_shift = CH_SWAP, .yuv422_en_bit = YUV422_EN, + .csc_enable_bit = CSC_ENABLE, };
static const struct mtk_dpi_conf mt2701_conf = { @@ -851,6 +854,7 @@ static const struct mtk_dpi_conf mt2701_conf = { .hvsize_mask = HSIZE_MASK, .channel_swap_shift = CH_SWAP, .yuv422_en_bit = YUV422_EN, + .csc_enable_bit = CSC_ENABLE, };
static const struct mtk_dpi_conf mt8183_conf = { @@ -865,6 +869,7 @@ static const struct mtk_dpi_conf mt8183_conf = { .hvsize_mask = HSIZE_MASK, .channel_swap_shift = CH_SWAP, .yuv422_en_bit = YUV422_EN, + .csc_enable_bit = CSC_ENABLE, };
static const struct mtk_dpi_conf mt8192_conf = { @@ -879,6 +884,7 @@ static const struct mtk_dpi_conf mt8192_conf = { .hvsize_mask = HSIZE_MASK, .channel_swap_shift = CH_SWAP, .yuv422_en_bit = YUV422_EN, + .csc_enable_bit = CSC_ENABLE, };
static int mtk_dpi_probe(struct platform_device *pdev)
From: Guillaume Ranquet granquet@baylibre.com
dpintf is the displayport interface hardware unit. This unit is similar to dpi and can reuse most of the code.
This patch adds support for mt8195-dpintf to this dpi driver. Main differences are: - 4 pixels for one round for dp_intf while dpi is 1 pixel for one round. Therefore, pixel clock and timing parameter should be divided by 4 for dp_intf. - Some features/functional components are not available for dpintf which are now excluded from code execution once is_dpintf is set. The main difference is some parts of hardware design between dp_intf and dpi. - Some register contents differ slightly between the two components. To work around this I added register bits/masks with a DPINTF_ prefix and use them where different.
Based on a separate driver for dpintf created by Jitao shi jitao.shi@mediatek.com.
Signed-off-by: Markus Schneider-Pargmann msp@baylibre.com Signed-off-by: Guillaume Ranquet granquet@baylibre.com [Bo-Chen: Modify reviewers' comments.] Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com --- drivers/gpu/drm/mediatek/mtk_dpi.c | 65 +++++++++++++++++++-- drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 13 +++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 4 ++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 + 5 files changed, 82 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index e186870ba3bc..2717b1741b7a 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -126,6 +126,7 @@ struct mtk_dpi_conf { const u32 *output_fmts; u32 num_output_fmts; bool is_ck_de_pol; + bool is_dpintf; bool swap_input_support; /* Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH (no shift) */ u32 dimension_mask; @@ -513,6 +514,14 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, pll_rate = clk_get_rate(dpi->tvd_clk);
vm.pixelclock = pll_rate / factor; + + /* + * For dp_intf, we need to divide clock by 4 because it's + * 4 pixels for one round while dpi is 1 pixel for one round. + */ + if (dpi->conf->is_dpintf) + vm.pixelclock /= 4; + if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) || (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE)) clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2); @@ -534,6 +543,17 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, hsync.sync_width = vm.hsync_len; hsync.back_porch = vm.hback_porch; hsync.front_porch = vm.hfront_porch; + + /* + * For dp_intf, we need to divide everything by 4 because it's + * 4 pixels for one round while dpi is 1 pixel for one round. + */ + if (dpi->conf->is_dpintf) { + hsync.sync_width = vm.hsync_len / 4; + hsync.back_porch = vm.hback_porch / 4; + hsync.front_porch = vm.hfront_porch / 4; + } + hsync.shift_half_line = false; vsync_lodd.sync_width = vm.vsync_len; vsync_lodd.back_porch = vm.vback_porch; @@ -575,11 +595,16 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, mtk_dpi_config_channel_limit(dpi); mtk_dpi_config_bit_num(dpi, dpi->bit_num); mtk_dpi_config_channel_swap(dpi, dpi->channel_swap); - mtk_dpi_config_yc_map(dpi, dpi->yc_map); mtk_dpi_config_color_format(dpi, dpi->color_format); - mtk_dpi_config_2n_h_fre(dpi); - mtk_dpi_dual_edge(dpi); - mtk_dpi_config_disable_edge(dpi); + if (dpi->conf->is_dpintf) { + mtk_dpi_mask(dpi, DPI_CON, DPINTF_INPUT_2P_EN, + DPINTF_INPUT_2P_EN); + } else { + mtk_dpi_config_yc_map(dpi, dpi->yc_map); + mtk_dpi_config_2n_h_fre(dpi); + mtk_dpi_dual_edge(dpi); + mtk_dpi_config_disable_edge(dpi); + } mtk_dpi_sw_reset(dpi, false);
return 0; @@ -817,6 +842,16 @@ static unsigned int mt8183_calculate_factor(int clock) return 2; }
+static unsigned int mt8195_dpintf_calculate_factor(int clock) +{ + if (clock < 70000) + return 4; + else if (clock < 200000) + return 2; + else + return 1; +} + static const u32 mt8173_output_fmts[] = { MEDIA_BUS_FMT_RGB888_1X24, }; @@ -826,6 +861,12 @@ static const u32 mt8183_output_fmts[] = { MEDIA_BUS_FMT_RGB888_2X12_BE, };
+static const u32 mt8195_output_fmts[] = { + MEDIA_BUS_FMT_RGB888_1X24, + MEDIA_BUS_FMT_YUV8_1X24, + MEDIA_BUS_FMT_YUYV8_1X16, +}; + static const struct mtk_dpi_conf mt8173_conf = { .cal_factor = mt8173_calculate_factor, .reg_h_fre_con = 0xe0, @@ -887,6 +928,19 @@ static const struct mtk_dpi_conf mt8192_conf = { .csc_enable_bit = CSC_ENABLE, };
+static const struct mtk_dpi_conf mt8195_dpintf_conf = { + .cal_factor = mt8195_dpintf_calculate_factor, + .max_clock_khz = 600000, + .output_fmts = mt8195_output_fmts, + .num_output_fmts = ARRAY_SIZE(mt8195_output_fmts), + .is_dpintf = true, + .dimension_mask = DPINTF_HPW_MASK, + .hvsize_mask = DPINTF_HSIZE_MASK, + .channel_swap_shift = DPINTF_CH_SWAP, + .yuv422_en_bit = DPINTF_YUV422_EN, + .csc_enable_bit = DPINTF_CSC_ENABLE, +}; + static int mtk_dpi_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -1009,6 +1063,9 @@ static const struct of_device_id mtk_dpi_of_ids[] = { { .compatible = "mediatek,mt8192-dpi", .data = &mt8192_conf, }, + { .compatible = "mediatek,mt8195-dp_intf", + .data = &mt8195_dpintf_conf, + }, { }, }; MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids); diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h index 3a02fabe1662..f7f0272dbd6a 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h @@ -40,9 +40,13 @@ #define FAKE_DE_LEVEN BIT(21) #define FAKE_DE_RODD BIT(22) #define FAKE_DE_REVEN BIT(23) +#define DPINTF_YUV422_EN BIT(24) +#define DPINTF_CSC_ENABLE BIT(26) +#define DPINTF_INPUT_2P_EN BIT(29)
#define DPI_OUTPUT_SETTING 0x14 #define CH_SWAP 0 +#define DPINTF_CH_SWAP 1 #define CH_SWAP_MASK (0x7 << 0) #define SWAP_RGB 0x00 #define SWAP_GBR 0x01 @@ -80,8 +84,10 @@ #define DPI_SIZE 0x18 #define HSIZE 0 #define HSIZE_MASK (0x1FFF << 0) +#define DPINTF_HSIZE_MASK (0xFFFF << 0) #define VSIZE 16 #define VSIZE_MASK (0x1FFF << 16) +#define DPINTF_VSIZE_MASK (0xFFFF << 16)
#define DPI_DDR_SETTING 0x1C #define DDR_EN BIT(0) @@ -93,24 +99,30 @@ #define DPI_TGEN_HWIDTH 0x20 #define HPW 0 #define HPW_MASK (0xFFF << 0) +#define DPINTF_HPW_MASK (0xFFFF << 0)
#define DPI_TGEN_HPORCH 0x24 #define HBP 0 #define HBP_MASK (0xFFF << 0) +#define DPINTF_HBP_MASK (0xFFFF << 0) #define HFP 16 #define HFP_MASK (0xFFF << 16) +#define DPINTF_HFP_MASK (0xFFFF << 16)
#define DPI_TGEN_VWIDTH 0x28 #define DPI_TGEN_VPORCH 0x2C
#define VSYNC_WIDTH_SHIFT 0 #define VSYNC_WIDTH_MASK (0xFFF << 0) +#define DPINTF_VSYNC_WIDTH_MASK (0xFFFF << 0) #define VSYNC_HALF_LINE_SHIFT 16 #define VSYNC_HALF_LINE_MASK BIT(16) #define VSYNC_BACK_PORCH_SHIFT 0 #define VSYNC_BACK_PORCH_MASK (0xFFF << 0) +#define DPINTF_VSYNC_BACK_PORCH_MASK (0xFFFF << 0) #define VSYNC_FRONT_PORCH_SHIFT 16 #define VSYNC_FRONT_PORCH_MASK (0xFFF << 16) +#define DPINTF_VSYNC_FRONT_PORCH_MASK (0xFFFF << 16)
#define DPI_BG_HCNTL 0x30 #define BG_RIGHT (0x1FFF << 0) @@ -217,4 +229,5 @@
#define EDGE_SEL_EN BIT(5) #define H_FRE_2N BIT(25) + #endif /* __MTK_DPI_REGS_H */ diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 2aab1e1eda36..5bef085714a1 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -427,6 +427,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { [MTK_DISP_RDMA] = "rdma", [MTK_DISP_UFOE] = "ufoe", [MTK_DISP_WDMA] = "wdma", + [MTK_DP_INTF] = "dp-intf", [MTK_DPI] = "dpi", [MTK_DSI] = "dsi", }; @@ -450,6 +451,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX] [DDP_COMPONENT_DRM_OVL_ADAPTOR] = { MTK_DISP_OVL_ADAPTOR, 0, &ddp_ovl_adaptor }, [DDP_COMPONENT_DSC0] = { MTK_DISP_DSC, 0, &ddp_dsc }, [DDP_COMPONENT_DSC1] = { MTK_DISP_DSC, 1, &ddp_dsc }, + [DDP_COMPONENT_DP_INTF0] = { MTK_DP_INTF, 0, &ddp_dpi }, + [DDP_COMPONENT_DP_INTF1] = { MTK_DP_INTF, 1, &ddp_dpi }, [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi }, [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi }, [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi }, @@ -575,6 +578,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, type == MTK_DISP_PWM || type == MTK_DISP_RDMA || type == MTK_DPI || + type == MTK_DP_INTF || type == MTK_DSI) return 0;
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index af9a6671f9c4..3084cc4e2830 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -38,6 +38,7 @@ enum mtk_ddp_comp_type { MTK_DISP_UFOE, MTK_DISP_WDMA, MTK_DPI, + MTK_DP_INTF, MTK_DSI, MTK_DDP_COMP_TYPE_MAX, }; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 78e79c8449c8..3b885ad61ac3 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -788,6 +788,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DPI }, { .compatible = "mediatek,mt8192-dpi", .data = (void *)MTK_DPI }, + { .compatible = "mediatek,mt8195-dp_intf", + .data = (void *)MTK_DP_INTF }, { .compatible = "mediatek,mt2701-dsi", .data = (void *)MTK_DSI }, { .compatible = "mediatek,mt8173-dsi", @@ -931,6 +933,7 @@ static int mtk_drm_probe(struct platform_device *pdev) comp_type == MTK_DISP_OVL_2L || comp_type == MTK_DISP_OVL_ADAPTOR || comp_type == MTK_DISP_RDMA || + comp_type == MTK_DP_INTF || comp_type == MTK_DPI || comp_type == MTK_DSI) { dev_info(dev, "Adding component match for %pOF\n",
Hi, Bo-Chen:
On Mon, 2022-06-20 at 20:10 +0800, Bo-Chen Chen wrote:
From: Guillaume Ranquet granquet@baylibre.com
dpintf is the displayport interface hardware unit. This unit is similar to dpi and can reuse most of the code.
This patch adds support for mt8195-dpintf to this dpi driver. Main differences are:
- 4 pixels for one round for dp_intf while dpi is 1 pixel for one
round. Therefore, pixel clock and timing parameter should be divided by 4 for dp_intf.
- Some features/functional components are not available for dpintf which are now excluded from code execution once is_dpintf is set. The main difference is some parts of hardware design between
dp_intf and dpi.
- Some register contents differ slightly between the two components.
To work around this I added register bits/masks with a DPINTF_ prefix and use them where different.
Based on a separate driver for dpintf created by Jitao shi jitao.shi@mediatek.com.
Signed-off-by: Markus Schneider-Pargmann msp@baylibre.com Signed-off-by: Guillaume Ranquet granquet@baylibre.com [Bo-Chen: Modify reviewers' comments.] Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com
drivers/gpu/drm/mediatek/mtk_dpi.c | 65 +++++++++++++++++++-- drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 13 +++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 4 ++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 + 5 files changed, 82 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index e186870ba3bc..2717b1741b7a 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -126,6 +126,7 @@ struct mtk_dpi_conf { const u32 *output_fmts; u32 num_output_fmts; bool is_ck_de_pol;
- bool is_dpintf; bool swap_input_support; /* Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH
(no shift) */ u32 dimension_mask; @@ -513,6 +514,14 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, pll_rate = clk_get_rate(dpi->tvd_clk);
vm.pixelclock = pll_rate / factor;
- /*
* For dp_intf, we need to divide clock by 4 because it's* 4 pixels for one round while dpi is 1 pixel for one round.*/- if (dpi->conf->is_dpintf)
vm.pixelclock /= 4;
I this this should define dpi->conf->round_pixels rather than dpi-
conf->is_dpintf.
- if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) || (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE)) clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2);
@@ -534,6 +543,17 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, hsync.sync_width = vm.hsync_len; hsync.back_porch = vm.hback_porch; hsync.front_porch = vm.hfront_porch;
- /*
* For dp_intf, we need to divide everything by 4 because it's* 4 pixels for one round while dpi is 1 pixel for one round.*/- if (dpi->conf->is_dpintf) {
hsync.sync_width = vm.hsync_len / 4;hsync.back_porch = vm.hback_porch / 4;hsync.front_porch = vm.hfront_porch / 4;- }
Ditto.
- hsync.shift_half_line = false; vsync_lodd.sync_width = vm.vsync_len; vsync_lodd.back_porch = vm.vback_porch;
@@ -575,11 +595,16 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, mtk_dpi_config_channel_limit(dpi); mtk_dpi_config_bit_num(dpi, dpi->bit_num); mtk_dpi_config_channel_swap(dpi, dpi->channel_swap);
- mtk_dpi_config_yc_map(dpi, dpi->yc_map); mtk_dpi_config_color_format(dpi, dpi->color_format);
- mtk_dpi_config_2n_h_fre(dpi);
- mtk_dpi_dual_edge(dpi);
- mtk_dpi_config_disable_edge(dpi);
- if (dpi->conf->is_dpintf) {
Separate this to an independent patch and give a better config name rather than dpi->conf->is_dpintf.
mtk_dpi_mask(dpi, DPI_CON, DPINTF_INPUT_2P_EN,DPINTF_INPUT_2P_EN);} else {
mtk_dpi_config_yc_map(dpi, dpi->yc_map);mtk_dpi_config_2n_h_fre(dpi);mtk_dpi_dual_edge(dpi);mtk_dpi_config_disable_edge(dpi);} mtk_dpi_sw_reset(dpi, false);
return 0;
@@ -817,6 +842,16 @@ static unsigned int mt8183_calculate_factor(int clock) return 2; }
[snip]
#define EDGE_SEL_EN BIT(5) #define H_FRE_2N BIT(25)
This seems not related to dpintf support.
Regards, CK
#endif /* __MTK_DPI_REGS_H */
On Tue, 2022-06-21 at 10:32 +0800, CK Hu wrote:
Hi, Bo-Chen:
On Mon, 2022-06-20 at 20:10 +0800, Bo-Chen Chen wrote:
From: Guillaume Ranquet granquet@baylibre.com
dpintf is the displayport interface hardware unit. This unit is similar to dpi and can reuse most of the code.
This patch adds support for mt8195-dpintf to this dpi driver. Main differences are:
- 4 pixels for one round for dp_intf while dpi is 1 pixel for one
round. Therefore, pixel clock and timing parameter should be divided by 4 for dp_intf.
- Some features/functional components are not available for dpintf which are now excluded from code execution once is_dpintf is
set. The main difference is some parts of hardware design between dp_intf and dpi.
- Some register contents differ slightly between the two
components. To work around this I added register bits/masks with a DPINTF_ prefix and use them where different.
Based on a separate driver for dpintf created by Jitao shi jitao.shi@mediatek.com.
Signed-off-by: Markus Schneider-Pargmann msp@baylibre.com Signed-off-by: Guillaume Ranquet granquet@baylibre.com [Bo-Chen: Modify reviewers' comments.] Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com
drivers/gpu/drm/mediatek/mtk_dpi.c | 65 +++++++++++++++++++-- drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 13 +++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 4 ++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 + 5 files changed, 82 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index e186870ba3bc..2717b1741b7a 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -126,6 +126,7 @@ struct mtk_dpi_conf { const u32 *output_fmts; u32 num_output_fmts; bool is_ck_de_pol;
- bool is_dpintf; bool swap_input_support; /* Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH
(no shift) */ u32 dimension_mask; @@ -513,6 +514,14 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, pll_rate = clk_get_rate(dpi->tvd_clk);
vm.pixelclock = pll_rate / factor;
- /*
* For dp_intf, we need to divide clock by 4 because it's* 4 pixels for one round while dpi is 1 pixel for one round.*/- if (dpi->conf->is_dpintf)
vm.pixelclock /= 4;I this this should define dpi->conf->round_pixels rather than dpi-
conf->is_dpintf.
ok, I will use this config and drop is_dpintf.
- if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) || (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE)) clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2);
@@ -534,6 +543,17 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, hsync.sync_width = vm.hsync_len; hsync.back_porch = vm.hback_porch; hsync.front_porch = vm.hfront_porch;
- /*
* For dp_intf, we need to divide everything by 4 because it's* 4 pixels for one round while dpi is 1 pixel for one round.*/- if (dpi->conf->is_dpintf) {
hsync.sync_width = vm.hsync_len / 4;hsync.back_porch = vm.hback_porch / 4;hsync.front_porch = vm.hfront_porch / 4;- }
Ditto.
- hsync.shift_half_line = false; vsync_lodd.sync_width = vm.vsync_len; vsync_lodd.back_porch = vm.vback_porch;
@@ -575,11 +595,16 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, mtk_dpi_config_channel_limit(dpi); mtk_dpi_config_bit_num(dpi, dpi->bit_num); mtk_dpi_config_channel_swap(dpi, dpi->channel_swap);
- mtk_dpi_config_yc_map(dpi, dpi->yc_map); mtk_dpi_config_color_format(dpi, dpi->color_format);
- mtk_dpi_config_2n_h_fre(dpi);
- mtk_dpi_dual_edge(dpi);
- mtk_dpi_config_disable_edge(dpi);
- if (dpi->conf->is_dpintf) {
Separate this to an independent patch and give a better config name rather than dpi->conf->is_dpintf.
this is separate config. I will modify like this: add new config "input_2pixel" for input two pixels in this patch: mtk_dpi_mask(dpi, DPI_CON, DPINTF_INPUT_2P_EN, DPINTF_INPUT_2P_EN);
and create another patch to add config "support_direct_pin" this config is only used for dpi which could be directly connect to pins while dp_intf is not.
+ if (dpi->conf->support_direct_pin) { + mtk_dpi_config_yc_map(dpi, dpi->yc_map); + mtk_dpi_config_2n_h_fre(dpi); + mtk_dpi_dual_edge(dpi); + mtk_dpi_config_disable_edge(dpi); + }
BRs, Bo-Chen
mtk_dpi_mask(dpi, DPI_CON, DPINTF_INPUT_2P_EN,DPINTF_INPUT_2P_EN);} else {
mtk_dpi_config_yc_map(dpi, dpi->yc_map);mtk_dpi_config_2n_h_fre(dpi);mtk_dpi_dual_edge(dpi);mtk_dpi_config_disable_edge(dpi);} mtk_dpi_sw_reset(dpi, false);
return 0;
@@ -817,6 +842,16 @@ static unsigned int mt8183_calculate_factor(int clock) return 2; }
[snip]
#define EDGE_SEL_EN BIT(5) #define H_FRE_2N BIT(25)
This seems not related to dpintf support.
Regards, CK
#endif /* __MTK_DPI_REGS_H */
We should enable/disable tvd_clk when power_on/power_off, so add this patch to do this.
Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com --- drivers/gpu/drm/mediatek/mtk_dpi.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 2717b1741b7a..f83ecb154457 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -455,6 +455,7 @@ static void mtk_dpi_power_off(struct mtk_dpi *dpi) mtk_dpi_disable(dpi); clk_disable_unprepare(dpi->pixel_clk); clk_disable_unprepare(dpi->engine_clk); + clk_disable_unprepare(dpi->tvd_clk); }
static int mtk_dpi_power_on(struct mtk_dpi *dpi) @@ -464,10 +465,16 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) if (++dpi->refcount != 1) return 0;
+ ret = clk_prepare_enable(dpi->tvd_clk); + if (ret) { + dev_err(dpi->dev, "Failed to enable tvd pll: %d\n", ret); + goto err_refcount; + } + ret = clk_prepare_enable(dpi->engine_clk); if (ret) { dev_err(dpi->dev, "Failed to enable engine clock: %d\n", ret); - goto err_refcount; + goto err_engine; }
ret = clk_prepare_enable(dpi->pixel_clk); @@ -484,6 +491,8 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi)
err_pixel: clk_disable_unprepare(dpi->engine_clk); +err_engine: + clk_disable_unprepare(dpi->tvd_clk); err_refcount: dpi->refcount--; return ret;
Hi, Bo-Chen:
On Mon, 2022-06-20 at 20:10 +0800, Bo-Chen Chen wrote:
We should enable/disable tvd_clk when power_on/power_off, so add this patch to do this.
Without this patch, what would happen? It seems this patch is redundant for these SoCs:
static const struct of_device_id mtk_dpi_of_ids[] = { { .compatible = "mediatek,mt2701-dpi", .data = &mt2701_conf, }, { .compatible = "mediatek,mt8173-dpi", .data = &mt8173_conf, }, { .compatible = "mediatek,mt8183-dpi", .data = &mt8183_conf, }, { .compatible = "mediatek,mt8192-dpi", .data = &mt8192_conf, }, { }, };
Regards, CK
Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com
drivers/gpu/drm/mediatek/mtk_dpi.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 2717b1741b7a..f83ecb154457 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -455,6 +455,7 @@ static void mtk_dpi_power_off(struct mtk_dpi *dpi) mtk_dpi_disable(dpi); clk_disable_unprepare(dpi->pixel_clk); clk_disable_unprepare(dpi->engine_clk);
- clk_disable_unprepare(dpi->tvd_clk);
}
static int mtk_dpi_power_on(struct mtk_dpi *dpi) @@ -464,10 +465,16 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) if (++dpi->refcount != 1) return 0;
- ret = clk_prepare_enable(dpi->tvd_clk);
- if (ret) {
dev_err(dpi->dev, "Failed to enable tvd pll: %d\n",ret);
goto err_refcount;- }
- ret = clk_prepare_enable(dpi->engine_clk); if (ret) { dev_err(dpi->dev, "Failed to enable engine clock:
%d\n", ret);
goto err_refcount;
goto err_engine;}
ret = clk_prepare_enable(dpi->pixel_clk);
@@ -484,6 +491,8 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi)
err_pixel: clk_disable_unprepare(dpi->engine_clk); +err_engine:
- clk_disable_unprepare(dpi->tvd_clk);
err_refcount: dpi->refcount--; return ret;
On Tue, 2022-06-21 at 10:55 +0800, CK Hu wrote:
Hi, Bo-Chen:
On Mon, 2022-06-20 at 20:10 +0800, Bo-Chen Chen wrote:
We should enable/disable tvd_clk when power_on/power_off, so add this patch to do this.
Without this patch, what would happen? It seems this patch is redundant for these SoCs:
static const struct of_device_id mtk_dpi_of_ids[] = { { .compatible = "mediatek,mt2701-dpi", .data = &mt2701_conf, }, { .compatible = "mediatek,mt8173-dpi", .data = &mt8173_conf, }, { .compatible = "mediatek,mt8183-dpi", .data = &mt8183_conf, }, { .compatible = "mediatek,mt8192-dpi", .data = &mt8192_conf, }, { }, };
Regards, CK
Hello CK,
IMO, this is a bug fix patch. From the usage of clock, if we want to use it, we should enable it . Therefore, I think we should add this and I will add a fix tag for this patch.
BRs, Bo-Chen
Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com
drivers/gpu/drm/mediatek/mtk_dpi.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 2717b1741b7a..f83ecb154457 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -455,6 +455,7 @@ static void mtk_dpi_power_off(struct mtk_dpi *dpi) mtk_dpi_disable(dpi); clk_disable_unprepare(dpi->pixel_clk); clk_disable_unprepare(dpi->engine_clk);
- clk_disable_unprepare(dpi->tvd_clk);
}
static int mtk_dpi_power_on(struct mtk_dpi *dpi) @@ -464,10 +465,16 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) if (++dpi->refcount != 1) return 0;
- ret = clk_prepare_enable(dpi->tvd_clk);
- if (ret) {
dev_err(dpi->dev, "Failed to enable tvd pll: %d\n",ret);
goto err_refcount;- }
- ret = clk_prepare_enable(dpi->engine_clk); if (ret) { dev_err(dpi->dev, "Failed to enable engine clock:
%d\n", ret);
goto err_refcount;
goto err_engine;}
ret = clk_prepare_enable(dpi->pixel_clk);
@@ -484,6 +491,8 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi)
err_pixel: clk_disable_unprepare(dpi->engine_clk); +err_engine:
- clk_disable_unprepare(dpi->tvd_clk);
err_refcount: dpi->refcount--; return ret;
On Tue, 2022-06-21 at 11:11 +0800, Rex-BC Chen wrote:
On Tue, 2022-06-21 at 10:55 +0800, CK Hu wrote:
Hi, Bo-Chen:
On Mon, 2022-06-20 at 20:10 +0800, Bo-Chen Chen wrote:
We should enable/disable tvd_clk when power_on/power_off, so add this patch to do this.
Without this patch, what would happen? It seems this patch is redundant for these SoCs:
static const struct of_device_id mtk_dpi_of_ids[] = { { .compatible = "mediatek,mt2701-dpi", .data = &mt2701_conf, }, { .compatible = "mediatek,mt8173-dpi", .data = &mt8173_conf, }, { .compatible = "mediatek,mt8183-dpi", .data = &mt8183_conf, }, { .compatible = "mediatek,mt8192-dpi", .data = &mt8192_conf, }, { }, };
Regards, CK
Hello CK,
IMO, this is a bug fix patch. From the usage of clock, if we want to use it, we should enable it . Therefore, I think we should add this and I will add a fix tag for this patch.
I think mt8173 chromebook use this driver for HDMI output. So mt8173 chromebook HDMI could not work normally?
Regards, CK
BRs, Bo-Chen
Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com
drivers/gpu/drm/mediatek/mtk_dpi.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 2717b1741b7a..f83ecb154457 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -455,6 +455,7 @@ static void mtk_dpi_power_off(struct mtk_dpi *dpi) mtk_dpi_disable(dpi); clk_disable_unprepare(dpi->pixel_clk); clk_disable_unprepare(dpi->engine_clk);
- clk_disable_unprepare(dpi->tvd_clk);
}
static int mtk_dpi_power_on(struct mtk_dpi *dpi) @@ -464,10 +465,16 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) if (++dpi->refcount != 1) return 0;
- ret = clk_prepare_enable(dpi->tvd_clk);
- if (ret) {
dev_err(dpi->dev, "Failed to enable tvd pll: %d\n",ret);
goto err_refcount;- }
- ret = clk_prepare_enable(dpi->engine_clk); if (ret) { dev_err(dpi->dev, "Failed to enable engine clock:
%d\n", ret);
goto err_refcount;
goto err_engine;}
ret = clk_prepare_enable(dpi->pixel_clk);
@@ -484,6 +491,8 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi)
err_pixel: clk_disable_unprepare(dpi->engine_clk); +err_engine:
- clk_disable_unprepare(dpi->tvd_clk);
err_refcount: dpi->refcount--; return ret;
On Tue, 2022-06-21 at 11:45 +0800, CK Hu wrote:
On Tue, 2022-06-21 at 11:11 +0800, Rex-BC Chen wrote:
On Tue, 2022-06-21 at 10:55 +0800, CK Hu wrote:
Hi, Bo-Chen:
On Mon, 2022-06-20 at 20:10 +0800, Bo-Chen Chen wrote:
We should enable/disable tvd_clk when power_on/power_off, so add this patch to do this.
Without this patch, what would happen? It seems this patch is redundant for these SoCs:
static const struct of_device_id mtk_dpi_of_ids[] = { { .compatible = "mediatek,mt2701-dpi", .data = &mt2701_conf, }, { .compatible = "mediatek,mt8173-dpi", .data = &mt8173_conf, }, { .compatible = "mediatek,mt8183-dpi", .data = &mt8183_conf, }, { .compatible = "mediatek,mt8192-dpi", .data = &mt8192_conf, }, { }, };
Regards, CK
Hello CK,
IMO, this is a bug fix patch. From the usage of clock, if we want to use it, we should enable it . Therefore, I think we should add this and I will add a fix tag for this patch.
I think mt8173 chromebook use this driver for HDMI output. So mt8173 chromebook HDMI could not work normally?
Regards, CK
Hmm.. I am not sure about this. But without this patch, dpi is also working in mt8183/mt8192. It may be related to the ccf driver. But anyway, I think we should do this whether ccf driver helps us to enable this clock.
BRs, Bo-Chen
BRs, Bo-Chen
Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com
drivers/gpu/drm/mediatek/mtk_dpi.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 2717b1741b7a..f83ecb154457 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -455,6 +455,7 @@ static void mtk_dpi_power_off(struct mtk_dpi *dpi) mtk_dpi_disable(dpi); clk_disable_unprepare(dpi->pixel_clk); clk_disable_unprepare(dpi->engine_clk);
- clk_disable_unprepare(dpi->tvd_clk);
}
static int mtk_dpi_power_on(struct mtk_dpi *dpi) @@ -464,10 +465,16 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) if (++dpi->refcount != 1) return 0;
- ret = clk_prepare_enable(dpi->tvd_clk);
- if (ret) {
dev_err(dpi->dev, "Failed to enable tvd pll:%d\n", ret);
goto err_refcount;- }
- ret = clk_prepare_enable(dpi->engine_clk); if (ret) { dev_err(dpi->dev, "Failed to enable engine
clock: %d\n", ret);
goto err_refcount;
goto err_engine;}
ret = clk_prepare_enable(dpi->pixel_clk);
@@ -484,6 +491,8 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi)
err_pixel: clk_disable_unprepare(dpi->engine_clk); +err_engine:
- clk_disable_unprepare(dpi->tvd_clk);
err_refcount: dpi->refcount--; return ret;
Hi, Rex:
On Tue, 2022-06-21 at 11:50 +0800, Rex-BC Chen wrote:
On Tue, 2022-06-21 at 11:45 +0800, CK Hu wrote:
On Tue, 2022-06-21 at 11:11 +0800, Rex-BC Chen wrote:
On Tue, 2022-06-21 at 10:55 +0800, CK Hu wrote:
Hi, Bo-Chen:
On Mon, 2022-06-20 at 20:10 +0800, Bo-Chen Chen wrote:
We should enable/disable tvd_clk when power_on/power_off, so add this patch to do this.
Without this patch, what would happen? It seems this patch is redundant for these SoCs:
static const struct of_device_id mtk_dpi_of_ids[] = { { .compatible = "mediatek,mt2701-dpi", .data = &mt2701_conf, }, { .compatible = "mediatek,mt8173-dpi", .data = &mt8173_conf, }, { .compatible = "mediatek,mt8183-dpi", .data = &mt8183_conf, }, { .compatible = "mediatek,mt8192-dpi", .data = &mt8192_conf, }, { }, };
Regards, CK
Hello CK,
IMO, this is a bug fix patch. From the usage of clock, if we want to use it, we should enable it . Therefore, I think we should add this and I will add a fix tag for this patch.
I think mt8173 chromebook use this driver for HDMI output. So mt8173 chromebook HDMI could not work normally?
Regards, CK
Hmm.. I am not sure about this. But without this patch, dpi is also working in mt8183/mt8192. It may be related to the ccf driver. But anyway, I think we should do this whether ccf driver helps us to enable this clock.
OK. So, could you help to fix the bug in ccf? If HDMI is disabled but ccf still turn on this clock, the power would be wasted.
Regards, CK
BRs, Bo-Chen
BRs, Bo-Chen
Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com
drivers/gpu/drm/mediatek/mtk_dpi.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 2717b1741b7a..f83ecb154457 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -455,6 +455,7 @@ static void mtk_dpi_power_off(struct mtk_dpi *dpi) mtk_dpi_disable(dpi); clk_disable_unprepare(dpi->pixel_clk); clk_disable_unprepare(dpi->engine_clk);
- clk_disable_unprepare(dpi->tvd_clk);
}
static int mtk_dpi_power_on(struct mtk_dpi *dpi) @@ -464,10 +465,16 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) if (++dpi->refcount != 1) return 0;
- ret = clk_prepare_enable(dpi->tvd_clk);
- if (ret) {
dev_err(dpi->dev, "Failed to enable tvd pll:%d\n", ret);
goto err_refcount;- }
- ret = clk_prepare_enable(dpi->engine_clk); if (ret) { dev_err(dpi->dev, "Failed to enable engine
clock: %d\n", ret);
goto err_refcount;
goto err_engine;}
ret = clk_prepare_enable(dpi->pixel_clk);
@@ -484,6 +491,8 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi)
err_pixel: clk_disable_unprepare(dpi->engine_clk); +err_engine:
- clk_disable_unprepare(dpi->tvd_clk);
err_refcount: dpi->refcount--; return ret;
On Tue, 2022-06-21 at 12:08 +0800, CK Hu wrote:
Hi, Rex:
On Tue, 2022-06-21 at 11:50 +0800, Rex-BC Chen wrote:
On Tue, 2022-06-21 at 11:45 +0800, CK Hu wrote:
On Tue, 2022-06-21 at 11:11 +0800, Rex-BC Chen wrote:
On Tue, 2022-06-21 at 10:55 +0800, CK Hu wrote:
Hi, Bo-Chen:
On Mon, 2022-06-20 at 20:10 +0800, Bo-Chen Chen wrote:
We should enable/disable tvd_clk when power_on/power_off, so add this patch to do this.
Without this patch, what would happen? It seems this patch is redundant for these SoCs:
static const struct of_device_id mtk_dpi_of_ids[] = { { .compatible = "mediatek,mt2701-dpi", .data = &mt2701_conf, }, { .compatible = "mediatek,mt8173-dpi", .data = &mt8173_conf, }, { .compatible = "mediatek,mt8183-dpi", .data = &mt8183_conf, }, { .compatible = "mediatek,mt8192-dpi", .data = &mt8192_conf, }, { }, };
Regards, CK
Hello CK,
IMO, this is a bug fix patch. From the usage of clock, if we want to use it, we should enable it . Therefore, I think we should add this and I will add a fix tag for this patch.
I think mt8173 chromebook use this driver for HDMI output. So mt8173 chromebook HDMI could not work normally?
Regards, CK
Hmm.. I am not sure about this. But without this patch, dpi is also working in mt8183/mt8192. It may be related to the ccf driver. But anyway, I think we should do this whether ccf driver helps us to enable this clock.
OK. So, could you help to fix the bug in ccf? If HDMI is disabled but ccf still turn on this clock, the power would be wasted.
Regards, CK
I am also testing if we don't have this patch and it also "works" (dpintf is working fine). do you think we need this patch or just drop this?
For the ccf driver, I am not familiar to ccf and also not a expert of ccf. It just a guest for this. I am not sure whether it's a "bug" or just a. And I think it's not the purpose of this series. If there is any issue, I think we will fix it in the future.
BRs, Bo-Chen
BRs, Bo-Chen
BRs, Bo-Chen
Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com
drivers/gpu/drm/mediatek/mtk_dpi.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 2717b1741b7a..f83ecb154457 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -455,6 +455,7 @@ static void mtk_dpi_power_off(struct mtk_dpi *dpi) mtk_dpi_disable(dpi); clk_disable_unprepare(dpi->pixel_clk); clk_disable_unprepare(dpi->engine_clk);
- clk_disable_unprepare(dpi->tvd_clk);
}
static int mtk_dpi_power_on(struct mtk_dpi *dpi) @@ -464,10 +465,16 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) if (++dpi->refcount != 1) return 0;
- ret = clk_prepare_enable(dpi->tvd_clk);
- if (ret) {
dev_err(dpi->dev, "Failed to enable tvd pll:%d\n", ret);
goto err_refcount;- }
- ret = clk_prepare_enable(dpi->engine_clk); if (ret) { dev_err(dpi->dev, "Failed to enable engine
clock: %d\n", ret);
goto err_refcount;
goto err_engine;}
ret = clk_prepare_enable(dpi->pixel_clk);
@@ -484,6 +491,8 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi)
err_pixel: clk_disable_unprepare(dpi->engine_clk); +err_engine:
- clk_disable_unprepare(dpi->tvd_clk);
err_refcount: dpi->refcount--; return ret;
Hi, Rex:
On Tue, 2022-06-21 at 13:47 +0800, Rex-BC Chen wrote:
On Tue, 2022-06-21 at 12:08 +0800, CK Hu wrote:
Hi, Rex:
On Tue, 2022-06-21 at 11:50 +0800, Rex-BC Chen wrote:
On Tue, 2022-06-21 at 11:45 +0800, CK Hu wrote:
On Tue, 2022-06-21 at 11:11 +0800, Rex-BC Chen wrote:
On Tue, 2022-06-21 at 10:55 +0800, CK Hu wrote:
Hi, Bo-Chen:
On Mon, 2022-06-20 at 20:10 +0800, Bo-Chen Chen wrote: > We should enable/disable tvd_clk when power_on/power_off, > so > add > this > patch to do this.
Without this patch, what would happen? It seems this patch is redundant for these SoCs:
static const struct of_device_id mtk_dpi_of_ids[] = { { .compatible = "mediatek,mt2701-dpi", .data = &mt2701_conf, }, { .compatible = "mediatek,mt8173-dpi", .data = &mt8173_conf, }, { .compatible = "mediatek,mt8183-dpi", .data = &mt8183_conf, }, { .compatible = "mediatek,mt8192-dpi", .data = &mt8192_conf, }, { }, };
Regards, CK
Hello CK,
IMO, this is a bug fix patch. From the usage of clock, if we want to use it, we should enable it . Therefore, I think we should add this and I will add a fix tag for this patch.
I think mt8173 chromebook use this driver for HDMI output. So mt8173 chromebook HDMI could not work normally?
Regards, CK
Hmm.. I am not sure about this. But without this patch, dpi is also working in mt8183/mt8192. It may be related to the ccf driver. But anyway, I think we should do this whether ccf driver helps us to enable this clock.
OK. So, could you help to fix the bug in ccf? If HDMI is disabled but ccf still turn on this clock, the power would be wasted.
Regards, CK
I am also testing if we don't have this patch and it also "works" (dpintf is working fine). do you think we need this patch or just drop this?
For the ccf driver, I am not familiar to ccf and also not a expert of ccf. It just a guest for this. I am not sure whether it's a "bug" or just a. And I think it's not the purpose of this series. If there is any issue, I think we will fix it in the future.
Because we have no idea how this works, I think it's better to drop this patch.
Regards, CK
BRs, Bo-Chen
BRs, Bo-Chen
BRs, Bo-Chen
> > Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com > --- > drivers/gpu/drm/mediatek/mtk_dpi.c | 11 ++++++++++- > 1 file changed, 10 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c > b/drivers/gpu/drm/mediatek/mtk_dpi.c > index 2717b1741b7a..f83ecb154457 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c > @@ -455,6 +455,7 @@ static void mtk_dpi_power_off(struct > mtk_dpi > *dpi) > mtk_dpi_disable(dpi); > clk_disable_unprepare(dpi->pixel_clk); > clk_disable_unprepare(dpi->engine_clk); > + clk_disable_unprepare(dpi->tvd_clk); > } > > static int mtk_dpi_power_on(struct mtk_dpi *dpi) > @@ -464,10 +465,16 @@ static int mtk_dpi_power_on(struct > mtk_dpi > *dpi) > if (++dpi->refcount != 1) > return 0; > > + ret = clk_prepare_enable(dpi->tvd_clk); > + if (ret) { > + dev_err(dpi->dev, "Failed to enable tvd pll: > %d\n", > ret); > + goto err_refcount; > + } > + > ret = clk_prepare_enable(dpi->engine_clk); > if (ret) { > dev_err(dpi->dev, "Failed to enable engine > clock: > %d\n", ret); > - goto err_refcount; > + goto err_engine; > } > > ret = clk_prepare_enable(dpi->pixel_clk); > @@ -484,6 +491,8 @@ static int mtk_dpi_power_on(struct > mtk_dpi > *dpi) > > err_pixel: > clk_disable_unprepare(dpi->engine_clk); > +err_engine: > + clk_disable_unprepare(dpi->tvd_clk); > err_refcount: > dpi->refcount--; > return ret;
On Tue, 2022-06-21 at 13:54 +0800, CK Hu wrote:
Hi, Rex:
On Tue, 2022-06-21 at 13:47 +0800, Rex-BC Chen wrote:
On Tue, 2022-06-21 at 12:08 +0800, CK Hu wrote:
Hi, Rex:
On Tue, 2022-06-21 at 11:50 +0800, Rex-BC Chen wrote:
On Tue, 2022-06-21 at 11:45 +0800, CK Hu wrote:
On Tue, 2022-06-21 at 11:11 +0800, Rex-BC Chen wrote:
On Tue, 2022-06-21 at 10:55 +0800, CK Hu wrote: > Hi, Bo-Chen: > > On Mon, 2022-06-20 at 20:10 +0800, Bo-Chen Chen wrote: > > We should enable/disable tvd_clk when > > power_on/power_off, > > so > > add > > this > > patch to do this. > > Without this patch, what would happen? > It seems this patch is redundant for these SoCs: > > static const struct of_device_id mtk_dpi_of_ids[] = { > { .compatible = "mediatek,mt2701-dpi", > .data = &mt2701_conf, > }, > { .compatible = "mediatek,mt8173-dpi", > .data = &mt8173_conf, > }, > { .compatible = "mediatek,mt8183-dpi", > .data = &mt8183_conf, > }, > { .compatible = "mediatek,mt8192-dpi", > .data = &mt8192_conf, > }, > { }, > }; > > Regards, > CK >
Hello CK,
IMO, this is a bug fix patch. From the usage of clock, if we want to use it, we should enable it . Therefore, I think we should add this and I will add a fix tag for this patch.
I think mt8173 chromebook use this driver for HDMI output. So mt8173 chromebook HDMI could not work normally?
Regards, CK
Hmm.. I am not sure about this. But without this patch, dpi is also working in mt8183/mt8192. It may be related to the ccf driver. But anyway, I think we should do this whether ccf driver helps us to enable this clock.
OK. So, could you help to fix the bug in ccf? If HDMI is disabled but ccf still turn on this clock, the power would be wasted.
Regards, CK
I am also testing if we don't have this patch and it also "works" (dpintf is working fine). do you think we need this patch or just drop this?
For the ccf driver, I am not familiar to ccf and also not a expert of ccf. It just a guest for this. I am not sure whether it's a "bug" or just a. And I think it's not the purpose of this series. If there is any issue, I think we will fix it in the future.
Because we have no idea how this works, I think it's better to drop this patch.
Regards, CK
ok, I will drop this patch in next version.
BRs, Bo-Chen
BRs, Bo-Chen
BRs, Bo-Chen
BRs, Bo-Chen > > > > > Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com > > --- > > drivers/gpu/drm/mediatek/mtk_dpi.c | 11 ++++++++++- > > 1 file changed, 10 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c > > b/drivers/gpu/drm/mediatek/mtk_dpi.c > > index 2717b1741b7a..f83ecb154457 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c > > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c > > @@ -455,6 +455,7 @@ static void > > mtk_dpi_power_off(struct > > mtk_dpi > > *dpi) > > mtk_dpi_disable(dpi); > > clk_disable_unprepare(dpi->pixel_clk); > > clk_disable_unprepare(dpi->engine_clk); > > + clk_disable_unprepare(dpi->tvd_clk); > > } > > > > static int mtk_dpi_power_on(struct mtk_dpi *dpi) > > @@ -464,10 +465,16 @@ static int > > mtk_dpi_power_on(struct > > mtk_dpi > > *dpi) > > if (++dpi->refcount != 1) > > return 0; > > > > + ret = clk_prepare_enable(dpi->tvd_clk); > > + if (ret) { > > + dev_err(dpi->dev, "Failed to enable tvd > > pll: > > %d\n", > > ret); > > + goto err_refcount; > > + } > > + > > ret = clk_prepare_enable(dpi->engine_clk); > > if (ret) { > > dev_err(dpi->dev, "Failed to enable > > engine > > clock: > > %d\n", ret); > > - goto err_refcount; > > + goto err_engine; > > } > > > > ret = clk_prepare_enable(dpi->pixel_clk); > > @@ -484,6 +491,8 @@ static int mtk_dpi_power_on(struct > > mtk_dpi > > *dpi) > > > > err_pixel: > > clk_disable_unprepare(dpi->engine_clk); > > +err_engine: > > + clk_disable_unprepare(dpi->tvd_clk); > > err_refcount: > > dpi->refcount--; > > return ret; > >
Dp_intf supports YUV422 as output format. In MT8195 Chrome project, YUV422 output format is used for 4K resolution.
Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com --- drivers/gpu/drm/mediatek/mtk_dpi.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index f83ecb154457..fc76ccad0a82 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -692,7 +692,10 @@ static int mtk_dpi_bridge_atomic_check(struct drm_bridge *bridge, dpi->bit_num = MTK_DPI_OUT_BIT_NUM_8BITS; dpi->channel_swap = MTK_DPI_OUT_CHANNEL_SWAP_RGB; dpi->yc_map = MTK_DPI_OUT_YC_MAP_RGB; - dpi->color_format = MTK_DPI_COLOR_FORMAT_RGB; + if (out_bus_format == MEDIA_BUS_FMT_YUYV8_1X16) + dpi->color_format = MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL; + else + dpi->color_format = MTK_DPI_COLOR_FORMAT_RGB;
return 0; }
Hi, Bo-Chen:
On Mon, 2022-06-20 at 20:10 +0800, Bo-Chen Chen wrote:
Dp_intf supports YUV422 as output format. In MT8195 Chrome project, YUV422 output format is used for 4K resolution.
Move this patch before [1]. Otherwise, [1] would result in a bug.
[1] [v12,10/14] drm/mediatek: dpi: Add dpintf support
Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com
drivers/gpu/drm/mediatek/mtk_dpi.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index f83ecb154457..fc76ccad0a82 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -692,7 +692,10 @@ static int mtk_dpi_bridge_atomic_check(struct drm_bridge *bridge, dpi->bit_num = MTK_DPI_OUT_BIT_NUM_8BITS; dpi->channel_swap = MTK_DPI_OUT_CHANNEL_SWAP_RGB; dpi->yc_map = MTK_DPI_OUT_YC_MAP_RGB;
- dpi->color_format = MTK_DPI_COLOR_FORMAT_RGB;
- if (out_bus_format == MEDIA_BUS_FMT_YUYV8_1X16)
dpi->color_format =MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL;
- else
dpi->color_format = MTK_DPI_COLOR_FORMAT_RGB;
If out_bus_format is MEDIA_BUS_FMT_YUV8_1X24, the color_format is MTK_DPI_COLOR_FORMAT_RGB?
Regards, CK
return 0; }
On Tue, 2022-06-21 at 11:04 +0800, CK Hu wrote:
Hi, Bo-Chen:
On Mon, 2022-06-20 at 20:10 +0800, Bo-Chen Chen wrote:
Dp_intf supports YUV422 as output format. In MT8195 Chrome project, YUV422 output format is used for 4K resolution.
Move this patch before [1]. Otherwise, [1] would result in a bug.
[1] [v12,10/14] drm/mediatek: dpi: Add dpintf support
ok, I will do this.
Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com
drivers/gpu/drm/mediatek/mtk_dpi.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index f83ecb154457..fc76ccad0a82 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -692,7 +692,10 @@ static int mtk_dpi_bridge_atomic_check(struct drm_bridge *bridge, dpi->bit_num = MTK_DPI_OUT_BIT_NUM_8BITS; dpi->channel_swap = MTK_DPI_OUT_CHANNEL_SWAP_RGB; dpi->yc_map = MTK_DPI_OUT_YC_MAP_RGB;
- dpi->color_format = MTK_DPI_COLOR_FORMAT_RGB;
- if (out_bus_format == MEDIA_BUS_FMT_YUYV8_1X16)
dpi->color_format =MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL;
- else
dpi->color_format = MTK_DPI_COLOR_FORMAT_RGB;If out_bus_format is MEDIA_BUS_FMT_YUV8_1X24, the color_format is MTK_DPI_COLOR_FORMAT_RGB?
I will drop output format of MEDIA_BUS_FMT_YUV8_1X24 for mt8195_dpintf because if support MEDIA_BUS_FMT_YUV8_1X24 means support RGB888.
BRs, Bo-Chen
Regards, CK
return 0; }
From: Guillaume Ranquet granquet@baylibre.com
Enabling the dpi too early causes glitches on screen.
Move the call to mtk_dpi_enable() at the end of the bridge_enable callback to ensure everything is setup properly before enabling dpi.
Fixes: f89c696e7f63 ("drm/mediatek: mtk_dpi: Convert to bridge driver") Signed-off-by: Guillaume Ranquet granquet@baylibre.com Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com --- drivers/gpu/drm/mediatek/mtk_dpi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index fc76ccad0a82..220e9b18e2cd 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -486,7 +486,6 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) if (dpi->pinctrl && dpi->pins_dpi) pinctrl_select_state(dpi->pinctrl, dpi->pins_dpi);
- mtk_dpi_enable(dpi); return 0;
err_pixel: @@ -731,6 +730,7 @@ static void mtk_dpi_bridge_enable(struct drm_bridge *bridge)
mtk_dpi_power_on(dpi); mtk_dpi_set_display_mode(dpi, &dpi->mode); + mtk_dpi_enable(dpi); }
static enum drm_mode_status
Hi, Bo-Chen:
On Mon, 2022-06-20 at 20:10 +0800, Bo-Chen Chen wrote:
From: Guillaume Ranquet granquet@baylibre.com
Enabling the dpi too early causes glitches on screen.
Move the call to mtk_dpi_enable() at the end of the bridge_enable callback to ensure everything is setup properly before enabling dpi.
Fixes: f89c696e7f63 ("drm/mediatek: mtk_dpi: Convert to bridge driver")
I think this problem happen in the first patch [1].
[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/commi...
Regards, CK
Signed-off-by: Guillaume Ranquet granquet@baylibre.com Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com
drivers/gpu/drm/mediatek/mtk_dpi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index fc76ccad0a82..220e9b18e2cd 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -486,7 +486,6 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) if (dpi->pinctrl && dpi->pins_dpi) pinctrl_select_state(dpi->pinctrl, dpi->pins_dpi);
- mtk_dpi_enable(dpi); return 0;
err_pixel: @@ -731,6 +730,7 @@ static void mtk_dpi_bridge_enable(struct drm_bridge *bridge)
mtk_dpi_power_on(dpi); mtk_dpi_set_display_mode(dpi, &dpi->mode);
- mtk_dpi_enable(dpi);
}
static enum drm_mode_status
On Tue, 2022-06-21 at 11:18 +0800, CK Hu wrote:
Hi, Bo-Chen:
On Mon, 2022-06-20 at 20:10 +0800, Bo-Chen Chen wrote:
From: Guillaume Ranquet granquet@baylibre.com
Enabling the dpi too early causes glitches on screen.
Move the call to mtk_dpi_enable() at the end of the bridge_enable callback to ensure everything is setup properly before enabling dpi.
Fixes: f89c696e7f63 ("drm/mediatek: mtk_dpi: Convert to bridge driver")
I think this problem happen in the first patch [1].
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/commi...
Regards, CK
ok, I will fix this.
BRs, Bo-Chen
Signed-off-by: Guillaume Ranquet granquet@baylibre.com Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com
drivers/gpu/drm/mediatek/mtk_dpi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index fc76ccad0a82..220e9b18e2cd 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -486,7 +486,6 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) if (dpi->pinctrl && dpi->pins_dpi) pinctrl_select_state(dpi->pinctrl, dpi->pins_dpi);
- mtk_dpi_enable(dpi); return 0;
err_pixel: @@ -731,6 +730,7 @@ static void mtk_dpi_bridge_enable(struct drm_bridge *bridge)
mtk_dpi_power_on(dpi); mtk_dpi_set_display_mode(dpi, &dpi->mode);
- mtk_dpi_enable(dpi);
}
static enum drm_mode_status
From: Guillaume Ranquet granquet@baylibre.com
Matrix selection is a new feature for both dpi and dpintf of MT8195. Add a mtk_dpi_matrix_sel() helper to update the DPI_MATRIX_SET register depending on the color format.
Signed-off-by: Guillaume Ranquet granquet@baylibre.com Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com --- drivers/gpu/drm/mediatek/mtk_dpi.c | 29 +++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 3 +++ 2 files changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 220e9b18e2cd..8a9151cb1622 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -135,6 +135,7 @@ struct mtk_dpi_conf { u32 channel_swap_shift; u32 yuv422_en_bit; u32 csc_enable_bit; + bool matrx_sel_support; };
static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) @@ -398,6 +399,31 @@ static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi) mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN); }
+static void mtk_dpi_matrix_sel(struct mtk_dpi *dpi, + enum mtk_dpi_out_color_format format) +{ + u32 matrix_sel = 0; + + if (!dpi->conf->matrx_sel_support) { + dev_info(dpi->dev, "matrix_sel is not supported.\n"); + return; + } + + switch (format) { + case MTK_DPI_COLOR_FORMAT_YCBCR_422: + case MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL: + case MTK_DPI_COLOR_FORMAT_YCBCR_444: + case MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL: + case MTK_DPI_COLOR_FORMAT_XV_YCC: + if (dpi->mode.hdisplay <= 720) + matrix_sel = 0x2; + break; + default: + break; + } + mtk_dpi_mask(dpi, DPI_MATRIX_SET, matrix_sel, INT_MATRIX_SEL_MASK); +} + static void mtk_dpi_config_color_format(struct mtk_dpi *dpi, enum mtk_dpi_out_color_format format) { @@ -405,6 +431,7 @@ static void mtk_dpi_config_color_format(struct mtk_dpi *dpi, (format == MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL)) { mtk_dpi_config_yuv422_enable(dpi, false); mtk_dpi_config_csc_enable(dpi, true); + mtk_dpi_matrix_sel(dpi, format); if (dpi->conf->swap_input_support) mtk_dpi_config_swap_input(dpi, false); mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_BGR); @@ -412,6 +439,7 @@ static void mtk_dpi_config_color_format(struct mtk_dpi *dpi, (format == MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL)) { mtk_dpi_config_yuv422_enable(dpi, true); mtk_dpi_config_csc_enable(dpi, true); + mtk_dpi_matrix_sel(dpi, format); if (dpi->conf->swap_input_support) mtk_dpi_config_swap_input(dpi, true); else @@ -951,6 +979,7 @@ static const struct mtk_dpi_conf mt8195_dpintf_conf = { .channel_swap_shift = DPINTF_CH_SWAP, .yuv422_en_bit = DPINTF_YUV422_EN, .csc_enable_bit = DPINTF_CSC_ENABLE, + .matrx_sel_support = true, };
static int mtk_dpi_probe(struct platform_device *pdev) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h index f7f0272dbd6a..96c117202d0d 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h @@ -230,4 +230,7 @@ #define EDGE_SEL_EN BIT(5) #define H_FRE_2N BIT(25)
+#define DPI_MATRIX_SET 0xB4 +#define INT_MATRIX_SEL_MASK (0x1F << 0) + #endif /* __MTK_DPI_REGS_H */
Hi, Bo-Chen:
On Mon, 2022-06-20 at 20:10 +0800, Bo-Chen Chen wrote:
From: Guillaume Ranquet granquet@baylibre.com
Matrix selection is a new feature for both dpi and dpintf of MT8195. Add a mtk_dpi_matrix_sel() helper to update the DPI_MATRIX_SET register depending on the color format.
Describe more about what this do.
Signed-off-by: Guillaume Ranquet granquet@baylibre.com Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com
drivers/gpu/drm/mediatek/mtk_dpi.c | 29 +++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 3 +++ 2 files changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 220e9b18e2cd..8a9151cb1622 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -135,6 +135,7 @@ struct mtk_dpi_conf { u32 channel_swap_shift; u32 yuv422_en_bit; u32 csc_enable_bit;
- bool matrx_sel_support;
};
static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) @@ -398,6 +399,31 @@ static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi) mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN); }
+static void mtk_dpi_matrix_sel(struct mtk_dpi *dpi,
enum mtk_dpi_out_color_format format)+{
- u32 matrix_sel = 0;
- if (!dpi->conf->matrx_sel_support) {
dev_info(dpi->dev, "matrix_sel is not supported.\n");
So for this SoC, there would be something wrong? I still does not understand what this feature is.
static const struct of_device_id mtk_dpi_of_ids[] = { { .compatible = "mediatek,mt2701-dpi", .data = &mt2701_conf, }, { .compatible = "mediatek,mt8173-dpi", .data = &mt8173_conf, }, { .compatible = "mediatek,mt8183-dpi", .data = &mt8183_conf, }, { .compatible = "mediatek,mt8192-dpi", .data = &mt8192_conf, }, { }, };
return;- }
- switch (format) {
- case MTK_DPI_COLOR_FORMAT_YCBCR_422:
- case MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL:
- case MTK_DPI_COLOR_FORMAT_YCBCR_444:
- case MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL:
- case MTK_DPI_COLOR_FORMAT_XV_YCC:
if (dpi->mode.hdisplay <= 720)matrix_sel = 0x2;
Symbolize 0x2.
break;- default:
If format is MTK_DPI_COLOR_FORMAT_YCBCR_422 first, then format change to MTK_DPI_COLOR_FORMAT_RGB and matrix_sel would still be 0x2. Is this correct?
Regards, CK
break;- }
- mtk_dpi_mask(dpi, DPI_MATRIX_SET, matrix_sel,
INT_MATRIX_SEL_MASK); +}
static void mtk_dpi_config_color_format(struct mtk_dpi *dpi, enum mtk_dpi_out_color_format format) { @@ -405,6 +431,7 @@ static void mtk_dpi_config_color_format(struct mtk_dpi *dpi, (format == MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL)) { mtk_dpi_config_yuv422_enable(dpi, false); mtk_dpi_config_csc_enable(dpi, true);
mtk_dpi_matrix_sel(dpi, format);MTK_DPI_OUT_CHANNEL_SWAP_BGR); @@ -412,6 +439,7 @@ static void mtk_dpi_config_color_format(struct mtk_dpi *dpi, (format == MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL)) { mtk_dpi_config_yuv422_enable(dpi, true); mtk_dpi_config_csc_enable(dpi, true);
mtk_dpi_matrix_sel(dpi, format);@@ -951,6 +979,7 @@ static const struct mtk_dpi_conf mt8195_dpintf_conf = { .channel_swap_shift = DPINTF_CH_SWAP, .yuv422_en_bit = DPINTF_YUV422_EN, .csc_enable_bit = DPINTF_CSC_ENABLE,
- .matrx_sel_support = true,
};
static int mtk_dpi_probe(struct platform_device *pdev) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h index f7f0272dbd6a..96c117202d0d 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h @@ -230,4 +230,7 @@ #define EDGE_SEL_EN BIT(5) #define H_FRE_2N BIT(25)
+#define DPI_MATRIX_SET 0xB4 +#define INT_MATRIX_SEL_MASK (0x1F << 0)
#endif /* __MTK_DPI_REGS_H */
On Tue, 2022-06-21 at 11:33 +0800, CK Hu wrote:
Hi, Bo-Chen:
On Mon, 2022-06-20 at 20:10 +0800, Bo-Chen Chen wrote:
From: Guillaume Ranquet granquet@baylibre.com
Matrix selection is a new feature for both dpi and dpintf of MT8195. Add a mtk_dpi_matrix_sel() helper to update the DPI_MATRIX_SET register depending on the color format.
Describe more about what this do.
this feature is color format transfer. For mt8195, the input format is RGB888 andd output format could be YUV422. do you think I should squash this patch into [v12,12/14] drm/mediatek: dpi: Add YUV422 output support?
Signed-off-by: Guillaume Ranquet granquet@baylibre.com Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com
drivers/gpu/drm/mediatek/mtk_dpi.c | 29 +++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 3 +++ 2 files changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 220e9b18e2cd..8a9151cb1622 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -135,6 +135,7 @@ struct mtk_dpi_conf { u32 channel_swap_shift; u32 yuv422_en_bit; u32 csc_enable_bit;
- bool matrx_sel_support;
};
static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) @@ -398,6 +399,31 @@ static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi) mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN); }
+static void mtk_dpi_matrix_sel(struct mtk_dpi *dpi,
enum mtk_dpi_out_color_format format)+{
- u32 matrix_sel = 0;
- if (!dpi->conf->matrx_sel_support) {
dev_info(dpi->dev, "matrix_sel is not supported.\n");So for this SoC, there would be something wrong? I still does not understand what this feature is.
static const struct of_device_id mtk_dpi_of_ids[] = { { .compatible = "mediatek,mt2701-dpi", .data = &mt2701_conf, }, { .compatible = "mediatek,mt8173-dpi", .data = &mt8173_conf, }, { .compatible = "mediatek,mt8183-dpi", .data = &mt8183_conf, }, { .compatible = "mediatek,mt8192-dpi", .data = &mt8192_conf, }, { }, };
return;- }
- switch (format) {
- case MTK_DPI_COLOR_FORMAT_YCBCR_422:
- case MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL:
- case MTK_DPI_COLOR_FORMAT_YCBCR_444:
- case MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL:
- case MTK_DPI_COLOR_FORMAT_XV_YCC:
if (dpi->mode.hdisplay <= 720)matrix_sel = 0x2;Symbolize 0x2.
break;- default:
If format is MTK_DPI_COLOR_FORMAT_YCBCR_422 first, then format change to MTK_DPI_COLOR_FORMAT_RGB and matrix_sel would still be 0x2. Is this correct?
Regards, CK
break;- }
- mtk_dpi_mask(dpi, DPI_MATRIX_SET, matrix_sel,
INT_MATRIX_SEL_MASK); +}
static void mtk_dpi_config_color_format(struct mtk_dpi *dpi, enum mtk_dpi_out_color_format format) { @@ -405,6 +431,7 @@ static void mtk_dpi_config_color_format(struct mtk_dpi *dpi, (format == MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL)) { mtk_dpi_config_yuv422_enable(dpi, false); mtk_dpi_config_csc_enable(dpi, true);
mtk_dpi_matrix_sel(dpi, format);MTK_DPI_OUT_CHANNEL_SWAP_BGR); @@ -412,6 +439,7 @@ static void mtk_dpi_config_color_format(struct mtk_dpi *dpi, (format == MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL)) { mtk_dpi_config_yuv422_enable(dpi, true); mtk_dpi_config_csc_enable(dpi, true);
mtk_dpi_matrix_sel(dpi, format);@@ -951,6 +979,7 @@ static const struct mtk_dpi_conf mt8195_dpintf_conf = { .channel_swap_shift = DPINTF_CH_SWAP, .yuv422_en_bit = DPINTF_YUV422_EN, .csc_enable_bit = DPINTF_CSC_ENABLE,
- .matrx_sel_support = true,
};
static int mtk_dpi_probe(struct platform_device *pdev) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h index f7f0272dbd6a..96c117202d0d 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h @@ -230,4 +230,7 @@ #define EDGE_SEL_EN BIT(5) #define H_FRE_2N BIT(25)
+#define DPI_MATRIX_SET 0xB4 +#define INT_MATRIX_SEL_MASK (0x1F << 0)
#endif /* __MTK_DPI_REGS_H */
Hi, Rex:
On Tue, 2022-06-21 at 16:41 +0800, Rex-BC Chen wrote:
On Tue, 2022-06-21 at 11:33 +0800, CK Hu wrote:
Hi, Bo-Chen:
On Mon, 2022-06-20 at 20:10 +0800, Bo-Chen Chen wrote:
From: Guillaume Ranquet granquet@baylibre.com
Matrix selection is a new feature for both dpi and dpintf of MT8195. Add a mtk_dpi_matrix_sel() helper to update the DPI_MATRIX_SET register depending on the color format.
Describe more about what this do.
this feature is color format transfer. For mt8195, the input format is RGB888 andd output format could be YUV422. do you think I should squash this patch into [v12,12/14] drm/mediatek: dpi: Add YUV422 output support?
OK, squash these two patches and add this description into commit message. For RGB input and RGB output, I think this function should be disabled.
Regards, CK
Signed-off-by: Guillaume Ranquet granquet@baylibre.com Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com
drivers/gpu/drm/mediatek/mtk_dpi.c | 29 +++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 3 +++ 2 files changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 220e9b18e2cd..8a9151cb1622 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -135,6 +135,7 @@ struct mtk_dpi_conf { u32 channel_swap_shift; u32 yuv422_en_bit; u32 csc_enable_bit;
- bool matrx_sel_support;
};
static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) @@ -398,6 +399,31 @@ static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi) mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN); }
+static void mtk_dpi_matrix_sel(struct mtk_dpi *dpi,
enum mtk_dpi_out_color_format format)+{
- u32 matrix_sel = 0;
- if (!dpi->conf->matrx_sel_support) {
dev_info(dpi->dev, "matrix_sel is not supported.\n");So for this SoC, there would be something wrong? I still does not understand what this feature is.
static const struct of_device_id mtk_dpi_of_ids[] = { { .compatible = "mediatek,mt2701-dpi", .data = &mt2701_conf, }, { .compatible = "mediatek,mt8173-dpi", .data = &mt8173_conf, }, { .compatible = "mediatek,mt8183-dpi", .data = &mt8183_conf, }, { .compatible = "mediatek,mt8192-dpi", .data = &mt8192_conf, }, { }, };
return;- }
- switch (format) {
- case MTK_DPI_COLOR_FORMAT_YCBCR_422:
- case MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL:
- case MTK_DPI_COLOR_FORMAT_YCBCR_444:
- case MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL:
- case MTK_DPI_COLOR_FORMAT_XV_YCC:
if (dpi->mode.hdisplay <= 720)matrix_sel = 0x2;Symbolize 0x2.
break;- default:
If format is MTK_DPI_COLOR_FORMAT_YCBCR_422 first, then format change to MTK_DPI_COLOR_FORMAT_RGB and matrix_sel would still be 0x2. Is this correct?
Regards, CK
break;- }
- mtk_dpi_mask(dpi, DPI_MATRIX_SET, matrix_sel,
INT_MATRIX_SEL_MASK); +}
static void mtk_dpi_config_color_format(struct mtk_dpi *dpi, enum mtk_dpi_out_color_format format) { @@ -405,6 +431,7 @@ static void mtk_dpi_config_color_format(struct mtk_dpi *dpi, (format == MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL)) { mtk_dpi_config_yuv422_enable(dpi, false); mtk_dpi_config_csc_enable(dpi, true);
mtk_dpi_matrix_sel(dpi, format);MTK_DPI_OUT_CHANNEL_SWAP_BGR); @@ -412,6 +439,7 @@ static void mtk_dpi_config_color_format(struct mtk_dpi *dpi, (format == MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL)) { mtk_dpi_config_yuv422_enable(dpi, true); mtk_dpi_config_csc_enable(dpi, true);
mtk_dpi_matrix_sel(dpi, format);@@ -951,6 +979,7 @@ static const struct mtk_dpi_conf mt8195_dpintf_conf = { .channel_swap_shift = DPINTF_CH_SWAP, .yuv422_en_bit = DPINTF_YUV422_EN, .csc_enable_bit = DPINTF_CSC_ENABLE,
- .matrx_sel_support = true,
};
static int mtk_dpi_probe(struct platform_device *pdev) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h index f7f0272dbd6a..96c117202d0d 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h @@ -230,4 +230,7 @@ #define EDGE_SEL_EN BIT(5) #define H_FRE_2N BIT(25)
+#define DPI_MATRIX_SET 0xB4 +#define INT_MATRIX_SEL_MASK (0x1F << 0)
#endif /* __MTK_DPI_REGS_H */
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