Converts various instances of the printk based drm logging macros to the struct drm_device based logging macros in i915/display/intel_dp.c. This also involves extracting the struct drm_i915_private device pointer from various intel types to be used in the macros.

Signed-off-by: Wambui Karuga wambui.karugax@gmail.com --- drivers/gpu/drm/i915/display/intel_dp.c | 320 +++++++++++++++--------- 1 file changed, 198 insertions(+), 122 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index f4dede6253f8..fab6e0af5d9d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -461,7 +461,8 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, !intel_dp_can_link_train_fallback_for_edp(intel_dp, intel_dp->common_rates[index - 1], lane_count)) { - DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n"); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "Retrying Link training for eDP with same parameters\n"); return 0; } intel_dp->max_link_rate = intel_dp->common_rates[index - 1]; @@ -471,13 +472,15 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, !intel_dp_can_link_train_fallback_for_edp(intel_dp, intel_dp_max_common_rate(intel_dp), lane_count >> 1)) { - DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n"); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "Retrying Link training for eDP with same parameters\n"); return 0; } intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); intel_dp->max_link_lane_count = lane_count >> 1; } else { - DRM_ERROR("Link Training Unsuccessful\n"); + drm_err(&dp_to_i915(intel_dp)->drm, + "Link Training Unsuccessful\n"); return -1; }

@@ -564,8 +567,9 @@ static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,

max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd); if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) { - DRM_DEBUG_KMS("Unsupported slice width %d by DP DSC Sink device\n", - max_slice_width); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "Unsupported slice width %d by DP DSC Sink device\n", + max_slice_width); return 0; } /* Also take into account max slice width */ @@ -583,7 +587,8 @@ static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, return valid_dsc_slicecount[i]; }

- DRM_DEBUG_KMS("Unsupported Slice Count %d\n", min_slice_count); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "Unsupported Slice Count %d\n", min_slice_count); return 0; }

@@ -1827,15 +1832,15 @@ static void intel_dp_print_rates(struct intel_dp *intel_dp)

snprintf_int_array(str, sizeof(str), intel_dp->source_rates, intel_dp->num_source_rates); - DRM_DEBUG_KMS("source rates: %s\n", str); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, "source rates: %s\n", str);

snprintf_int_array(str, sizeof(str), intel_dp->sink_rates, intel_dp->num_sink_rates); - DRM_DEBUG_KMS("sink rates: %s\n", str); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, "sink rates: %s\n", str);

snprintf_int_array(str, sizeof(str), intel_dp->common_rates, intel_dp->num_common_rates); - DRM_DEBUG_KMS("common rates: %s\n", str); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, "common rates: %s\n", str); }

int @@ -1949,7 +1954,8 @@ intel_dp_adjust_compliance_config(struct intel_dp *intel_dp, limits->min_bpp = limits->max_bpp = bpp; pipe_config->dither_force_disable = bpp == 6 * 3;

- DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "Setting pipe_bpp to %d\n", bpp); }

/* Use values requested by Compliance Test Request */ @@ -2077,7 +2083,8 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,

line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd); if (!line_buf_depth) { - DRM_DEBUG_KMS("DSC Sink Line Buffer Depth invalid\n"); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "DSC Sink Line Buffer Depth invalid\n"); return -EINVAL; }

@@ -2219,6 +2226,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, { struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + struct drm_i915_private *i915 = dp_to_i915(intel_dp); struct link_config_limits limits; int common_len; int ret; @@ -2252,11 +2260,11 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,

intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);

- DRM_DEBUG_KMS("DP link computation with max lane count %i " - "max rate %d max bpp %d pixel clock %iKHz\n", - limits.max_lane_count, - intel_dp->common_rates[limits.max_clock], - limits.max_bpp, adjusted_mode->crtc_clock); + drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i " + "max rate %d max bpp %d pixel clock %iKHz\n", + limits.max_lane_count, + intel_dp->common_rates[limits.max_clock], + limits.max_bpp, adjusted_mode->crtc_clock);

/* * Optimize for slow and wide. This is the place to add alternative @@ -2265,7 +2273,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);

/* enable compression if the mode doesn't fit available BW */ - DRM_DEBUG_KMS("Force DSC en = %d\n", intel_dp->force_dsc_en); + drm_dbg_kms(&i915->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en); if (ret || intel_dp->force_dsc_en) { ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, conn_state, &limits); @@ -2274,26 +2282,29 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, }

if (pipe_config->dsc.compression_enable) { - DRM_DEBUG_KMS("DP lane count %d clock %d Input bpp %d Compressed bpp %d\n", - pipe_config->lane_count, pipe_config->port_clock, - pipe_config->pipe_bpp, - pipe_config->dsc.compressed_bpp); - - DRM_DEBUG_KMS("DP link rate required %i available %i\n", - intel_dp_link_required(adjusted_mode->crtc_clock, - pipe_config->dsc.compressed_bpp), - intel_dp_max_data_rate(pipe_config->port_clock, - pipe_config->lane_count)); + drm_dbg_kms(&i915->drm, + "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n", + pipe_config->lane_count, pipe_config->port_clock, + pipe_config->pipe_bpp, + pipe_config->dsc.compressed_bpp); + + drm_dbg_kms(&i915->drm, + "DP link rate required %i available %i\n", + intel_dp_link_required(adjusted_mode->crtc_clock, + pipe_config->dsc.compressed_bpp), + intel_dp_max_data_rate(pipe_config->port_clock, + pipe_config->lane_count)); } else { - DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n", - pipe_config->lane_count, pipe_config->port_clock, - pipe_config->pipe_bpp); + drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n", + pipe_config->lane_count, pipe_config->port_clock, + pipe_config->pipe_bpp);

- DRM_DEBUG_KMS("DP link rate required %i available %i\n", - intel_dp_link_required(adjusted_mode->crtc_clock, - pipe_config->pipe_bpp), - intel_dp_max_data_rate(pipe_config->port_clock, - pipe_config->lane_count)); + drm_dbg_kms(&i915->drm, + "DP link rate required %i available %i\n", + intel_dp_link_required(adjusted_mode->crtc_clock, + pipe_config->pipe_bpp), + intel_dp_max_data_rate(pipe_config->port_clock, + pipe_config->lane_count)); } return 0; } @@ -2319,7 +2330,8 @@ intel_dp_ycbcr420_config(struct intel_dp *intel_dp, /* YCBCR 420 output conversion needs a scaler */ ret = skl_update_scaler_crtc(crtc_state); if (ret) { - DRM_DEBUG_KMS("Scaler allocation for output failed\n"); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "Scaler allocation for output failed\n"); return ret; }

@@ -2621,13 +2633,14 @@ static void wait_panel_status(struct intel_dp *intel_dp,

static void wait_panel_on(struct intel_dp *intel_dp) { - DRM_DEBUG_KMS("Wait for panel power on\n"); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, "Wait for panel power on\n"); wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); }

static void wait_panel_off(struct intel_dp *intel_dp) { - DRM_DEBUG_KMS("Wait for panel power off time\n"); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "Wait for panel power off time\n"); wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); }

@@ -2636,7 +2649,8 @@ static void wait_panel_power_cycle(struct intel_dp *intel_dp) ktime_t panel_power_on_time; s64 panel_power_off_duration;

- DRM_DEBUG_KMS("Wait for panel power cycle\n"); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "Wait for panel power cycle\n");

/* take the difference of currrent time and panel power off time * and then make panel wait for t11_t12 if needed. */ @@ -3003,7 +3017,7 @@ void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state, if (!intel_dp_is_edp(intel_dp)) return;

- DRM_DEBUG_KMS("\n"); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, "\n");

intel_panel_enable_backlight(crtc_state, conn_state); _intel_edp_backlight_on(intel_dp); @@ -3041,7 +3055,7 @@ void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state) if (!intel_dp_is_edp(intel_dp)) return;

- DRM_DEBUG_KMS("\n"); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, "\n");

_intel_edp_backlight_off(intel_dp); intel_panel_disable_backlight(old_conn_state); @@ -3064,8 +3078,9 @@ static void intel_edp_backlight_power(struct intel_connector *connector, if (is_enabled == enable) return;

- DRM_DEBUG_KMS("panel power control backlight %s\n", - enable ? "enable" : "disable"); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "panel power control backlight %s\n", + enable ? "enable" : "disable");

if (enable) _intel_edp_backlight_on(intel_dp); @@ -3183,8 +3198,9 @@ void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp, ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE, enable ? DP_DECOMPRESSION_EN : 0); if (ret < 0) - DRM_DEBUG_KMS("Failed to %s sink decompression state\n", - enable ? "enable" : "disable"); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "Failed to %s sink decompression state\n", + enable ? "enable" : "disable"); }

/* If the sink supports it, try to set the power state appropriately */ @@ -3222,8 +3238,9 @@ void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) }

if (ret != 1) - DRM_DEBUG_KMS("failed to %s sink power state\n", - mode == DRM_MODE_DPMS_ON ? "enable" : "disable"); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "failed to %s sink power state\n", + mode == DRM_MODE_DPMS_ON ? "enable" : "disable"); }

static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv, @@ -4319,20 +4336,22 @@ intel_dp_extended_receiver_capabilities(struct intel_dp *intel_dp)

if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV, &dpcd_ext, sizeof(dpcd_ext)) != sizeof(dpcd_ext)) { - DRM_ERROR("DPCD failed read at extended capabilities\n"); + drm_err(&dp_to_i915(intel_dp)->drm, + "DPCD failed read at extended capabilities\n"); return; }

if (intel_dp->dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) { - DRM_DEBUG_KMS("DPCD extended DPCD rev less than base DPCD rev\n"); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "DPCD extended DPCD rev less than base DPCD rev\n"); return; }

if (!memcmp(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext))) return;

- DRM_DEBUG_KMS("Base DPCD: %*ph\n", - (int)sizeof(intel_dp->dpcd), intel_dp->dpcd); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, "Base DPCD: %*ph\n", + (int)sizeof(intel_dp->dpcd), intel_dp->dpcd);

memcpy(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext)); } @@ -4346,7 +4365,8 @@ intel_dp_read_dpcd(struct intel_dp *intel_dp)

intel_dp_extended_receiver_capabilities(intel_dp);

- DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, "DPCD: %*ph\n", + (int)sizeof(intel_dp->dpcd), intel_dp->dpcd);

return intel_dp->dpcd[DP_DPCD_REV] != 0; } @@ -4378,20 +4398,23 @@ static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp) if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT, intel_dp->dsc_dpcd, sizeof(intel_dp->dsc_dpcd)) < 0) - DRM_ERROR("Failed to read DPCD register 0x%x\n", - DP_DSC_SUPPORT); + drm_err(&dp_to_i915(intel_dp)->drm, + "Failed to read DPCD register 0x%x\n", + DP_DSC_SUPPORT);

- DRM_DEBUG_KMS("DSC DPCD: %*ph\n", - (int)sizeof(intel_dp->dsc_dpcd), - intel_dp->dsc_dpcd); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, "DSC DPCD: %*ph\n", + (int)sizeof(intel_dp->dsc_dpcd), + intel_dp->dsc_dpcd);

/* FEC is supported only on DP 1.4 */ if (!intel_dp_is_edp(intel_dp) && drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY, &intel_dp->fec_capable) < 0) - DRM_ERROR("Failed to read FEC DPCD register\n"); + drm_err(&dp_to_i915(intel_dp)->drm, + "Failed to read FEC DPCD register\n");

- DRM_DEBUG_KMS("FEC CAPABILITY: %x\n", intel_dp->fec_capable); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "FEC CAPABILITY: %x\n", intel_dp->fec_capable); } }

@@ -4568,10 +4591,11 @@ intel_dp_configure_mst(struct intel_dp *intel_dp) &dp_to_dig_port(intel_dp)->base; bool sink_can_mst = intel_dp_sink_can_mst(intel_dp);

- DRM_DEBUG_KMS("[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n", - encoder->base.base.id, encoder->base.name, - yesno(intel_dp->can_mst), yesno(sink_can_mst), - yesno(i915_modparams.enable_dp_mst)); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n", + encoder->base.base.id, encoder->base.name, + yesno(intel_dp->can_mst), yesno(sink_can_mst), + yesno(i915_modparams.enable_dp_mst));

if (!intel_dp->can_mst) return; @@ -4756,18 +4780,21 @@ intel_dp_setup_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,

ret = drm_hdmi_infoframe_set_hdr_metadata(&drm_infoframe, conn_state); if (ret) { - DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n"); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "couldn't set HDR metadata in infoframe\n"); return; }

len = hdmi_drm_infoframe_pack_only(&drm_infoframe, buf, sizeof(buf)); if (len < 0) { - DRM_DEBUG_KMS("buffer size is smaller than hdr metadata infoframe\n"); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "buffer size is smaller than hdr metadata infoframe\n"); return; }

if (len != infoframe_size) { - DRM_DEBUG_KMS("wrong static hdr metadata size\n"); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "wrong static hdr metadata size\n"); return; }

@@ -4856,7 +4883,8 @@ static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp) &test_lane_count);

if (status <= 0) { - DRM_DEBUG_KMS("Lane count read failed\n"); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "Lane count read failed\n"); return DP_TEST_NAK; } test_lane_count &= DP_MAX_LANE_COUNT_MASK; @@ -4864,7 +4892,8 @@ static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp) status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE, &test_link_bw); if (status <= 0) { - DRM_DEBUG_KMS("Link Rate read failed\n"); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "Link Rate read failed\n"); return DP_TEST_NAK; } test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw); @@ -4882,6 +4911,7 @@ static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)

static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) { + struct drm_i915_private *i915 = dp_to_i915(intel_dp); u8 test_pattern; u8 test_misc; __be16 h_width, v_height; @@ -4891,7 +4921,7 @@ static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN, &test_pattern); if (status <= 0) { - DRM_DEBUG_KMS("Test pattern read failed\n"); + drm_dbg_kms(&i915->drm, "Test pattern read failed\n"); return DP_TEST_NAK; } if (test_pattern != DP_COLOR_RAMP) @@ -4900,21 +4930,21 @@ static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI, &h_width, 2); if (status <= 0) { - DRM_DEBUG_KMS("H Width read failed\n"); + drm_dbg_kms(&i915->drm, "H Width read failed\n"); return DP_TEST_NAK; }

status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI, &v_height, 2); if (status <= 0) { - DRM_DEBUG_KMS("V Height read failed\n"); + drm_dbg_kms(&i915->drm, "V Height read failed\n"); return DP_TEST_NAK; }

status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0, &test_misc); if (status <= 0) { - DRM_DEBUG_KMS("TEST MISC read failed\n"); + drm_dbg_kms(&i915->drm, "TEST MISC read failed\n"); return DP_TEST_NAK; } if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB) @@ -4959,9 +4989,10 @@ static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp) */ if (intel_dp->aux.i2c_nack_count > 0 || intel_dp->aux.i2c_defer_count > 0) - DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n", - intel_dp->aux.i2c_nack_count, - intel_dp->aux.i2c_defer_count); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "EDID read had %d NACKs, %d DEFERs\n", + intel_dp->aux.i2c_nack_count, + intel_dp->aux.i2c_defer_count); intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE; } else { struct edid *block = intel_connector->detect_edid; @@ -4973,7 +5004,8 @@ static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)

if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM, block->checksum) <= 0) - DRM_DEBUG_KMS("Failed to write EDID checksum\n"); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "Failed to write EDID checksum\n");

test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED; @@ -4999,29 +5031,35 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp)

status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request); if (status <= 0) { - DRM_DEBUG_KMS("Could not read test request from sink\n"); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "Could not read test request from sink\n"); goto update_status; }

switch (request) { case DP_TEST_LINK_TRAINING: - DRM_DEBUG_KMS("LINK_TRAINING test requested\n"); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "LINK_TRAINING test requested\n"); response = intel_dp_autotest_link_training(intel_dp); break; case DP_TEST_LINK_VIDEO_PATTERN: - DRM_DEBUG_KMS("TEST_PATTERN test requested\n"); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "TEST_PATTERN test requested\n"); response = intel_dp_autotest_video_pattern(intel_dp); break; case DP_TEST_LINK_EDID_READ: - DRM_DEBUG_KMS("EDID test requested\n"); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "EDID test requested\n"); response = intel_dp_autotest_edid(intel_dp); break; case DP_TEST_LINK_PHY_TEST_PATTERN: - DRM_DEBUG_KMS("PHY_PATTERN test requested\n"); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "PHY_PATTERN test requested\n"); response = intel_dp_autotest_phy_pattern(intel_dp); break; default: - DRM_DEBUG_KMS("Invalid test request '%02x'\n", request); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "Invalid test request '%02x'\n", request); break; }

@@ -5031,7 +5069,8 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp) update_status: status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response); if (status <= 0) - DRM_DEBUG_KMS("Could not write test response to sink\n"); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "Could not write test response to sink\n"); }

static int @@ -5053,12 +5092,14 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp) /* check link status - esi[10] = 0x200c */ if (intel_dp->active_mst_links > 0 && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { - DRM_DEBUG_KMS("channel EQ not ok, retraining\n"); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "channel EQ not ok, retraining\n"); intel_dp_start_link_train(intel_dp); intel_dp_stop_link_train(intel_dp); }

- DRM_DEBUG_KMS("got esi %3ph\n", esi); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "got esi %3ph\n", esi); ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);

if (handled) { @@ -5074,7 +5115,8 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp)

bret = intel_dp_get_sink_irq_esi(intel_dp, esi); if (bret == true) { - DRM_DEBUG_KMS("got esi2 %3ph\n", esi); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "got esi2 %3ph\n", esi); goto go_again; } } else @@ -5082,7 +5124,8 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp)

return ret; } else { - DRM_DEBUG_KMS("failed to get ESI - device may have failed\n"); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "failed to get ESI - device may have failed\n"); intel_dp->is_mst = false; drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); @@ -5261,7 +5304,8 @@ static void intel_dp_check_service_irq(struct intel_dp *intel_dp) intel_hdcp_handle_cp_irq(intel_dp->attached_connector);

if (val & DP_SINK_SPECIFIC_IRQ) - DRM_DEBUG_DRIVER("Sink specific irq unhandled\n"); + drm_dbg(&dp_to_i915(intel_dp)->drm, + "Sink specific irq unhandled\n"); }

/* @@ -5375,7 +5419,8 @@ intel_dp_detect_dpcd(struct intel_dp *intel_dp) }

/* Anything else is out of spec, warn and ignore */ - DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "Broken DP branch device, ignoring\n"); return connector_status_disconnected; }

@@ -5853,8 +5898,9 @@ intel_dp_connector_register(struct drm_connector *connector)

i915_debugfs_connector_add(connector);

- DRM_DEBUG_KMS("registering %s bus for %s\n", - intel_dp->aux.name, connector->kdev->kobj.name); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "registering %s bus for %s\n", + intel_dp->aux.name, connector->kdev->kobj.name);

intel_dp->aux.dev = connector->kdev; ret = drm_dp_aux_register(&intel_dp->aux); @@ -5954,8 +6000,9 @@ int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port, dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN, an, DRM_HDCP_AN_LEN); if (dpcd_ret != DRM_HDCP_AN_LEN) { - DRM_DEBUG_KMS("Failed to write An over DP/AUX (%zd)\n", - dpcd_ret); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "Failed to write An over DP/AUX (%zd)\n", + dpcd_ret); return dpcd_ret >= 0 ? -EIO : dpcd_ret; }

@@ -5971,17 +6018,20 @@ int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port, rxbuf, sizeof(rxbuf), DP_AUX_CH_CTL_AUX_AKSV_SELECT); if (ret < 0) { - DRM_DEBUG_KMS("Write Aksv over DP/AUX failed (%d)\n", ret); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "Write Aksv over DP/AUX failed (%d)\n", ret); return ret; } else if (ret == 0) { - DRM_DEBUG_KMS("Aksv write over DP/AUX was empty\n"); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "Aksv write over DP/AUX was empty\n"); return -EIO; }

reply = (rxbuf[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK; if (reply != DP_AUX_NATIVE_REPLY_ACK) { - DRM_DEBUG_KMS("Aksv write: no DP_AUX_NATIVE_REPLY_ACK %x\n", - reply); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "Aksv write: no DP_AUX_NATIVE_REPLY_ACK %x\n", + reply); return -EIO; } return 0; @@ -5990,11 +6040,13 @@ int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port, static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port, u8 *bksv) { + struct intel_dp *intel_dp = &intel_dig_port->dp; ssize_t ret; ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv, DRM_HDCP_KSV_LEN); if (ret != DRM_HDCP_KSV_LEN) { - DRM_DEBUG_KMS("Read Bksv from DP/AUX failed (%zd)\n", ret); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "Read Bksv from DP/AUX failed (%zd)\n", ret); return ret >= 0 ? -EIO : ret; } return 0; @@ -6003,6 +6055,7 @@ static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port, static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port, u8 *bstatus) { + struct intel_dp *intel_dp = &intel_dig_port->dp; ssize_t ret; /* * For some reason the HDMI and DP HDCP specs call this register @@ -6012,7 +6065,8 @@ static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port, ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO, bstatus, DRM_HDCP_BSTATUS_LEN); if (ret != DRM_HDCP_BSTATUS_LEN) { - DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "Read bstatus from DP/AUX failed (%zd)\n", ret); return ret >= 0 ? -EIO : ret; } return 0; @@ -6022,12 +6076,14 @@ static int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port, u8 *bcaps) { + struct intel_dp *intel_dp = &intel_dig_port->dp; ssize_t ret;

ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS, bcaps, 1); if (ret != 1) { - DRM_DEBUG_KMS("Read bcaps from DP/AUX failed (%zd)\n", ret); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "Read bcaps from DP/AUX failed (%zd)\n", ret); return ret >= 0 ? -EIO : ret; }

@@ -6053,11 +6109,13 @@ static int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port, u8 *ri_prime) { + struct intel_dp *intel_dp = &intel_dig_port->dp; ssize_t ret; ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME, ri_prime, DRM_HDCP_RI_LEN); if (ret != DRM_HDCP_RI_LEN) { - DRM_DEBUG_KMS("Read Ri' from DP/AUX failed (%zd)\n", ret); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "Read Ri' from DP/AUX failed (%zd)\n", ret); return ret >= 0 ? -EIO : ret; } return 0; @@ -6067,12 +6125,14 @@ static int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port, bool *ksv_ready) { + struct intel_dp *intel_dp = &intel_dig_port->dp; ssize_t ret; u8 bstatus; ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS, &bstatus, 1); if (ret != 1) { - DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "Read bstatus from DP/AUX failed (%zd)\n", ret); return ret >= 0 ? -EIO : ret; } *ksv_ready = bstatus & DP_BSTATUS_READY; @@ -6083,19 +6143,21 @@ static int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port, int num_downstream, u8 *ksv_fifo) { + struct intel_dp *intel_dp = &intel_dig_port->dp; ssize_t ret; int i;

/* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */ for (i = 0; i < num_downstream; i += 3) { size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN; - ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, + ret = drm_dp_dpcd_read(&intel_dp->aux, DP_AUX_HDCP_KSV_FIFO, ksv_fifo + i * DRM_HDCP_KSV_LEN, len); if (ret != len) { - DRM_DEBUG_KMS("Read ksv[%d] from DP/AUX failed (%zd)\n", - i, ret); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "Read ksv[%d] from DP/AUX failed (%zd)\n", + i, ret); return ret >= 0 ? -EIO : ret; } } @@ -6106,6 +6168,7 @@ static int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port, int i, u32 *part) { + struct intel_dp *intel_dp = &intel_dig_port->dp; ssize_t ret;

if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) @@ -6115,7 +6178,8 @@ int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port, DP_AUX_HDCP_V_PRIME(i), part, DRM_HDCP_V_PRIME_PART_LEN); if (ret != DRM_HDCP_V_PRIME_PART_LEN) { - DRM_DEBUG_KMS("Read v'[%d] from DP/AUX failed (%zd)\n", i, ret); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "Read v'[%d] from DP/AUX failed (%zd)\n", i, ret); return ret >= 0 ? -EIO : ret; } return 0; @@ -6132,13 +6196,15 @@ int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, static bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port) { + struct intel_dp *intel_dp = &intel_dig_port->dp; ssize_t ret; u8 bstatus;

ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS, &bstatus, 1); if (ret != 1) { - DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "Read bstatus from DP/AUX failed (%zd)\n", ret); return false; }

@@ -6213,13 +6279,15 @@ static inline int intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port, u8 *rx_status) { + struct intel_dp *intel_dp = &intel_dig_port->dp; ssize_t ret;

ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status, HDCP_2_2_DP_RXSTATUS_LEN); if (ret != HDCP_2_2_DP_RXSTATUS_LEN) { - DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "Read bstatus from DP/AUX failed (%zd)\n", ret); return ret >= 0 ? -EIO : ret; }

@@ -6230,6 +6298,7 @@ static int hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port, u8 msg_id, bool *msg_ready) { + struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); u8 rx_status; int ret;

@@ -6252,7 +6321,7 @@ int hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port, *msg_ready = true; break; default: - DRM_ERROR("Unidentified msg_id: %d\n", msg_id); + drm_err(&i915->drm, "Unidentified msg_id: %d\n", msg_id); return -EINVAL; }

@@ -6294,8 +6363,9 @@ intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port, }

if (ret) - DRM_DEBUG_KMS("msg_id %d, ret %d, timeout(mSec): %d\n", - hdcp2_msg_data->msg_id, ret, timeout); + drm_dbg_kms(&dp_to_i915(dp)->drm, + "msg_id %d, ret %d, timeout(mSec): %d\n", + hdcp2_msg_data->msg_id, ret, timeout);

return ret; } @@ -6381,6 +6451,7 @@ static int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port, u8 msg_id, void *buf, size_t size) { + struct intel_dp *dp = &intel_dig_port->dp; unsigned int offset; u8 *byte = buf; ssize_t ret, bytes_to_recv, len; @@ -6414,7 +6485,8 @@ int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port, ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, offset, (void *)byte, len); if (ret < 0) { - DRM_DEBUG_KMS("msg_id %d, ret %zd\n", msg_id, ret); + drm_dbg_kms(&dp_to_i915(dp)->drm, + "msg_id %d, ret %zd\n", msg_id, ret); return ret; }

@@ -6618,16 +6690,18 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) * would end up in an endless cycle of * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..." */ - DRM_DEBUG_KMS("ignoring long hpd on eDP [ENCODER:%d:%s]\n", - intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "ignoring long hpd on eDP [ENCODER:%d:%s]\n", + intel_dig_port->base.base.base.id, + intel_dig_port->base.base.name); return IRQ_HANDLED; }

- DRM_DEBUG_KMS("got hpd irq on [ENCODER:%d:%s] - %s\n", - intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name, - long_hpd ? "long" : "short"); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "got hpd irq on [ENCODER:%d:%s] - %s\n", + intel_dig_port->base.base.base.id, + intel_dig_port->base.base.name, + long_hpd ? "long" : "short");

if (long_hpd) { intel_dp->reset_link_params = true; @@ -6640,8 +6714,10 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) * If we were in MST mode, and device is not * there, get out of MST mode */ - DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", - intel_dp->is_mst, intel_dp->mst_mgr.mst_state); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "MST device may have disappeared %d vs %d\n", + intel_dp->is_mst, + intel_dp->mst_mgr.mst_state); intel_dp->is_mst = false; drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); @@ -6774,7 +6850,7 @@ intel_pps_verify_state(struct intel_dp *intel_dp)

if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 || hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) { - DRM_ERROR("PPS state mismatch\n"); + drm_err(&dp_to_i915(intel_dp)->drm, "PPS state mismatch\n"); intel_pps_dump_state("sw", sw); intel_pps_dump_state("hw", &hw); }

Converts various instances of the printk based drm logging macros to the struct drm_device based logging macros in i915/display/intel_dp_link_training.c. This also involves extracting the drm_i915_private device pointer from the intel_dp type to use in the various macros.

Signed-off-by: Wambui Karuga wambui.karugax@gmail.com --- .../drm/i915/display/intel_dp_link_training.c | 75 ++++++++++++------- 1 file changed, 46 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 2a1130dd1ad0..a7defb37ab00 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -130,6 +130,7 @@ static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp) static bool intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp) { + struct drm_i915_private *i915 = dp_to_i915(intel_dp); u8 voltage; int voltage_tries, cr_tries, max_cr_tries; bool max_vswing_reached = false; @@ -143,9 +144,11 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp) &link_bw, &rate_select);

if (link_bw) - DRM_DEBUG_KMS("Using LINK_BW_SET value %02x\n", link_bw); + drm_dbg_kms(&i915->drm, + "Using LINK_BW_SET value %02x\n", link_bw); else - DRM_DEBUG_KMS("Using LINK_RATE_SET value %02x\n", rate_select); + drm_dbg_kms(&i915->drm, + "Using LINK_RATE_SET value %02x\n", rate_select);

/* Write the link configuration data */ link_config[0] = link_bw; @@ -169,7 +172,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp) if (!intel_dp_reset_link_train(intel_dp, DP_TRAINING_PATTERN_1 | DP_LINK_SCRAMBLING_DISABLE)) { - DRM_ERROR("failed to enable link training\n"); + drm_err(&i915->drm, "failed to enable link training\n"); return false; }

@@ -193,22 +196,23 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp) drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);

if (!intel_dp_get_link_status(intel_dp, link_status)) { - DRM_ERROR("failed to get link status\n"); + drm_err(&i915->drm, "failed to get link status\n"); return false; }

if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { - DRM_DEBUG_KMS("clock recovery OK\n"); + drm_dbg_kms(&i915->drm, "clock recovery OK\n"); return true; }

if (voltage_tries == 5) { - DRM_DEBUG_KMS("Same voltage tried 5 times\n"); + drm_dbg_kms(&i915->drm, + "Same voltage tried 5 times\n"); return false; }

if (max_vswing_reached) { - DRM_DEBUG_KMS("Max Voltage Swing reached\n"); + drm_dbg_kms(&i915->drm, "Max Voltage Swing reached\n"); return false; }

@@ -217,7 +221,8 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp) /* Update training set as requested by target */ intel_get_adjust_train(intel_dp, link_status); if (!intel_dp_update_link_train(intel_dp)) { - DRM_ERROR("failed to update link training\n"); + drm_err(&i915->drm, + "failed to update link training\n"); return false; }

@@ -231,7 +236,8 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp) max_vswing_reached = true;

} - DRM_ERROR("Failed clock recovery %d times, giving up!\n", max_cr_tries); + drm_err(&i915->drm, + "Failed clock recovery %d times, giving up!\n", max_cr_tries); return false; }

@@ -256,9 +262,11 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp) return DP_TRAINING_PATTERN_4; } else if (intel_dp->link_rate == 810000) { if (!source_tps4) - DRM_DEBUG_KMS("8.1 Gbps link rate without source HBR3/TPS4 support\n"); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "8.1 Gbps link rate without source HBR3/TPS4 support\n"); if (!sink_tps4) - DRM_DEBUG_KMS("8.1 Gbps link rate without sink TPS4 support\n"); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "8.1 Gbps link rate without sink TPS4 support\n"); } /* * Intel platforms that support HBR2 also support TPS3. TPS3 support is @@ -271,9 +279,11 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp) return DP_TRAINING_PATTERN_3; } else if (intel_dp->link_rate >= 540000) { if (!source_tps3) - DRM_DEBUG_KMS(">=5.4/6.48 Gbps link rate without source HBR2/TPS3 support\n"); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + ">=5.4/6.48 Gbps link rate without source HBR2/TPS3 support\n"); if (!sink_tps3) - DRM_DEBUG_KMS(">=5.4/6.48 Gbps link rate without sink TPS3 support\n"); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + ">=5.4/6.48 Gbps link rate without sink TPS3 support\n"); }

return DP_TRAINING_PATTERN_2; @@ -282,6 +292,7 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp) static bool intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp) { + struct drm_i915_private *i915 = dp_to_i915(intel_dp); int tries; u32 training_pattern; u8 link_status[DP_LINK_STATUS_SIZE]; @@ -295,7 +306,7 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp) /* channel equalization */ if (!intel_dp_set_link_train(intel_dp, training_pattern)) { - DRM_ERROR("failed to start channel equalization\n"); + drm_err(&i915->drm, "failed to start channel equalization\n"); return false; }

@@ -303,7 +314,8 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)

drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); if (!intel_dp_get_link_status(intel_dp, link_status)) { - DRM_ERROR("failed to get link status\n"); + drm_err(&i915->drm, + "failed to get link status\n"); break; }

@@ -311,23 +323,25 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp) if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { intel_dp_dump_link_status(link_status); - DRM_DEBUG_KMS("Clock recovery check failed, cannot " - "continue channel equalization\n"); + drm_dbg_kms(&i915->drm, + "Clock recovery check failed, cannot " + "continue channel equalization\n"); break; }

if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { channel_eq = true; - DRM_DEBUG_KMS("Channel EQ done. DP Training " - "successful\n"); + drm_dbg_kms(&i915->drm, "Channel EQ done. DP Training " + "successful\n"); break; }

/* Update training set as requested by target */ intel_get_adjust_train(intel_dp, link_status); if (!intel_dp_update_link_train(intel_dp)) { - DRM_ERROR("failed to update link training\n"); + drm_err(&i915->drm, + "failed to update link training\n"); break; } } @@ -335,7 +349,8 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp) /* Try 5 times, else fail and try at lower BW */ if (tries == 5) { intel_dp_dump_link_status(link_status); - DRM_DEBUG_KMS("Channel equalization failed 5 times\n"); + drm_dbg_kms(&i915->drm, + "Channel equalization failed 5 times\n"); }

intel_dp_set_idle_link_train(intel_dp); @@ -362,17 +377,19 @@ intel_dp_start_link_train(struct intel_dp *intel_dp) if (!intel_dp_link_training_channel_equalization(intel_dp)) goto failure_handling;

- DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Link Training Passed at Link Rate = %d, Lane count = %d", - intel_connector->base.base.id, - intel_connector->base.name, - intel_dp->link_rate, intel_dp->lane_count); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "[CONNECTOR:%d:%s] Link Training Passed at Link Rate = %d, Lane count = %d", + intel_connector->base.base.id, + intel_connector->base.name, + intel_dp->link_rate, intel_dp->lane_count); return;

failure_handling: - DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Link Training failed at link rate = %d, lane count = %d", - intel_connector->base.base.id, - intel_connector->base.name, - intel_dp->link_rate, intel_dp->lane_count); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "[CONNECTOR:%d:%s] Link Training failed at link rate = %d, lane count = %d", + intel_connector->base.base.id, + intel_connector->base.name, + intel_dp->link_rate, intel_dp->lane_count); if (!intel_dp_get_link_train_fallback_values(intel_dp, intel_dp->link_rate, intel_dp->lane_count))

Initial conversion of the straightforward printk based logging macros to the struct drm_device based logging macros in i915/display/intel_color.c.

Signed-off-by: Wambui Karuga wambui.karugax@gmail.com --- drivers/gpu/drm/i915/display/intel_color.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 2087a1852486..d44bd8287801 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1192,7 +1192,8 @@ static int check_luts(const struct intel_crtc_state *crtc_state)

/* C8 relies on its palette being stored in the legacy LUT */ if (crtc_state->c8_planes) { - DRM_DEBUG_KMS("C8 pixelformat requires the legacy LUT\n"); + drm_dbg_kms(&dev_priv->drm, + "C8 pixelformat requires the legacy LUT\n"); return -EINVAL; }

Conversion of the printk based drm logging macros to the struct drm_device based logging macros in display/intel_dp_aux_backlight.c. This also involves extracting the drm_i915_private device pointer from various intel types to use in the macros.

Note that this converts DRM_DEBUG_DRIVER to drm_dbg().

References: https://lists.freedesktop.org/archives/dri-devel/2020-January/253381.html Signed-off-by: Wambui Karuga wambui.karugax@gmail.com --- .../drm/i915/display/intel_dp_aux_backlight.c | 72 ++++++++++++------- 1 file changed, 45 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c index e86feebef299..83d9c76e4da9 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c @@ -35,8 +35,9 @@ static void set_aux_backlight_enable(struct intel_dp *intel_dp, bool enable)

if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, &reg_val) < 0) { - DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n", - DP_EDP_DISPLAY_CONTROL_REGISTER); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "Failed to read DPCD register 0x%x\n", + DP_EDP_DISPLAY_CONTROL_REGISTER); return; } if (enable) @@ -46,8 +47,9 @@ static void set_aux_backlight_enable(struct intel_dp *intel_dp, bool enable)

if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, reg_val) != 1) { - DRM_DEBUG_KMS("Failed to %s aux backlight\n", - enable ? "enable" : "disable"); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "Failed to %s aux backlight\n", + enable ? "enable" : "disable"); } }

@@ -65,8 +67,9 @@ static u32 intel_dp_aux_get_backlight(struct intel_connector *connector) if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &mode_reg) != 1) { - DRM_DEBUG_KMS("Failed to read the DPCD register 0x%x\n", - DP_EDP_BACKLIGHT_MODE_SET_REGISTER); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "Failed to read the DPCD register 0x%x\n", + DP_EDP_BACKLIGHT_MODE_SET_REGISTER); return 0; }

@@ -80,8 +83,9 @@ static u32 intel_dp_aux_get_backlight(struct intel_connector *connector)

if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, &read_val, sizeof(read_val)) < 0) { - DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n", - DP_EDP_BACKLIGHT_BRIGHTNESS_MSB); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "Failed to read DPCD register 0x%x\n", + DP_EDP_BACKLIGHT_BRIGHTNESS_MSB); return 0; } level = read_val[0]; @@ -111,7 +115,8 @@ intel_dp_aux_set_backlight(const struct drm_connector_state *conn_state, u32 lev } if (drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, vals, sizeof(vals)) < 0) { - DRM_DEBUG_KMS("Failed to write aux backlight level\n"); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "Failed to write aux backlight level\n"); return; } } @@ -133,7 +138,8 @@ static bool intel_dp_aux_set_pwm_freq(struct intel_connector *connector)

freq = dev_priv->vbt.backlight.pwm_freq_hz; if (!freq) { - DRM_DEBUG_KMS("Use panel default backlight frequency\n"); + drm_dbg_kms(&dev_priv->drm, + "Use panel default backlight frequency\n"); return false; }

@@ -146,13 +152,14 @@ static bool intel_dp_aux_set_pwm_freq(struct intel_connector *connector) fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);

if (fxp_min > fxp_actual || fxp_actual > fxp_max) { - DRM_DEBUG_KMS("Actual frequency out of range\n"); + drm_dbg_kms(&dev_priv->drm, "Actual frequency out of range\n"); return false; }

if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_FREQ_SET, (u8) f) < 0) { - DRM_DEBUG_KMS("Failed to write aux backlight freq\n"); + drm_dbg_kms(&dev_priv->drm, + "Failed to write aux backlight freq\n"); return false; } return true; @@ -162,14 +169,16 @@ static void intel_dp_aux_enable_backlight(const struct intel_crtc_state *crtc_st const struct drm_connector_state *conn_state) { struct intel_connector *connector = to_intel_connector(conn_state->connector); + struct drm_i915_private *i915 = to_i915(connector->base.dev); struct intel_dp *intel_dp = intel_attached_dp(connector); struct intel_panel *panel = &connector->panel; u8 dpcd_buf, new_dpcd_buf, edp_backlight_mode;

if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf) != 1) { - DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n", - DP_EDP_BACKLIGHT_MODE_SET_REGISTER); + drm_dbg_kms(&i915->drm, + "Failed to read DPCD register 0x%x\n", + DP_EDP_BACKLIGHT_MODE_SET_REGISTER); return; }

@@ -186,7 +195,8 @@ static void intel_dp_aux_enable_backlight(const struct intel_crtc_state *crtc_st if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, panel->backlight.pwmgen_bit_count) < 0) - DRM_DEBUG_KMS("Failed to write aux pwmgen bit count\n"); + drm_dbg_kms(&i915->drm, + "Failed to write aux pwmgen bit count\n");

break;

@@ -203,7 +213,8 @@ static void intel_dp_aux_enable_backlight(const struct intel_crtc_state *crtc_st if (new_dpcd_buf != dpcd_buf) { if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, new_dpcd_buf) < 0) { - DRM_DEBUG_KMS("Failed to write aux backlight mode\n"); + drm_dbg_kms(&i915->drm, + "Failed to write aux backlight mode\n"); } }

@@ -237,9 +248,11 @@ static u32 intel_dp_aux_calc_max_backlight(struct intel_connector *connector) * minimum value will applied automatically. So no need to check that. */ freq = i915->vbt.backlight.pwm_freq_hz; - DRM_DEBUG_KMS("VBT defined backlight frequency %u Hz\n", freq); + drm_dbg_kms(&i915->drm, "VBT defined backlight frequency %u Hz\n", + freq); if (!freq) { - DRM_DEBUG_KMS("Use panel default backlight frequency\n"); + drm_dbg_kms(&i915->drm, + "Use panel default backlight frequency\n"); return max_backlight; }

@@ -254,12 +267,14 @@ static u32 intel_dp_aux_calc_max_backlight(struct intel_connector *connector) */ if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min) != 1) { - DRM_DEBUG_KMS("Failed to read pwmgen bit count cap min\n"); + drm_dbg_kms(&i915->drm, + "Failed to read pwmgen bit count cap min\n"); return max_backlight; } if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max) != 1) { - DRM_DEBUG_KMS("Failed to read pwmgen bit count cap max\n"); + drm_dbg_kms(&i915->drm, + "Failed to read pwmgen bit count cap max\n"); return max_backlight; } pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK; @@ -268,7 +283,8 @@ static u32 intel_dp_aux_calc_max_backlight(struct intel_connector *connector) fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4); fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4); if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) { - DRM_DEBUG_KMS("VBT defined backlight frequency out of range\n"); + drm_dbg_kms(&i915->drm, + "VBT defined backlight frequency out of range\n"); return max_backlight; }

@@ -279,10 +295,11 @@ static u32 intel_dp_aux_calc_max_backlight(struct intel_connector *connector) break; }

- DRM_DEBUG_KMS("Using eDP pwmgen bit count of %d\n", pn); + drm_dbg_kms(&i915->drm, "Using eDP pwmgen bit count of %d\n", pn); if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, pn) < 0) { - DRM_DEBUG_KMS("Failed to write aux pwmgen bit count\n"); + drm_dbg_kms(&i915->drm, + "Failed to write aux pwmgen bit count\n"); return max_backlight; } panel->backlight.pwmgen_bit_count = pn; @@ -319,7 +336,8 @@ intel_dp_aux_display_control_capable(struct intel_connector *connector) if (intel_dp->edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP && (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP) && !(intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP)) { - DRM_DEBUG_KMS("AUX Backlight Control Supported!\n"); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "AUX Backlight Control Supported!\n"); return true; } return false; @@ -328,8 +346,8 @@ intel_dp_aux_display_control_capable(struct intel_connector *connector) int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector) { struct intel_panel *panel = &intel_connector->panel; - enum intel_backlight_type type = - to_i915(intel_connector->base.dev)->vbt.backlight.type; + struct drm_i915_private *i915 = to_i915(intel_connector->base.dev); + enum intel_backlight_type type = i915->vbt.backlight.type;

if (i915_modparams.enable_dpcd_backlight == 0 || (i915_modparams.enable_dpcd_backlight == -1 && @@ -337,7 +355,7 @@ int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector) return -ENODEV;

if (type != INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE) - DRM_DEBUG_DRIVER("Ignoring VBT backlight type\n"); + drm_dbg(&i915->drm, "Ignoring VBT backlight type\n");

panel->backlight.setup = intel_dp_aux_setup_backlight; panel->backlight.enable = intel_dp_aux_enable_backlight;

Conversion of instances of printk based drm logging macros to the struct drm_device based logging macros in i915/display/intel_dpll_mgr.c. This also involves extracting the struct drm_i915_private device pointer from various intel types to use in the drm_device based macros.

Note that this converts DRM_DEBUG_DRIVER to drm_dbg().

References: https://lists.freedesktop.org/archives/dri-devel/2020-January/253381.html Signed-off-by: Wambui Karuga wambui.karugax@gmail.com --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 254 ++++++++++-------- 1 file changed, 142 insertions(+), 112 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index 2e596e88cf09..e5bfe5245276 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -147,7 +147,7 @@ void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state) mutex_lock(&dev_priv->dpll_lock); drm_WARN_ON(&dev_priv->drm, !pll->state.crtc_mask); if (!pll->active_mask) { - DRM_DEBUG_DRIVER("setting up %s\n", pll->info->name); + drm_dbg(&dev_priv->drm, "setting up %s\n", pll->info->name); drm_WARN_ON(&dev_priv->drm, pll->on); assert_shared_dpll_disabled(dev_priv, pll);

@@ -182,9 +182,10 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)

pll->active_mask |= crtc_mask;

- DRM_DEBUG_KMS("enable %s (active %x, on? %d) for crtc %d\n", - pll->info->name, pll->active_mask, pll->on, - crtc->base.base.id); + drm_dbg_kms(&dev_priv->drm, + "enable %s (active %x, on? %d) for crtc %d\n", + pll->info->name, pll->active_mask, pll->on, + crtc->base.base.id);

if (old_mask) { drm_WARN_ON(&dev_priv->drm, !pll->on); @@ -193,7 +194,7 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state) } drm_WARN_ON(&dev_priv->drm, pll->on);

- DRM_DEBUG_KMS("enabling %s\n", pll->info->name); + drm_dbg_kms(&dev_priv->drm, "enabling %s\n", pll->info->name); pll->info->funcs->enable(dev_priv, pll); pll->on = true;

@@ -225,9 +226,10 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state) if (drm_WARN_ON(&dev_priv->drm, !(pll->active_mask & crtc_mask))) goto out;

- DRM_DEBUG_KMS("disable %s (active %x, on? %d) for crtc %d\n", - pll->info->name, pll->active_mask, pll->on, - crtc->base.base.id); + drm_dbg_kms(&dev_priv->drm, + "disable %s (active %x, on? %d) for crtc %d\n", + pll->info->name, pll->active_mask, pll->on, + crtc->base.base.id);

assert_shared_dpll_enabled(dev_priv, pll); drm_WARN_ON(&dev_priv->drm, !pll->on); @@ -236,7 +238,7 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state) if (pll->active_mask) goto out;

- DRM_DEBUG_KMS("disabling %s\n", pll->info->name); + drm_dbg_kms(&dev_priv->drm, "disabling %s\n", pll->info->name); pll->info->funcs->disable(dev_priv, pll); pll->on = false;

@@ -272,20 +274,21 @@ intel_find_shared_dpll(struct intel_atomic_state *state, if (memcmp(pll_state, &shared_dpll[i].hw_state, sizeof(*pll_state)) == 0) { - DRM_DEBUG_KMS("[CRTC:%d:%s] sharing existing %s (crtc mask 0x%08x, active %x)\n", - crtc->base.base.id, crtc->base.name, - pll->info->name, - shared_dpll[i].crtc_mask, - pll->active_mask); + drm_dbg_kms(&dev_priv->drm, + "[CRTC:%d:%s] sharing existing %s (crtc mask 0x%08x, active %x)\n", + crtc->base.base.id, crtc->base.name, + pll->info->name, + shared_dpll[i].crtc_mask, + pll->active_mask); return pll; } }

/* Ok no matching timings, maybe there's a free one? */ if (unused_pll) { - DRM_DEBUG_KMS("[CRTC:%d:%s] allocated %s\n", - crtc->base.base.id, crtc->base.name, - unused_pll->info->name); + drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] allocated %s\n", + crtc->base.base.id, crtc->base.name, + unused_pll->info->name); return unused_pll; }

@@ -298,6 +301,7 @@ intel_reference_shared_dpll(struct intel_atomic_state *state, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *pll_state) { + struct drm_i915_private *i915 = to_i915(state->base.dev); struct intel_shared_dpll_state *shared_dpll; const enum intel_dpll_id id = pll->info->id;

@@ -306,8 +310,8 @@ intel_reference_shared_dpll(struct intel_atomic_state *state, if (shared_dpll[id].crtc_mask == 0) shared_dpll[id].hw_state = *pll_state;

- DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->info->name, - pipe_name(crtc->pipe)); + drm_dbg(&i915->drm, "using %s for pipe %c\n", pll->info->name, + pipe_name(crtc->pipe));

shared_dpll[id].crtc_mask |= 1 << crtc->pipe; } @@ -460,9 +464,10 @@ static bool ibx_get_dpll(struct intel_atomic_state *state, i = (enum intel_dpll_id) crtc->pipe; pll = &dev_priv->shared_dplls[i];

- DRM_DEBUG_KMS("[CRTC:%d:%s] using pre-allocated %s\n", - crtc->base.base.id, crtc->base.name, - pll->info->name); + drm_dbg_kms(&dev_priv->drm, + "[CRTC:%d:%s] using pre-allocated %s\n", + crtc->base.base.id, crtc->base.name, + pll->info->name); } else { pll = intel_find_shared_dpll(state, crtc, &crtc_state->dpll_hw_state, @@ -485,12 +490,13 @@ static bool ibx_get_dpll(struct intel_atomic_state *state, static void ibx_dump_hw_state(struct drm_i915_private *dev_priv, const struct intel_dpll_hw_state *hw_state) { - DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " - "fp0: 0x%x, fp1: 0x%x\n", - hw_state->dpll, - hw_state->dpll_md, - hw_state->fp0, - hw_state->fp1); + drm_dbg_kms(&dev_priv->drm, + "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " + "fp0: 0x%x, fp1: 0x%x\n", + hw_state->dpll, + hw_state->dpll_md, + hw_state->fp0, + hw_state->fp1); }

static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = { @@ -859,7 +865,8 @@ hsw_ddi_dp_get_dpll(struct intel_crtc_state *crtc_state) pll_id = DPLL_ID_LCPLL_2700; break; default: - DRM_DEBUG_KMS("Invalid clock for DP: %d\n", clock); + drm_dbg_kms(&dev_priv->drm, "Invalid clock for DP: %d\n", + clock); return NULL; }

@@ -914,8 +921,8 @@ static bool hsw_get_dpll(struct intel_atomic_state *state, static void hsw_dump_hw_state(struct drm_i915_private *dev_priv, const struct intel_dpll_hw_state *hw_state) { - DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", - hw_state->wrpll, hw_state->spll); + drm_dbg_kms(&dev_priv->drm, "dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", + hw_state->wrpll, hw_state->spll); }

static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs = { @@ -1019,7 +1026,7 @@ static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv, intel_de_read(dev_priv, regs[id].ctl) | LCPLL_PLL_ENABLE);

if (intel_de_wait_for_set(dev_priv, DPLL_STATUS, DPLL_LOCK(id), 5)) - DRM_ERROR("DPLL %d not locked\n", id); + drm_err(&dev_priv->drm, "DPLL %d not locked\n", id); }

static void skl_ddi_dpll0_enable(struct drm_i915_private *dev_priv, @@ -1443,19 +1450,22 @@ static bool skl_get_dpll(struct intel_atomic_state *state, { struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); + struct drm_i915_private *i915 = to_i915(crtc->base.dev); struct intel_shared_dpll *pll; bool bret;

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { bret = skl_ddi_hdmi_pll_dividers(crtc_state); if (!bret) { - DRM_DEBUG_KMS("Could not get HDMI pll dividers.\n"); + drm_dbg_kms(&i915->drm, + "Could not get HDMI pll dividers.\n"); return false; } } else if (intel_crtc_has_dp_encoder(crtc_state)) { bret = skl_ddi_dp_set_dpll_hw_state(crtc_state); if (!bret) { - DRM_DEBUG_KMS("Could not set DP dpll HW state.\n"); + drm_dbg_kms(&i915->drm, + "Could not set DP dpll HW state.\n"); return false; } } else { @@ -1486,7 +1496,7 @@ static bool skl_get_dpll(struct intel_atomic_state *state, static void skl_dump_hw_state(struct drm_i915_private *dev_priv, const struct intel_dpll_hw_state *hw_state) { - DRM_DEBUG_KMS("dpll_hw_state: " + drm_dbg_kms(&dev_priv->drm, "dpll_hw_state: " "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", hw_state->ctrl1, hw_state->cfgcr1, @@ -1527,7 +1537,8 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,

if (wait_for_us((intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_POWER_STATE), 200)) - DRM_ERROR("Power state not set for PLL:%d\n", port); + drm_err(&dev_priv->drm, + "Power state not set for PLL:%d\n", port); }

/* Disable 10 bit clock */ @@ -1606,7 +1617,7 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,

if (wait_for_us((intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK), 200)) - DRM_ERROR("PLL %d not locked\n", port); + drm_err(&dev_priv->drm, "PLL %d not locked\n", port);

if (IS_GEMINILAKE(dev_priv)) { temp = intel_de_read(dev_priv, BXT_PORT_TX_DW5_LN0(phy, ch)); @@ -1643,7 +1654,8 @@ static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,

if (wait_for_us(!(intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_POWER_STATE), 200)) - DRM_ERROR("Power state not reset for PLL:%d\n", port); + drm_err(&dev_priv->drm, + "Power state not reset for PLL:%d\n", port); } }

@@ -1712,9 +1724,11 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, hw_state->pcsdw12 = intel_de_read(dev_priv, BXT_PORT_PCS_DW12_LN01(phy, ch)); if (intel_de_read(dev_priv, BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12) - DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n", - hw_state->pcsdw12, - intel_de_read(dev_priv, BXT_PORT_PCS_DW12_LN23(phy, ch))); + drm_dbg(&dev_priv->drm, + "lane stagger config different for lane 01 (%08x) and 23 (%08x)\n", + hw_state->pcsdw12, + intel_de_read(dev_priv, + BXT_PORT_PCS_DW12_LN23(phy, ch))); hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;

ret = true; @@ -1753,6 +1767,7 @@ static bool bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state, struct bxt_clk_div *clk_div) { + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct dpll best_clock;

@@ -1762,9 +1777,9 @@ bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state, * i9xx_crtc_compute_clock */ if (!bxt_find_best_dpll(crtc_state, &best_clock)) { - DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n", - crtc_state->port_clock, - pipe_name(crtc->pipe)); + drm_dbg(&i915->drm, "no PLL dividers found for clock %d pipe %c\n", + crtc_state->port_clock, + pipe_name(crtc->pipe)); return false; }

@@ -1801,6 +1816,7 @@ static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state, static bool bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state, const struct bxt_clk_div *clk_div) { + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); struct intel_dpll_hw_state *dpll_hw_state = &crtc_state->dpll_hw_state; int clock = crtc_state->port_clock; int vco = clk_div->vco; @@ -1826,7 +1842,7 @@ static bool bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state, gain_ctl = 1; targ_cnt = 9; } else { - DRM_ERROR("Invalid VCO\n"); + drm_err(&i915->drm, "Invalid VCO\n"); return false; }

@@ -1909,8 +1925,8 @@ static bool bxt_get_dpll(struct intel_atomic_state *state, id = (enum intel_dpll_id) encoder->port; pll = intel_get_shared_dpll_by_id(dev_priv, id);

- DRM_DEBUG_KMS("[CRTC:%d:%s] using pre-allocated %s\n", - crtc->base.base.id, crtc->base.name, pll->info->name); + drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] using pre-allocated %s\n", + crtc->base.base.id, crtc->base.name, pll->info->name);

intel_reference_shared_dpll(state, crtc, pll, &crtc_state->dpll_hw_state); @@ -1923,20 +1939,20 @@ static bool bxt_get_dpll(struct intel_atomic_state *state, static void bxt_dump_hw_state(struct drm_i915_private *dev_priv, const struct intel_dpll_hw_state *hw_state) { - DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," - "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " - "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", - hw_state->ebb0, - hw_state->ebb4, - hw_state->pll0, - hw_state->pll1, - hw_state->pll2, - hw_state->pll3, - hw_state->pll6, - hw_state->pll8, - hw_state->pll9, - hw_state->pll10, - hw_state->pcsdw12); + drm_dbg_kms(&dev_priv->drm, "dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," + "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " + "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", + hw_state->ebb0, + hw_state->ebb4, + hw_state->pll0, + hw_state->pll1, + hw_state->pll2, + hw_state->pll3, + hw_state->pll6, + hw_state->pll8, + hw_state->pll9, + hw_state->pll10, + hw_state->pcsdw12); }

static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = { @@ -2033,7 +2049,7 @@ static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv, /* 2. Wait for DPLL power state enabled in DPLL_ENABLE. */ if (intel_de_wait_for_set(dev_priv, CNL_DPLL_ENABLE(id), PLL_POWER_STATE, 5)) - DRM_ERROR("PLL %d Power not enabled\n", id); + drm_err(&dev_priv->drm, "PLL %d Power not enabled\n", id);

/* * 3. Configure DPLL_CFGCR0 to set SSC enable/disable, @@ -2070,7 +2086,7 @@ static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,

/* 7. Wait for PLL lock status in DPLL_ENABLE. */ if (intel_de_wait_for_set(dev_priv, CNL_DPLL_ENABLE(id), PLL_LOCK, 5)) - DRM_ERROR("PLL %d not locked\n", id); + drm_err(&dev_priv->drm, "PLL %d not locked\n", id);

/* * 8. If the frequency will result in a change to the voltage @@ -2114,7 +2130,7 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,

/* 4. Wait for PLL not locked status in DPLL_ENABLE. */ if (intel_de_wait_for_clear(dev_priv, CNL_DPLL_ENABLE(id), PLL_LOCK, 5)) - DRM_ERROR("PLL %d locked\n", id); + drm_err(&dev_priv->drm, "PLL %d locked\n", id);

/* * 5. If the frequency will result in a change to the voltage @@ -2133,7 +2149,7 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv, /* 7. Wait for DPLL power state disabled in DPLL_ENABLE. */ if (intel_de_wait_for_clear(dev_priv, CNL_DPLL_ENABLE(id), PLL_POWER_STATE, 5)) - DRM_ERROR("PLL %d Power not disabled\n", id); + drm_err(&dev_priv->drm, "PLL %d Power not disabled\n", id); }

static bool cnl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, @@ -2398,24 +2414,28 @@ static bool cnl_get_dpll(struct intel_atomic_state *state, { struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); struct intel_shared_dpll *pll; bool bret;

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { bret = cnl_ddi_hdmi_pll_dividers(crtc_state); if (!bret) { - DRM_DEBUG_KMS("Could not get HDMI pll dividers.\n"); + drm_dbg_kms(&i915->drm, + "Could not get HDMI pll dividers.\n"); return false; } } else if (intel_crtc_has_dp_encoder(crtc_state)) { bret = cnl_ddi_dp_set_dpll_hw_state(crtc_state); if (!bret) { - DRM_DEBUG_KMS("Could not set DP dpll HW state.\n"); + drm_dbg_kms(&i915->drm, + "Could not set DP dpll HW state.\n"); return false; } } else { - DRM_DEBUG_KMS("Skip DPLL setup for output_types 0x%x\n", - crtc_state->output_types); + drm_dbg_kms(&i915->drm, + "Skip DPLL setup for output_types 0x%x\n", + crtc_state->output_types); return false; }

@@ -2425,7 +2445,7 @@ static bool cnl_get_dpll(struct intel_atomic_state *state, BIT(DPLL_ID_SKL_DPLL1) | BIT(DPLL_ID_SKL_DPLL0)); if (!pll) { - DRM_DEBUG_KMS("No PLL selected\n"); + drm_dbg_kms(&i915->drm, "No PLL selected\n"); return false; }

@@ -2440,10 +2460,10 @@ static bool cnl_get_dpll(struct intel_atomic_state *state, static void cnl_dump_hw_state(struct drm_i915_private *dev_priv, const struct intel_dpll_hw_state *hw_state) { - DRM_DEBUG_KMS("dpll_hw_state: " - "cfgcr0: 0x%x, cfgcr1: 0x%x\n", - hw_state->cfgcr0, - hw_state->cfgcr1); + drm_dbg_kms(&dev_priv->drm, "dpll_hw_state: " + "cfgcr0: 0x%x, cfgcr1: 0x%x\n", + hw_state->cfgcr0, + hw_state->cfgcr1); }

static const struct intel_shared_dpll_funcs cnl_ddi_pll_funcs = { @@ -2764,7 +2784,8 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,

if (!icl_mg_pll_find_divisors(clock, is_dp, use_ssc, &dco_khz, pll_state, is_dkl)) { - DRM_DEBUG_KMS("Failed to find divisors for clock %d\n", clock); + drm_dbg_kms(&dev_priv->drm, + "Failed to find divisors for clock %d\n", clock); return false; }

@@ -2777,8 +2798,9 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state, }

if (m2div_int > 255) { - DRM_DEBUG_KMS("Failed to find mdiv for clock %d\n", - clock); + drm_dbg_kms(&dev_priv->drm, + "Failed to find mdiv for clock %d\n", + clock); return false; } } @@ -2999,7 +3021,8 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state, unsigned long dpll_mask;

if (!icl_calc_dpll_state(crtc_state, encoder, &port_dpll->hw_state)) { - DRM_DEBUG_KMS("Could not calculate combo PHY PLL state.\n"); + drm_dbg_kms(&dev_priv->drm, + "Could not calculate combo PHY PLL state.\n");

return false; } @@ -3016,8 +3039,9 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state, &port_dpll->hw_state, dpll_mask); if (!port_dpll->pll) { - DRM_DEBUG_KMS("No combo PHY PLL found for [ENCODER:%d:%s]\n", - encoder->base.base.id, encoder->base.name); + drm_dbg_kms(&dev_priv->drm, + "No combo PHY PLL found for [ENCODER:%d:%s]\n", + encoder->base.base.id, encoder->base.name); return false; }

@@ -3041,7 +3065,8 @@ static bool icl_get_tc_phy_dplls(struct intel_atomic_state *state,

port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; if (!icl_calc_dpll_state(crtc_state, encoder, &port_dpll->hw_state)) { - DRM_DEBUG_KMS("Could not calculate TBT PLL state.\n"); + drm_dbg_kms(&dev_priv->drm, + "Could not calculate TBT PLL state.\n"); return false; }

@@ -3049,7 +3074,7 @@ static bool icl_get_tc_phy_dplls(struct intel_atomic_state *state, &port_dpll->hw_state, BIT(DPLL_ID_ICL_TBTPLL)); if (!port_dpll->pll) { - DRM_DEBUG_KMS("No TBT-ALT PLL found\n"); + drm_dbg_kms(&dev_priv->drm, "No TBT-ALT PLL found\n"); return false; } intel_reference_shared_dpll(state, crtc, @@ -3058,7 +3083,8 @@ static bool icl_get_tc_phy_dplls(struct intel_atomic_state *state,

port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY]; if (!icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state)) { - DRM_DEBUG_KMS("Could not calculate MG PHY PLL state.\n"); + drm_dbg_kms(&dev_priv->drm, + "Could not calculate MG PHY PLL state.\n"); goto err_unreference_tbt_pll; }

@@ -3068,7 +3094,7 @@ static bool icl_get_tc_phy_dplls(struct intel_atomic_state *state, &port_dpll->hw_state, BIT(dpll_id)); if (!port_dpll->pll) { - DRM_DEBUG_KMS("No MG PHY PLL found\n"); + drm_dbg_kms(&dev_priv->drm, "No MG PHY PLL found\n"); goto err_unreference_tbt_pll; } intel_reference_shared_dpll(state, crtc, @@ -3492,7 +3518,8 @@ static void icl_pll_power_enable(struct drm_i915_private *dev_priv, * immediate. */ if (intel_de_wait_for_set(dev_priv, enable_reg, PLL_POWER_STATE, 1)) - DRM_ERROR("PLL %d Power not enabled\n", pll->info->id); + drm_err(&dev_priv->drm, "PLL %d Power not enabled\n", + pll->info->id); }

static void icl_pll_enable(struct drm_i915_private *dev_priv, @@ -3507,7 +3534,7 @@ static void icl_pll_enable(struct drm_i915_private *dev_priv,

/* Timeout is actually 600us. */ if (intel_de_wait_for_set(dev_priv, enable_reg, PLL_LOCK, 1)) - DRM_ERROR("PLL %d not locked\n", pll->info->id); + drm_err(&dev_priv->drm, "PLL %d not locked\n", pll->info->id); }

static void combo_pll_enable(struct drm_i915_private *dev_priv, @@ -3605,7 +3632,7 @@ static void icl_pll_disable(struct drm_i915_private *dev_priv,

/* Timeout is actually 1us. */ if (intel_de_wait_for_clear(dev_priv, enable_reg, PLL_LOCK, 1)) - DRM_ERROR("PLL %d locked\n", pll->info->id); + drm_err(&dev_priv->drm, "PLL %d locked\n", pll->info->id);

/* DVFS post sequence would be here. See the comment above. */

@@ -3618,7 +3645,8 @@ static void icl_pll_disable(struct drm_i915_private *dev_priv, * immediate. */ if (intel_de_wait_for_clear(dev_priv, enable_reg, PLL_POWER_STATE, 1)) - DRM_ERROR("PLL %d Power not disabled\n", pll->info->id); + drm_err(&dev_priv->drm, "PLL %d Power not disabled\n", + pll->info->id); }

static void combo_pll_disable(struct drm_i915_private *dev_priv, @@ -3657,23 +3685,24 @@ static void mg_pll_disable(struct drm_i915_private *dev_priv, static void icl_dump_hw_state(struct drm_i915_private *dev_priv, const struct intel_dpll_hw_state *hw_state) { - DRM_DEBUG_KMS("dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, " - "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, " - "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, " - "mg_pll_div2: 0x%x, mg_pll_lf: 0x%x, " - "mg_pll_frac_lock: 0x%x, mg_pll_ssc: 0x%x, " - "mg_pll_bias: 0x%x, mg_pll_tdc_coldst_bias: 0x%x\n", - hw_state->cfgcr0, hw_state->cfgcr1, - hw_state->mg_refclkin_ctl, - hw_state->mg_clktop2_coreclkctl1, - hw_state->mg_clktop2_hsclkctl, - hw_state->mg_pll_div0, - hw_state->mg_pll_div1, - hw_state->mg_pll_lf, - hw_state->mg_pll_frac_lock, - hw_state->mg_pll_ssc, - hw_state->mg_pll_bias, - hw_state->mg_pll_tdc_coldst_bias); + drm_dbg_kms(&dev_priv->drm, + "dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, " + "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, " + "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, " + "mg_pll_div2: 0x%x, mg_pll_lf: 0x%x, " + "mg_pll_frac_lock: 0x%x, mg_pll_ssc: 0x%x, " + "mg_pll_bias: 0x%x, mg_pll_tdc_coldst_bias: 0x%x\n", + hw_state->cfgcr0, hw_state->cfgcr1, + hw_state->mg_refclkin_ctl, + hw_state->mg_clktop2_coreclkctl1, + hw_state->mg_clktop2_hsclkctl, + hw_state->mg_pll_div0, + hw_state->mg_pll_div1, + hw_state->mg_pll_lf, + hw_state->mg_pll_frac_lock, + hw_state->mg_pll_ssc, + hw_state->mg_pll_bias, + hw_state->mg_pll_tdc_coldst_bias); }

static const struct intel_shared_dpll_funcs combo_pll_funcs = { @@ -3892,7 +3921,7 @@ void intel_update_active_dpll(struct intel_atomic_state *state, * @dev_priv: i915 drm device * @hw_state: hw state to be written to the log * - * Write the relevant values in @hw_state to dmesg using DRM_DEBUG_KMS. + * Write the relevant values in @hw_state to dmesg using drm_dbg_kms. */ void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv, const struct intel_dpll_hw_state *hw_state) @@ -3903,11 +3932,12 @@ void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv, /* fallback for platforms that don't use the shared dpll * infrastructure */ - DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " - "fp0: 0x%x, fp1: 0x%x\n", - hw_state->dpll, - hw_state->dpll_md, - hw_state->fp0, - hw_state->fp1); + drm_dbg_kms(&dev_priv->drm, + "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " + "fp0: 0x%x, fp1: 0x%x\n", + hw_state->dpll, + hw_state->dpll_md, + hw_state->fp0, + hw_state->fp1); } }

Conversion of instances of the printk based drm logging macros to the struct drm_device based logging macros in i915/display/intel_dp_mst.c. This also involves extracting the drm_i915_private device pointer from various intel types to use in the macros.

Signed-off-by: Wambui Karuga wambui.karugax@gmail.com --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 30 ++++++++++++++------- 1 file changed, 20 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index b8aee506d595..45028faa4409 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -42,6 +42,7 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder, struct drm_connector_state *conn_state, struct link_config_limits *limits) { + struct drm_i915_private *i915 = to_i915(encoder->base.dev); struct drm_atomic_state *state = crtc_state->uapi.state; struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); struct intel_dp *intel_dp = &intel_mst->primary->dp; @@ -73,7 +74,8 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder, }

if (slots < 0) { - DRM_DEBUG_KMS("failed finding vcpi slots:%d\n", slots); + drm_dbg_kms(&i915->drm, + "failed finding vcpi slots:%d\n", slots); return slots; }

@@ -322,15 +324,18 @@ static void intel_mst_disable_dp(struct intel_encoder *encoder, struct intel_dp *intel_dp = &intel_dig_port->dp; struct intel_connector *connector = to_intel_connector(old_conn_state->connector); + struct drm_i915_private *i915 = to_i915(encoder->base.dev); int ret;

- DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links); + drm_dbg_kms(&i915->drm, + "active links %d\n", intel_dp->active_mst_links);

drm_dp_mst_reset_vcpi_slots(&intel_dp->mst_mgr, connector->port);

ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr); if (ret) { - DRM_DEBUG_KMS("failed to update payload %d\n", ret); + drm_dbg_kms(&i915->drm, + "failed to update payload %d\n", ret); } if (old_crtc_state->has_audio) intel_audio_codec_disable(encoder, @@ -371,7 +376,8 @@ static void intel_mst_post_disable_dp(struct intel_encoder *encoder,

if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, DP_TP_STATUS_ACT_SENT, 1)) - DRM_ERROR("Timed out waiting for ACT sent when disabling\n"); + drm_err(&dev_priv->drm, + "Timed out waiting for ACT sent when disabling\n"); drm_dp_check_act_status(&intel_dp->mst_mgr);

drm_dp_mst_deallocate_vcpi(&intel_dp->mst_mgr, connector->port); @@ -405,7 +411,8 @@ static void intel_mst_post_disable_dp(struct intel_encoder *encoder, intel_dig_port->base.post_disable(&intel_dig_port->base, old_crtc_state, NULL);

- DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links); + drm_dbg_kms(&dev_priv->drm, "active links %d\n", + intel_dp->active_mst_links); }

static void intel_mst_pre_pll_enable_dp(struct intel_encoder *encoder, @@ -445,7 +452,8 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder, INTEL_GEN(dev_priv) >= 12 && first_mst_stream && !intel_dp_mst_is_master_trans(pipe_config));

- DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links); + drm_dbg_kms(&dev_priv->drm, "active links %d\n", + intel_dp->active_mst_links);

if (first_mst_stream) intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); @@ -461,7 +469,7 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder, pipe_config->pbn, pipe_config->dp_m_n.tu); if (!ret) - DRM_ERROR("failed to allocate vcpi\n"); + drm_err(&dev_priv->drm, "failed to allocate vcpi\n");

intel_dp->active_mst_links++; temp = intel_de_read(dev_priv, intel_dp->regs.dp_tp_status); @@ -491,11 +499,12 @@ static void intel_mst_enable_dp(struct intel_encoder *encoder, struct intel_dp *intel_dp = &intel_dig_port->dp; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

- DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links); + drm_dbg_kms(&dev_priv->drm, "active links %d\n", + intel_dp->active_mst_links);

if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, DP_TP_STATUS_ACT_SENT, 1)) - DRM_ERROR("Timed out waiting for ACT sent\n"); + drm_err(&dev_priv->drm, "Timed out waiting for ACT sent\n");

drm_dp_check_act_status(&intel_dp->mst_mgr);

@@ -727,7 +736,8 @@ static void intel_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr, { struct drm_i915_private *dev_priv = to_i915(connector->dev);

- DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id, connector->name); + drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", connector->base.id, + connector->name); drm_connector_unregister(connector);

if (dev_priv->fbdev)

Convert various instances of the printk based drm logging macros to the struct drm_device based logging macros in i915/display/intel_dsi_vbt.c. This also involves extracting the drm_i915_private device from the intel_dsi type for use in the logging macros.

This converts DRM_DEBUG/DRM_DEBUG_DRIVER to drm_dbg().

References: https://lists.freedesktop.org/archives/dri-devel/2020-January/253381.html Signed-off-by: Wambui Karuga wambui.karugax@gmail.com --- drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 162 +++++++++++-------- 1 file changed, 99 insertions(+), 63 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c index 3914cfdab511..694498f4b719 100644 --- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c +++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c @@ -136,7 +136,7 @@ static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, u16 len; enum port port;

- DRM_DEBUG_KMS("\n"); + drm_dbg_kms(&dev_priv->drm, "\n");

flags = *data++; type = *data++; @@ -158,7 +158,8 @@ static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,

dsi_device = intel_dsi->dsi_hosts[port]->device; if (!dsi_device) { - DRM_DEBUG_KMS("no dsi device for port %c\n", port_name(port)); + drm_dbg_kms(&dev_priv->drm, "no dsi device for port %c\n", + port_name(port)); goto out; }

@@ -182,7 +183,8 @@ static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: - DRM_DEBUG_DRIVER("Generic Read not yet implemented or used\n"); + drm_dbg(&dev_priv->drm, + "Generic Read not yet implemented or used\n"); break; case MIPI_DSI_GENERIC_LONG_WRITE: mipi_dsi_generic_write(dsi_device, data, len); @@ -194,7 +196,8 @@ static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, mipi_dsi_dcs_write_buffer(dsi_device, data, 2); break; case MIPI_DSI_DCS_READ: - DRM_DEBUG_DRIVER("DCS Read not yet implemented or used\n"); + drm_dbg(&dev_priv->drm, + "DCS Read not yet implemented or used\n"); break; case MIPI_DSI_DCS_LONG_WRITE: mipi_dsi_dcs_write_buffer(dsi_device, data, len); @@ -212,9 +215,10 @@ static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,

static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data) { + struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); u32 delay = *((const u32 *) data);

- DRM_DEBUG_KMS("\n"); + drm_dbg_kms(&i915->drm, "\n");

usleep_range(delay, delay + 10); data += 4; @@ -231,7 +235,8 @@ static void vlv_exec_gpio(struct drm_i915_private *dev_priv, u8 port;

if (gpio_index >= ARRAY_SIZE(vlv_gpio_table)) { - DRM_DEBUG_KMS("unknown gpio index %u\n", gpio_index); + drm_dbg_kms(&dev_priv->drm, "unknown gpio index %u\n", + gpio_index); return; }

@@ -244,10 +249,11 @@ static void vlv_exec_gpio(struct drm_i915_private *dev_priv, if (gpio_source == 0) { port = IOSF_PORT_GPIO_NC; } else if (gpio_source == 1) { - DRM_DEBUG_KMS("SC gpio not supported\n"); + drm_dbg_kms(&dev_priv->drm, "SC gpio not supported\n"); return; } else { - DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source); + drm_dbg_kms(&dev_priv->drm, + "unknown gpio source %u\n", gpio_source); return; } } @@ -291,13 +297,15 @@ static void chv_exec_gpio(struct drm_i915_private *dev_priv, } else { /* XXX: The spec is unclear about CHV GPIO on seq v2 */ if (gpio_source != 0) { - DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source); + drm_dbg_kms(&dev_priv->drm, + "unknown gpio source %u\n", gpio_source); return; }

if (gpio_index >= CHV_GPIO_IDX_START_E) { - DRM_DEBUG_KMS("invalid gpio index %u for GPIO N\n", - gpio_index); + drm_dbg_kms(&dev_priv->drm, + "invalid gpio index %u for GPIO N\n", + gpio_index); return; }

@@ -332,8 +340,9 @@ static void bxt_exec_gpio(struct drm_i915_private *dev_priv, GPIOD_OUT_HIGH);

if (IS_ERR_OR_NULL(gpio_desc)) { - DRM_ERROR("GPIO index %u request failed (%ld)\n", - gpio_index, PTR_ERR(gpio_desc)); + drm_err(&dev_priv->drm, + "GPIO index %u request failed (%ld)\n", + gpio_index, PTR_ERR(gpio_desc)); return; }

@@ -346,7 +355,7 @@ static void bxt_exec_gpio(struct drm_i915_private *dev_priv, static void icl_exec_gpio(struct drm_i915_private *dev_priv, u8 gpio_source, u8 gpio_index, bool value) { - DRM_DEBUG_KMS("Skipping ICL GPIO element execution\n"); + drm_dbg_kms(&dev_priv->drm, "Skipping ICL GPIO element execution\n"); }

static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) @@ -356,7 +365,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) u8 gpio_source, gpio_index = 0, gpio_number; bool value;

- DRM_DEBUG_KMS("\n"); + drm_dbg_kms(&dev_priv->drm, "\n");

if (dev_priv->vbt.dsi.seq_version >= 3) gpio_index = *data++; @@ -494,13 +503,16 @@ static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data)

static const u8 *mipi_exec_spi(struct intel_dsi *intel_dsi, const u8 *data) { - DRM_DEBUG_KMS("Skipping SPI element execution\n"); + struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); + + drm_dbg_kms(&i915->drm, "Skipping SPI element execution\n");

return data + *(data + 5) + 6; }

static const u8 *mipi_exec_pmic(struct intel_dsi *intel_dsi, const u8 *data) { + struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); #ifdef CONFIG_PMIC_OPREGION u32 value, mask, reg_address; u16 i2c_address; @@ -516,9 +528,10 @@ static const u8 *mipi_exec_pmic(struct intel_dsi *intel_dsi, const u8 *data) reg_address, value, mask); if (ret) - DRM_ERROR("%s failed, error: %d\n", __func__, ret); + drm_err(&i915->drm, "%s failed, error: %d\n", __func__, ret); #else - DRM_ERROR("Your hardware requires CONFIG_PMIC_OPREGION and it is not set\n"); + drm_err(&i915->drm, + "Your hardware requires CONFIG_PMIC_OPREGION and it is not set\n"); #endif

return data + 15; @@ -580,8 +593,8 @@ static void intel_dsi_vbt_exec(struct intel_dsi *intel_dsi,

drm_WARN_ON(&dev_priv->drm, *data != seq_id);

- DRM_DEBUG_KMS("Starting MIPI sequence %d - %s\n", - seq_id, sequence_name(seq_id)); + drm_dbg_kms(&dev_priv->drm, "Starting MIPI sequence %d - %s\n", + seq_id, sequence_name(seq_id));

/* Skip Sequence Byte. */ data++; @@ -613,18 +626,21 @@ static void intel_dsi_vbt_exec(struct intel_dsi *intel_dsi,

/* Consistency check if we have size. */ if (operation_size && data != next) { - DRM_ERROR("Inconsistent operation size\n"); + drm_err(&dev_priv->drm, + "Inconsistent operation size\n"); return; } } else if (operation_size) { /* We have size, skip. */ - DRM_DEBUG_KMS("Unsupported MIPI operation byte %u\n", - operation_byte); + drm_dbg_kms(&dev_priv->drm, + "Unsupported MIPI operation byte %u\n", + operation_byte); data += operation_size; } else { /* No size, can't skip without parsing. */ - DRM_ERROR("Unsupported MIPI operation byte %u\n", - operation_byte); + drm_err(&dev_priv->drm, + "Unsupported MIPI operation byte %u\n", + operation_byte); return; } } @@ -659,40 +675,54 @@ void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)

void intel_dsi_log_params(struct intel_dsi *intel_dsi) { - DRM_DEBUG_KMS("Pclk %d\n", intel_dsi->pclk); - DRM_DEBUG_KMS("Pixel overlap %d\n", intel_dsi->pixel_overlap); - DRM_DEBUG_KMS("Lane count %d\n", intel_dsi->lane_count); - DRM_DEBUG_KMS("DPHY param reg 0x%x\n", intel_dsi->dphy_reg); - DRM_DEBUG_KMS("Video mode format %s\n", - intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE ? - "non-burst with sync pulse" : - intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS ? - "non-burst with sync events" : - intel_dsi->video_mode_format == VIDEO_MODE_BURST ? - "burst" : "<unknown>"); - DRM_DEBUG_KMS("Burst mode ratio %d\n", intel_dsi->burst_mode_ratio); - DRM_DEBUG_KMS("Reset timer %d\n", intel_dsi->rst_timer_val); - DRM_DEBUG_KMS("Eot %s\n", enableddisabled(intel_dsi->eotp_pkt)); - DRM_DEBUG_KMS("Clockstop %s\n", enableddisabled(!intel_dsi->clock_stop)); - DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video"); + struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); + + drm_dbg_kms(&i915->drm, "Pclk %d\n", intel_dsi->pclk); + drm_dbg_kms(&i915->drm, "Pixel overlap %d\n", + intel_dsi->pixel_overlap); + drm_dbg_kms(&i915->drm, "Lane count %d\n", intel_dsi->lane_count); + drm_dbg_kms(&i915->drm, "DPHY param reg 0x%x\n", intel_dsi->dphy_reg); + drm_dbg_kms(&i915->drm, "Video mode format %s\n", + intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE ? + "non-burst with sync pulse" : + intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS ? + "non-burst with sync events" : + intel_dsi->video_mode_format == VIDEO_MODE_BURST ? + "burst" : "<unknown>"); + drm_dbg_kms(&i915->drm, "Burst mode ratio %d\n", + intel_dsi->burst_mode_ratio); + drm_dbg_kms(&i915->drm, "Reset timer %d\n", intel_dsi->rst_timer_val); + drm_dbg_kms(&i915->drm, "Eot %s\n", + enableddisabled(intel_dsi->eotp_pkt)); + drm_dbg_kms(&i915->drm, "Clockstop %s\n", + enableddisabled(!intel_dsi->clock_stop)); + drm_dbg_kms(&i915->drm, "Mode %s\n", + intel_dsi->operation_mode ? "command" : "video"); if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) - DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n"); + drm_dbg_kms(&i915->drm, + "Dual link: DSI_DUAL_LINK_FRONT_BACK\n"); else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT) - DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n"); + drm_dbg_kms(&i915->drm, + "Dual link: DSI_DUAL_LINK_PIXEL_ALT\n"); else - DRM_DEBUG_KMS("Dual link: NONE\n"); - DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format); - DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div); - DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout); - DRM_DEBUG_KMS("Turnaround Timeout 0x%x\n", intel_dsi->turn_arnd_val); - DRM_DEBUG_KMS("Init Count 0x%x\n", intel_dsi->init_count); - DRM_DEBUG_KMS("HS to LP Count 0x%x\n", intel_dsi->hs_to_lp_count); - DRM_DEBUG_KMS("LP Byte Clock %d\n", intel_dsi->lp_byte_clk); - DRM_DEBUG_KMS("DBI BW Timer 0x%x\n", intel_dsi->bw_timer); - DRM_DEBUG_KMS("LP to HS Clock Count 0x%x\n", intel_dsi->clk_lp_to_hs_count); - DRM_DEBUG_KMS("HS to LP Clock Count 0x%x\n", intel_dsi->clk_hs_to_lp_count); - DRM_DEBUG_KMS("BTA %s\n", - enableddisabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA))); + drm_dbg_kms(&i915->drm, "Dual link: NONE\n"); + drm_dbg_kms(&i915->drm, "Pixel Format %d\n", intel_dsi->pixel_format); + drm_dbg_kms(&i915->drm, "TLPX %d\n", intel_dsi->escape_clk_div); + drm_dbg_kms(&i915->drm, "LP RX Timeout 0x%x\n", + intel_dsi->lp_rx_timeout); + drm_dbg_kms(&i915->drm, "Turnaround Timeout 0x%x\n", + intel_dsi->turn_arnd_val); + drm_dbg_kms(&i915->drm, "Init Count 0x%x\n", intel_dsi->init_count); + drm_dbg_kms(&i915->drm, "HS to LP Count 0x%x\n", + intel_dsi->hs_to_lp_count); + drm_dbg_kms(&i915->drm, "LP Byte Clock %d\n", intel_dsi->lp_byte_clk); + drm_dbg_kms(&i915->drm, "DBI BW Timer 0x%x\n", intel_dsi->bw_timer); + drm_dbg_kms(&i915->drm, "LP to HS Clock Count 0x%x\n", + intel_dsi->clk_lp_to_hs_count); + drm_dbg_kms(&i915->drm, "HS to LP Clock Count 0x%x\n", + intel_dsi->clk_hs_to_lp_count); + drm_dbg_kms(&i915->drm, "BTA %s\n", + enableddisabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA))); }

bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id) @@ -705,7 +735,7 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id) u16 burst_mode_ratio; enum port port;

- DRM_DEBUG_KMS("\n"); + drm_dbg_kms(&dev_priv->drm, "\n");

intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1; intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0; @@ -764,7 +794,8 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id) mipi_config->target_burst_mode_freq = bitrate;

if (mipi_config->target_burst_mode_freq < bitrate) { - DRM_ERROR("Burst mode freq is less than computed\n"); + drm_err(&dev_priv->drm, + "Burst mode freq is less than computed\n"); return false; }

@@ -774,7 +805,8 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)

intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * burst_mode_ratio, 100); } else { - DRM_ERROR("Burst mode target is not set\n"); + drm_err(&dev_priv->drm, + "Burst mode target is not set\n"); return false; } } else @@ -857,17 +889,20 @@ void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on) ret = pinctrl_register_mappings(soc_pwm_pinctrl_map, ARRAY_SIZE(soc_pwm_pinctrl_map)); if (ret) - DRM_ERROR("Failed to register pwm0 pinmux mapping\n"); + drm_err(&dev_priv->drm, + "Failed to register pwm0 pinmux mapping\n");

pinctrl = devm_pinctrl_get_select(dev->dev, "soc_pwm0"); if (IS_ERR(pinctrl)) - DRM_ERROR("Failed to set pinmux to PWM\n"); + drm_err(&dev_priv->drm, + "Failed to set pinmux to PWM\n"); }

if (want_panel_gpio) { intel_dsi->gpio_panel = gpiod_get(dev->dev, "panel", flags); if (IS_ERR(intel_dsi->gpio_panel)) { - DRM_ERROR("Failed to own gpio for panel control\n"); + drm_err(&dev_priv->drm, + "Failed to own gpio for panel control\n"); intel_dsi->gpio_panel = NULL; } } @@ -876,7 +911,8 @@ void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on) intel_dsi->gpio_backlight = gpiod_get(dev->dev, "backlight", flags); if (IS_ERR(intel_dsi->gpio_backlight)) { - DRM_ERROR("Failed to own gpio for backlight control\n"); + drm_err(&dev_priv->drm, + "Failed to own gpio for backlight control\n"); intel_dsi->gpio_backlight = NULL; } }