These series patches is to add some new format supported by some rockchip socs, include: RK3288/RK3228/RK3328/RK3368/RK3399
these new format layout as following rule: 2 plane YCbCr 10bit index 0 = Y plane, [9:0] Y index 1 = Cr:Cb plane, [19:0] or index 1 = Cb:Cr plane, [19:0]
Sandy Huang (3): drm: Add some new format DRM_FORMAT_NVXX_10 drm/rockchip: Add vop_format_get_bpp to get format bpp drm/rockchip: Add support 10bit yuv format
drivers/gpu/drm/drm_fourcc.c | 18 +++++++++++++ drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 42 ++++++++++++++++++++++++++--- drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 1 + drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 2 ++ include/uapi/drm/drm_fourcc.h | 14 ++++++++++ 5 files changed, 74 insertions(+), 3 deletions(-)
These new format is supported by some rockchip socs:
DRM_FORMAT_NV12_10/DRM_FORMAT_NV21_10 DRM_FORMAT_NV16_10/DRM_FORMAT_NV61_10 DRM_FORMAT_NV24_10/DRM_FORMAT_NV42_10
Signed-off-by: Sandy Huang hjc@rock-chips.com --- drivers/gpu/drm/drm_fourcc.c | 18 ++++++++++++++++++ include/uapi/drm/drm_fourcc.h | 14 ++++++++++++++ 2 files changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c index c630064..f25fa81 100644 --- a/drivers/gpu/drm/drm_fourcc.c +++ b/drivers/gpu/drm/drm_fourcc.c @@ -274,6 +274,24 @@ const struct drm_format_info *__drm_format_info(u32 format) { .format = DRM_FORMAT_YUV420_10BIT, .depth = 0, .num_planes = 1, .cpp = { 0, 0, 0 }, .hsub = 2, .vsub = 2, .is_yuv = true }, + { .format = DRM_FORMAT_NV12_10, .depth = 0, + .num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 2, .vsub = 2, + .is_yuv = true }, + { .format = DRM_FORMAT_NV21_10, .depth = 0, + .num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 2, .vsub = 2, + .is_yuv = true }, + { .format = DRM_FORMAT_NV16_10, .depth = 0, + .num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 2, .vsub = 1, + .is_yuv = true }, + { .format = DRM_FORMAT_NV61_10, .depth = 0, + .num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 2, .vsub = 1, + .is_yuv = true }, + { .format = DRM_FORMAT_NV24_10, .depth = 0, + .num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 1, .vsub = 1, + .is_yuv = true }, + { .format = DRM_FORMAT_NV42_10, .depth = 0, + .num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 1, .vsub = 1, + .is_yuv = true }, };
unsigned int i; diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 3feeaa3..0479f47 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -238,6 +238,20 @@ extern "C" { #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
/* + * 2 plane YCbCr 10bit + * index 0 = Y plane, [9:0] Y + * index 1 = Cr:Cb plane, [19:0] + * or + * index 1 = Cb:Cr plane, [19:0] + */ +#define DRM_FORMAT_NV12_10 fourcc_code('N', 'A', '1', '2') /* 2x2 subsampled Cr:Cb plane */ +#define DRM_FORMAT_NV21_10 fourcc_code('N', 'A', '2', '1') /* 2x2 subsampled Cb:Cr plane */ +#define DRM_FORMAT_NV16_10 fourcc_code('N', 'A', '1', '6') /* 2x1 subsampled Cr:Cb plane */ +#define DRM_FORMAT_NV61_10 fourcc_code('N', 'A', '6', '1') /* 2x1 subsampled Cb:Cr plane */ +#define DRM_FORMAT_NV24_10 fourcc_code('N', 'A', '2', '4') /* non-subsampled Cr:Cb plane */ +#define DRM_FORMAT_NV42_10 fourcc_code('N', 'A', '4', '2') /* non-subsampled Cb:Cr plane */ + +/* * 2 plane YCbCr MSB aligned * index 0 = Y plane, [15:0] Y:x [10:6] little endian * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
Op 25-09-2019 om 10:06 schreef Sandy Huang:
These new format is supported by some rockchip socs:
DRM_FORMAT_NV12_10/DRM_FORMAT_NV21_10 DRM_FORMAT_NV16_10/DRM_FORMAT_NV61_10 DRM_FORMAT_NV24_10/DRM_FORMAT_NV42_10
Signed-off-by: Sandy Huang hjc@rock-chips.com
drivers/gpu/drm/drm_fourcc.c | 18 ++++++++++++++++++ include/uapi/drm/drm_fourcc.h | 14 ++++++++++++++ 2 files changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c index c630064..f25fa81 100644 --- a/drivers/gpu/drm/drm_fourcc.c +++ b/drivers/gpu/drm/drm_fourcc.c @@ -274,6 +274,24 @@ const struct drm_format_info *__drm_format_info(u32 format) { .format = DRM_FORMAT_YUV420_10BIT, .depth = 0, .num_planes = 1, .cpp = { 0, 0, 0 }, .hsub = 2, .vsub = 2, .is_yuv = true },
{ .format = DRM_FORMAT_NV12_10, .depth = 0,.num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 2, .vsub = 2,.is_yuv = true },{ .format = DRM_FORMAT_NV21_10, .depth = 0,.num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 2, .vsub = 2,.is_yuv = true },{ .format = DRM_FORMAT_NV16_10, .depth = 0,.num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 2, .vsub = 1,.is_yuv = true },{ .format = DRM_FORMAT_NV61_10, .depth = 0,.num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 2, .vsub = 1,.is_yuv = true },{ .format = DRM_FORMAT_NV24_10, .depth = 0,.num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 1, .vsub = 1,.is_yuv = true },{ .format = DRM_FORMAT_NV42_10, .depth = 0,.num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 1, .vsub = 1,.is_yuv = true },};
unsigned int i;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 3feeaa3..0479f47 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -238,6 +238,20 @@ extern "C" { #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
/*
- 2 plane YCbCr 10bit
- index 0 = Y plane, [9:0] Y
- index 1 = Cr:Cb plane, [19:0]
- or
- index 1 = Cb:Cr plane, [19:0]
- */
+#define DRM_FORMAT_NV12_10 fourcc_code('N', 'A', '1', '2') /* 2x2 subsampled Cr:Cb plane */ +#define DRM_FORMAT_NV21_10 fourcc_code('N', 'A', '2', '1') /* 2x2 subsampled Cb:Cr plane */ +#define DRM_FORMAT_NV16_10 fourcc_code('N', 'A', '1', '6') /* 2x1 subsampled Cr:Cb plane */ +#define DRM_FORMAT_NV61_10 fourcc_code('N', 'A', '6', '1') /* 2x1 subsampled Cb:Cr plane */ +#define DRM_FORMAT_NV24_10 fourcc_code('N', 'A', '2', '4') /* non-subsampled Cr:Cb plane */ +#define DRM_FORMAT_NV42_10 fourcc_code('N', 'A', '4', '2') /* non-subsampled Cb:Cr plane */
+/*
- 2 plane YCbCr MSB aligned
- index 0 = Y plane, [15:0] Y:x [10:6] little endian
- index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
What are the other bits, they are not mentioned?
在 2019/9/25 下午4:17, Maarten Lankhorst 写道:
Op 25-09-2019 om 10:06 schreef Sandy Huang:
These new format is supported by some rockchip socs:
DRM_FORMAT_NV12_10/DRM_FORMAT_NV21_10 DRM_FORMAT_NV16_10/DRM_FORMAT_NV61_10 DRM_FORMAT_NV24_10/DRM_FORMAT_NV42_10
Signed-off-by: Sandy Huang hjc@rock-chips.com
drivers/gpu/drm/drm_fourcc.c | 18 ++++++++++++++++++ include/uapi/drm/drm_fourcc.h | 14 ++++++++++++++ 2 files changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c index c630064..f25fa81 100644 --- a/drivers/gpu/drm/drm_fourcc.c +++ b/drivers/gpu/drm/drm_fourcc.c @@ -274,6 +274,24 @@ const struct drm_format_info *__drm_format_info(u32 format) { .format = DRM_FORMAT_YUV420_10BIT, .depth = 0, .num_planes = 1, .cpp = { 0, 0, 0 }, .hsub = 2, .vsub = 2, .is_yuv = true },
{ .format = DRM_FORMAT_NV12_10, .depth = 0,.num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 2, .vsub = 2,.is_yuv = true },{ .format = DRM_FORMAT_NV21_10, .depth = 0,.num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 2, .vsub = 2,.is_yuv = true },{ .format = DRM_FORMAT_NV16_10, .depth = 0,.num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 2, .vsub = 1,.is_yuv = true },{ .format = DRM_FORMAT_NV61_10, .depth = 0,.num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 2, .vsub = 1,.is_yuv = true },{ .format = DRM_FORMAT_NV24_10, .depth = 0,.num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 1, .vsub = 1,.is_yuv = true },{ .format = DRM_FORMAT_NV42_10, .depth = 0,.num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 1, .vsub = 1,.is_yuv = true },};
unsigned int i;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 3feeaa3..0479f47 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -238,6 +238,20 @@ extern "C" { #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
/*
- 2 plane YCbCr 10bit
- index 0 = Y plane, [9:0] Y
- index 1 = Cr:Cb plane, [19:0]
- or
- index 1 = Cb:Cr plane, [19:0]
- */
+#define DRM_FORMAT_NV12_10 fourcc_code('N', 'A', '1', '2') /* 2x2 subsampled Cr:Cb plane */ +#define DRM_FORMAT_NV21_10 fourcc_code('N', 'A', '2', '1') /* 2x2 subsampled Cb:Cr plane */ +#define DRM_FORMAT_NV16_10 fourcc_code('N', 'A', '1', '6') /* 2x1 subsampled Cr:Cb plane */ +#define DRM_FORMAT_NV61_10 fourcc_code('N', 'A', '6', '1') /* 2x1 subsampled Cb:Cr plane */ +#define DRM_FORMAT_NV24_10 fourcc_code('N', 'A', '2', '4') /* non-subsampled Cr:Cb plane */ +#define DRM_FORMAT_NV42_10 fourcc_code('N', 'A', '4', '2') /* non-subsampled Cb:Cr plane */
+/*
- 2 plane YCbCr MSB aligned
- index 0 = Y plane, [15:0] Y:x [10:6] little endian
- index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
What are the other bits, they are not mentioned?
It's compact layout
Yplane:
Y0[9:0]Y1[9:0]Y2[9:0]Y3[9:0]...
UVplane:
U0[9:0]V0[9:0]U1[9:0]V1[9:0]...
Op 25-09-2019 om 10:32 schreef sandy.huang:
在 2019/9/25 下午4:17, Maarten Lankhorst 写道:
Op 25-09-2019 om 10:06 schreef Sandy Huang:
These new format is supported by some rockchip socs:
DRM_FORMAT_NV12_10/DRM_FORMAT_NV21_10 DRM_FORMAT_NV16_10/DRM_FORMAT_NV61_10 DRM_FORMAT_NV24_10/DRM_FORMAT_NV42_10
Signed-off-by: Sandy Huang hjc@rock-chips.com
drivers/gpu/drm/drm_fourcc.c | 18 ++++++++++++++++++ include/uapi/drm/drm_fourcc.h | 14 ++++++++++++++ 2 files changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c index c630064..f25fa81 100644 --- a/drivers/gpu/drm/drm_fourcc.c +++ b/drivers/gpu/drm/drm_fourcc.c @@ -274,6 +274,24 @@ const struct drm_format_info *__drm_format_info(u32 format) { .format = DRM_FORMAT_YUV420_10BIT, .depth = 0, .num_planes = 1, .cpp = { 0, 0, 0 }, .hsub = 2, .vsub = 2, .is_yuv = true }, + { .format = DRM_FORMAT_NV12_10, .depth = 0, + .num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 2, .vsub = 2, + .is_yuv = true }, + { .format = DRM_FORMAT_NV21_10, .depth = 0, + .num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 2, .vsub = 2, + .is_yuv = true }, + { .format = DRM_FORMAT_NV16_10, .depth = 0, + .num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 2, .vsub = 1, + .is_yuv = true }, + { .format = DRM_FORMAT_NV61_10, .depth = 0, + .num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 2, .vsub = 1, + .is_yuv = true }, + { .format = DRM_FORMAT_NV24_10, .depth = 0, + .num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 1, .vsub = 1, + .is_yuv = true }, + { .format = DRM_FORMAT_NV42_10, .depth = 0, + .num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 1, .vsub = 1, + .is_yuv = true }, }; unsigned int i; diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 3feeaa3..0479f47 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -238,6 +238,20 @@ extern "C" { #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */ /*
- 2 plane YCbCr 10bit
- index 0 = Y plane, [9:0] Y
- index 1 = Cr:Cb plane, [19:0]
- or
- index 1 = Cb:Cr plane, [19:0]
- */
+#define DRM_FORMAT_NV12_10 fourcc_code('N', 'A', '1', '2') /* 2x2 subsampled Cr:Cb plane */ +#define DRM_FORMAT_NV21_10 fourcc_code('N', 'A', '2', '1') /* 2x2 subsampled Cb:Cr plane */ +#define DRM_FORMAT_NV16_10 fourcc_code('N', 'A', '1', '6') /* 2x1 subsampled Cr:Cb plane */ +#define DRM_FORMAT_NV61_10 fourcc_code('N', 'A', '6', '1') /* 2x1 subsampled Cb:Cr plane */ +#define DRM_FORMAT_NV24_10 fourcc_code('N', 'A', '2', '4') /* non-subsampled Cr:Cb plane */ +#define DRM_FORMAT_NV42_10 fourcc_code('N', 'A', '4', '2') /* non-subsampled Cb:Cr plane */
+/* * 2 plane YCbCr MSB aligned * index 0 = Y plane, [15:0] Y:x [10:6] little endian * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
What are the other bits, they are not mentioned?
It's compact layout
Yplane:
Y0[9:0]Y1[9:0]Y2[9:0]Y3[9:0]...
UVplane:
U0[9:0]V0[9:0]U1[9:0]V1[9:0]...
This should be put in the comment then, for clarity. :) Probably needs 4 pixels to describe how it fits in 5 (or 10 for cbcr) bytes.
Cheers,
Maarten
在 2019/9/25 下午5:23, Maarten Lankhorst 写道:
Op 25-09-2019 om 10:32 schreef sandy.huang:
在 2019/9/25 下午4:17, Maarten Lankhorst 写道:
Op 25-09-2019 om 10:06 schreef Sandy Huang:
These new format is supported by some rockchip socs:
DRM_FORMAT_NV12_10/DRM_FORMAT_NV21_10 DRM_FORMAT_NV16_10/DRM_FORMAT_NV61_10 DRM_FORMAT_NV24_10/DRM_FORMAT_NV42_10
Signed-off-by: Sandy Huang hjc@rock-chips.com
drivers/gpu/drm/drm_fourcc.c | 18 ++++++++++++++++++ include/uapi/drm/drm_fourcc.h | 14 ++++++++++++++ 2 files changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c index c630064..f25fa81 100644 --- a/drivers/gpu/drm/drm_fourcc.c +++ b/drivers/gpu/drm/drm_fourcc.c @@ -274,6 +274,24 @@ const struct drm_format_info *__drm_format_info(u32 format) { .format = DRM_FORMAT_YUV420_10BIT, .depth = 0, .num_planes = 1, .cpp = { 0, 0, 0 }, .hsub = 2, .vsub = 2, .is_yuv = true }, + { .format = DRM_FORMAT_NV12_10, .depth = 0, + .num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 2, .vsub = 2, + .is_yuv = true }, + { .format = DRM_FORMAT_NV21_10, .depth = 0, + .num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 2, .vsub = 2, + .is_yuv = true }, + { .format = DRM_FORMAT_NV16_10, .depth = 0, + .num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 2, .vsub = 1, + .is_yuv = true }, + { .format = DRM_FORMAT_NV61_10, .depth = 0, + .num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 2, .vsub = 1, + .is_yuv = true }, + { .format = DRM_FORMAT_NV24_10, .depth = 0, + .num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 1, .vsub = 1, + .is_yuv = true }, + { .format = DRM_FORMAT_NV42_10, .depth = 0, + .num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 1, .vsub = 1, + .is_yuv = true }, }; unsigned int i; diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 3feeaa3..0479f47 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -238,6 +238,20 @@ extern "C" { #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */ /*
- 2 plane YCbCr 10bit
- index 0 = Y plane, [9:0] Y
- index 1 = Cr:Cb plane, [19:0]
- or
- index 1 = Cb:Cr plane, [19:0]
- */
+#define DRM_FORMAT_NV12_10 fourcc_code('N', 'A', '1', '2') /* 2x2 subsampled Cr:Cb plane */ +#define DRM_FORMAT_NV21_10 fourcc_code('N', 'A', '2', '1') /* 2x2 subsampled Cb:Cr plane */ +#define DRM_FORMAT_NV16_10 fourcc_code('N', 'A', '1', '6') /* 2x1 subsampled Cr:Cb plane */ +#define DRM_FORMAT_NV61_10 fourcc_code('N', 'A', '6', '1') /* 2x1 subsampled Cb:Cr plane */ +#define DRM_FORMAT_NV24_10 fourcc_code('N', 'A', '2', '4') /* non-subsampled Cr:Cb plane */ +#define DRM_FORMAT_NV42_10 fourcc_code('N', 'A', '4', '2') /* non-subsampled Cb:Cr plane */
+/* * 2 plane YCbCr MSB aligned * index 0 = Y plane, [15:0] Y:x [10:6] little endian * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
What are the other bits, they are not mentioned?
It's compact layout
Yplane:
Y0[9:0]Y1[9:0]Y2[9:0]Y3[9:0]...
UVplane:
U0[9:0]V0[9:0]U1[9:0]V1[9:0]...
This should be put in the comment then, for clarity. :) Probably needs 4 pixels to describe how it fits in 5 (or 10 for cbcr) bytes.
Cheers,
Maarten
OK, I will add this describe at next version.
On Wed, Sep 25, 2019 at 10:07 AM Sandy Huang hjc@rock-chips.com wrote:
These new format is supported by some rockchip socs:
DRM_FORMAT_NV12_10/DRM_FORMAT_NV21_10 DRM_FORMAT_NV16_10/DRM_FORMAT_NV61_10 DRM_FORMAT_NV24_10/DRM_FORMAT_NV42_10
Signed-off-by: Sandy Huang hjc@rock-chips.com
Again, please use the block formats to describe these, plus proper comments as Maarten also asked for. -Daniel
drivers/gpu/drm/drm_fourcc.c | 18 ++++++++++++++++++ include/uapi/drm/drm_fourcc.h | 14 ++++++++++++++ 2 files changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c index c630064..f25fa81 100644 --- a/drivers/gpu/drm/drm_fourcc.c +++ b/drivers/gpu/drm/drm_fourcc.c @@ -274,6 +274,24 @@ const struct drm_format_info *__drm_format_info(u32 format) { .format = DRM_FORMAT_YUV420_10BIT, .depth = 0, .num_planes = 1, .cpp = { 0, 0, 0 }, .hsub = 2, .vsub = 2, .is_yuv = true },
{ .format = DRM_FORMAT_NV12_10, .depth = 0,.num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 2, .vsub = 2,.is_yuv = true },{ .format = DRM_FORMAT_NV21_10, .depth = 0,.num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 2, .vsub = 2,.is_yuv = true },{ .format = DRM_FORMAT_NV16_10, .depth = 0,.num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 2, .vsub = 1,.is_yuv = true },{ .format = DRM_FORMAT_NV61_10, .depth = 0,.num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 2, .vsub = 1,.is_yuv = true },{ .format = DRM_FORMAT_NV24_10, .depth = 0,.num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 1, .vsub = 1,.is_yuv = true },{ .format = DRM_FORMAT_NV42_10, .depth = 0,.num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 1, .vsub = 1,.is_yuv = true }, }; unsigned int i;diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 3feeaa3..0479f47 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -238,6 +238,20 @@ extern "C" { #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
/*
- 2 plane YCbCr 10bit
- index 0 = Y plane, [9:0] Y
- index 1 = Cr:Cb plane, [19:0]
- or
- index 1 = Cb:Cr plane, [19:0]
- */
+#define DRM_FORMAT_NV12_10 fourcc_code('N', 'A', '1', '2') /* 2x2 subsampled Cr:Cb plane */ +#define DRM_FORMAT_NV21_10 fourcc_code('N', 'A', '2', '1') /* 2x2 subsampled Cb:Cr plane */ +#define DRM_FORMAT_NV16_10 fourcc_code('N', 'A', '1', '6') /* 2x1 subsampled Cr:Cb plane */ +#define DRM_FORMAT_NV61_10 fourcc_code('N', 'A', '6', '1') /* 2x1 subsampled Cb:Cr plane */ +#define DRM_FORMAT_NV24_10 fourcc_code('N', 'A', '2', '4') /* non-subsampled Cr:Cb plane */ +#define DRM_FORMAT_NV42_10 fourcc_code('N', 'A', '4', '2') /* non-subsampled Cb:Cr plane */
+/*
- 2 plane YCbCr MSB aligned
- index 0 = Y plane, [15:0] Y:x [10:6] little endian
- index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
-- 2.7.4
在 2019/9/25 下午7:20, Daniel Vetter 写道:
On Wed, Sep 25, 2019 at 10:07 AM Sandy Huang hjc@rock-chips.com wrote:
These new format is supported by some rockchip socs:
DRM_FORMAT_NV12_10/DRM_FORMAT_NV21_10 DRM_FORMAT_NV16_10/DRM_FORMAT_NV61_10 DRM_FORMAT_NV24_10/DRM_FORMAT_NV42_10
Signed-off-by: Sandy Huang hjc@rock-chips.com
Again, please use the block formats to describe these, plus proper comments as Maarten also asked for. -Daniel
Hi Daniel and Maarten,
The new v2 patches have update to block formats, please help to review, thanks.
drivers/gpu/drm/drm_fourcc.c | 18 ++++++++++++++++++ include/uapi/drm/drm_fourcc.h | 14 ++++++++++++++ 2 files changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c index c630064..f25fa81 100644 --- a/drivers/gpu/drm/drm_fourcc.c +++ b/drivers/gpu/drm/drm_fourcc.c @@ -274,6 +274,24 @@ const struct drm_format_info *__drm_format_info(u32 format) { .format = DRM_FORMAT_YUV420_10BIT, .depth = 0, .num_planes = 1, .cpp = { 0, 0, 0 }, .hsub = 2, .vsub = 2, .is_yuv = true },
{ .format = DRM_FORMAT_NV12_10, .depth = 0,.num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 2, .vsub = 2,.is_yuv = true },{ .format = DRM_FORMAT_NV21_10, .depth = 0,.num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 2, .vsub = 2,.is_yuv = true },{ .format = DRM_FORMAT_NV16_10, .depth = 0,.num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 2, .vsub = 1,.is_yuv = true },{ .format = DRM_FORMAT_NV61_10, .depth = 0,.num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 2, .vsub = 1,.is_yuv = true },{ .format = DRM_FORMAT_NV24_10, .depth = 0,.num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 1, .vsub = 1,.is_yuv = true },{ .format = DRM_FORMAT_NV42_10, .depth = 0,.num_planes = 2, .cpp = { 0, 0, 0 }, .hsub = 1, .vsub = 1,.is_yuv = true }, }; unsigned int i;diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 3feeaa3..0479f47 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -238,6 +238,20 @@ extern "C" { #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
/*
- 2 plane YCbCr 10bit
- index 0 = Y plane, [9:0] Y
- index 1 = Cr:Cb plane, [19:0]
- or
- index 1 = Cb:Cr plane, [19:0]
- */
+#define DRM_FORMAT_NV12_10 fourcc_code('N', 'A', '1', '2') /* 2x2 subsampled Cr:Cb plane */ +#define DRM_FORMAT_NV21_10 fourcc_code('N', 'A', '2', '1') /* 2x2 subsampled Cb:Cr plane */ +#define DRM_FORMAT_NV16_10 fourcc_code('N', 'A', '1', '6') /* 2x1 subsampled Cr:Cb plane */ +#define DRM_FORMAT_NV61_10 fourcc_code('N', 'A', '6', '1') /* 2x1 subsampled Cb:Cr plane */ +#define DRM_FORMAT_NV24_10 fourcc_code('N', 'A', '2', '4') /* non-subsampled Cr:Cb plane */ +#define DRM_FORMAT_NV42_10 fourcc_code('N', 'A', '4', '2') /* non-subsampled Cb:Cr plane */
+/*
- 2 plane YCbCr MSB aligned
- index 0 = Y plane, [15:0] Y:x [10:6] little endian
- index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
-- 2.7.4
For 10bit yuv format, we need to get format bpp each plane, so we Add vop_format_get_bpp() to instead of format->cpp[];
Signed-off-by: Sandy Huang hjc@rock-chips.com --- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 2f821c5..ce5b45d 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -249,6 +249,25 @@ static bool has_rb_swapped(uint32_t format) } }
+static int vop_format_get_bpp(u32 format, u8 plane) +{ + const struct drm_format_info *info; + + info = drm_format_info(format); + if (!info || plane >= info->num_planes) + return 0; + + if (info->cpp[0] == 0) { + /* only support DRM_FORMAT_NVxx_10 now */ + if (plane == 0) + return 10; + else + return 20; + } + + return info->cpp[plane] * 8; +} + static enum vop_data_format vop_convert_format(uint32_t format) { switch (format) { @@ -832,7 +851,8 @@ static void vop_plane_atomic_update(struct drm_plane *plane, dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
- offset = (src->x1 >> 16) * fb->format->cpp[0]; + offset = (src->x1 >> 16) * + vop_format_get_bpp(fb->format->format, 0) / 8; offset += (src->y1 >> 16) * fb->pitches[0]; dma_addr = rk_obj->dma_addr + offset + fb->offsets[0];
@@ -859,12 +879,12 @@ static void vop_plane_atomic_update(struct drm_plane *plane, if (is_yuv) { int hsub = fb->format->hsub; int vsub = fb->format->vsub; - int bpp = fb->format->cpp[1]; + int bpp = vop_format_get_bpp(fb->format->format, 1);
uv_obj = fb->obj[1]; rk_uv_obj = to_rockchip_obj(uv_obj);
- offset = (src->x1 >> 16) * bpp / hsub; + offset = (src->x1 >> 16) * bpp / 8 / hsub; offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
Add support 10bit yuv format display for rockchip some socs, include: RK3288/RK3228/RK3328/RK3368/RK3399
Signed-off-by: Sandy Huang hjc@rock-chips.com --- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 16 ++++++++++++++++ drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 1 + drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 2 ++ 3 files changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index ce5b45d..9cb9fff 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -249,6 +249,21 @@ static bool has_rb_swapped(uint32_t format) } }
+static bool is_yuv_10bit(uint32_t format) +{ + switch (format) { + case DRM_FORMAT_NV12_10: + case DRM_FORMAT_NV21_10: + case DRM_FORMAT_NV16_10: + case DRM_FORMAT_NV61_10: + case DRM_FORMAT_NV24_10: + case DRM_FORMAT_NV42_10: + return true; + default: + return false; + } +} + static int vop_format_get_bpp(u32 format, u8 plane) { const struct drm_format_info *info; @@ -890,6 +905,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4)); VOP_WIN_SET(vop, win, uv_mst, dma_addr); + VOP_WIN_SET(vop, win, fmt_10, is_yuv_10bit(fb->format->format));
for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) { VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h index 2149a889..adc2b0b5 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h @@ -133,6 +133,7 @@ struct vop_win_phy { struct vop_reg gate; struct vop_reg format; struct vop_reg rb_swap; + struct vop_reg fmt_10; struct vop_reg act_info; struct vop_reg dsp_info; struct vop_reg dsp_st; diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index d1494be..732e535 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -544,6 +544,7 @@ static const struct vop_win_phy rk3288_win01_data = { .nformats = ARRAY_SIZE(formats_win_full), .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0), .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1), + .fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4), .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12), .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0), .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0), @@ -674,6 +675,7 @@ static const struct vop_win_phy rk3368_win01_data = { .nformats = ARRAY_SIZE(formats_win_full), .enable = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 0), .format = VOP_REG(RK3368_WIN0_CTRL0, 0x7, 1), + .fmt_10 = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 4), .rb_swap = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 12), .x_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 21), .y_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 22),
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