The VPU embeds a "Register DMA" that can write a sequence of registers on the VPU AHB bus, either manually or triggered by an internal IRQ event like VSYNC or a line input counter.
The initial implementation handles a single channel (over 8), triggered by the VSYNC irq and does not handle the RDMA irq.
The RDMA will be usefull to reset and program the AFBC decoder unit on each vsync without involving the interrupt handler that can be masked for a long period of time, producing display glitches.
For this we use the meson_rdma_writel_sync() which adds the register write tuple (VPU register offset and register value) to the RDMA buffer and write the value to the HW.
When enabled, the RDMA is enabled to rewritte the same sequence at the next VSYNC event, until a new buffer is committed to the OSD plane.
The the Amlogic G12A is switched to RDMA, the Amlogic GXM Decoder doesn't need a reset/reprogram at each vsync.
Changes since v1 at [1]: - Fixed a regression when AFBC was not used, adding a reset() call for the afbc module - Added a define for the RDMA descriptor size - Fixed overflow detection
[1] https://patchwork.freedesktop.org/series/68021/#rev1
Neil Armstrong (3): drm/meson: add RDMA register bits defines drm/meson: add RDMA module driver drm/meson: use RDMA to reconfigure AFBC on vsync
drivers/gpu/drm/meson/Makefile | 2 +- drivers/gpu/drm/meson/meson_crtc.c | 27 ++--- drivers/gpu/drm/meson/meson_drv.c | 14 ++- drivers/gpu/drm/meson/meson_drv.h | 6 ++ drivers/gpu/drm/meson/meson_osd_afbcd.c | 100 ++++++++++-------- drivers/gpu/drm/meson/meson_rdma.c | 132 ++++++++++++++++++++++++ drivers/gpu/drm/meson/meson_rdma.h | 21 ++++ drivers/gpu/drm/meson/meson_registers.h | 48 +++++++++ 8 files changed, 283 insertions(+), 67 deletions(-) create mode 100644 drivers/gpu/drm/meson/meson_rdma.c create mode 100644 drivers/gpu/drm/meson/meson_rdma.h
The Amlogic VPU embeds a "Register DMA" that can write a sequence of registers on the VPU AHB bus, either manually or triggered by an internal IRQ event like VSYNC or a line input counter.
This adds the register defines.
Signed-off-by: Neil Armstrong narmstrong@baylibre.com --- drivers/gpu/drm/meson/meson_registers.h | 48 +++++++++++++++++++++++++ 1 file changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/meson/meson_registers.h b/drivers/gpu/drm/meson/meson_registers.h index 547bee04b46e..8ea00546cd4e 100644 --- a/drivers/gpu/drm/meson/meson_registers.h +++ b/drivers/gpu/drm/meson/meson_registers.h @@ -1211,11 +1211,59 @@ #define RDMA_AHB_START_ADDR_7 0x110e #define RDMA_AHB_END_ADDR_7 0x110f #define RDMA_ACCESS_AUTO 0x1110 +#define RDMA_ACCESS_TRIGGER_CHAN3 GENMASK(31, 24) +#define RDMA_ACCESS_TRIGGER_CHAN2 GENMASK(23, 16) +#define RDMA_ACCESS_TRIGGER_CHAN1 GENMASK(15, 8) +#define RDMA_ACCESS_TRIGGER_STOP 0 +#define RDMA_ACCESS_TRIGGER_VSYNC 1 +#define RDMA_ACCESS_TRIGGER_LINE 32 +#define RDMA_ACCESS_RW_FLAG_CHAN3 BIT(7) +#define RDMA_ACCESS_RW_FLAG_CHAN2 BIT(6) +#define RDMA_ACCESS_RW_FLAG_CHAN1 BIT(5) +#define RDMA_ACCESS_ADDR_INC_CHAN3 BIT(3) +#define RDMA_ACCESS_ADDR_INC_CHAN2 BIT(2) +#define RDMA_ACCESS_ADDR_INC_CHAN1 BIT(1) #define RDMA_ACCESS_AUTO2 0x1111 +#define RDMA_ACCESS_RW_FLAG_CHAN7 BIT(7) +#define RDMA_ACCESS_RW_FLAG_CHAN6 BIT(6) +#define RDMA_ACCESS_RW_FLAG_CHAN5 BIT(5) +#define RDMA_ACCESS_RW_FLAG_CHAN4 BIT(4) +#define RDMA_ACCESS_ADDR_INC_CHAN7 BIT(3) +#define RDMA_ACCESS_ADDR_INC_CHAN6 BIT(2) +#define RDMA_ACCESS_ADDR_INC_CHAN5 BIT(1) +#define RDMA_ACCESS_ADDR_INC_CHAN4 BIT(0) #define RDMA_ACCESS_AUTO3 0x1112 +#define RDMA_ACCESS_TRIGGER_CHAN7 GENMASK(31, 24) +#define RDMA_ACCESS_TRIGGER_CHAN6 GENMASK(23, 16) +#define RDMA_ACCESS_TRIGGER_CHAN5 GENMASK(15, 8) +#define RDMA_ACCESS_TRIGGER_CHAN4 GENMASK(7, 0) #define RDMA_ACCESS_MAN 0x1113 +#define RDMA_ACCESS_MAN_RW_FLAG BIT(2) +#define RDMA_ACCESS_MAN_ADDR_INC BIT(1) +#define RDMA_ACCESS_MAN_START BIT(0) #define RDMA_CTRL 0x1114 +#define RDMA_IRQ_CLEAR_CHAN7 BIT(31) +#define RDMA_IRQ_CLEAR_CHAN6 BIT(30) +#define RDMA_IRQ_CLEAR_CHAN5 BIT(29) +#define RDMA_IRQ_CLEAR_CHAN4 BIT(28) +#define RDMA_IRQ_CLEAR_CHAN3 BIT(27) +#define RDMA_IRQ_CLEAR_CHAN2 BIT(26) +#define RDMA_IRQ_CLEAR_CHAN1 BIT(25) +#define RDMA_IRQ_CLEAR_CHAN_MAN BIT(24) +#define RDMA_DEFAULT_CONFIG (BIT(7) | BIT(6)) +#define RDMA_CTRL_AHB_WR_BURST GENMASK(5, 4) +#define RDMA_CTRL_AHB_RD_BURST GENMASK(3, 2) +#define RDMA_CTRL_SW_RESET BIT(1) +#define RDMA_CTRL_FREE_CLK_EN BIT(0) #define RDMA_STATUS 0x1115 +#define RDMA_IRQ_STAT_CHAN7 BIT(31) +#define RDMA_IRQ_STAT_CHAN6 BIT(30) +#define RDMA_IRQ_STAT_CHAN5 BIT(29) +#define RDMA_IRQ_STAT_CHAN4 BIT(28) +#define RDMA_IRQ_STAT_CHAN3 BIT(27) +#define RDMA_IRQ_STAT_CHAN2 BIT(26) +#define RDMA_IRQ_STAT_CHAN1 BIT(25) +#define RDMA_IRQ_STAT_CHAN_MAN BIT(24) #define RDMA_STATUS2 0x1116 #define RDMA_STATUS3 0x1117 #define L_GAMMA_CNTL_PORT 0x1400
The VPU embeds a "Register DMA" that can write a sequence of registers on the VPU AHB bus, either manually or triggered by an internal IRQ event like VSYNC or a line input counter.
The initial implementation handles a single channel (over 8), triggered by the VSYNC irq and does not handle the RDMA irq.
The RDMA will be usefull to reset and program the AFBC decoder unit on each vsync without involving the interrupt handler that can be masked for a log period of time, producing display glitches.
Signed-off-by: Neil Armstrong narmstrong@baylibre.com --- drivers/gpu/drm/meson/Makefile | 2 +- drivers/gpu/drm/meson/meson_drv.c | 14 ++- drivers/gpu/drm/meson/meson_drv.h | 6 ++ drivers/gpu/drm/meson/meson_rdma.c | 132 +++++++++++++++++++++++++++++ drivers/gpu/drm/meson/meson_rdma.h | 21 +++++ 5 files changed, 171 insertions(+), 4 deletions(-) create mode 100644 drivers/gpu/drm/meson/meson_rdma.c create mode 100644 drivers/gpu/drm/meson/meson_rdma.h
diff --git a/drivers/gpu/drm/meson/Makefile b/drivers/gpu/drm/meson/Makefile index b1fa055aaed3..9e36f0c7b816 100644 --- a/drivers/gpu/drm/meson/Makefile +++ b/drivers/gpu/drm/meson/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only meson-drm-y := meson_drv.o meson_plane.o meson_crtc.o meson_venc_cvbs.o meson-drm-y += meson_viu.o meson_vpp.o meson_venc.o meson_vclk.o meson_overlay.o -meson-drm-y += meson_osd_afbcd.o +meson-drm-y += meson_osd_afbcd.o meson_rdma.o
obj-$(CONFIG_DRM_MESON) += meson-drm.o obj-$(CONFIG_DRM_MESON_DW_HDMI) += meson_dw_hdmi.o diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c index 0f31e70bb94f..2200d8b5252e 100644 --- a/drivers/gpu/drm/meson/meson_drv.c +++ b/drivers/gpu/drm/meson/meson_drv.c @@ -33,6 +33,7 @@ #include "meson_venc_cvbs.h" #include "meson_viu.h" #include "meson_vpp.h" +#include "meson_rdma.h"
#define DRIVER_NAME "meson" #define DRIVER_DESC "Amlogic Meson DRM driver" @@ -295,8 +296,11 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) meson_venc_init(priv); meson_vpp_init(priv); meson_viu_init(priv); - if (priv->afbcd.ops) - priv->afbcd.ops->init(priv); + if (priv->afbcd.ops) { + ret = priv->afbcd.ops->init(priv); + if (ret) + return ret; + }
/* Encoder Initialization */
@@ -367,12 +371,16 @@ static void meson_drv_unbind(struct device *dev) meson_canvas_free(priv->canvas, priv->canvas_id_vd1_2); }
+ if (priv->afbcd.ops) { + priv->afbcd.ops->reset(priv); + meson_rdma_free(priv); + } + drm_dev_unregister(drm); drm_irq_uninstall(drm); drm_kms_helper_poll_fini(drm); drm_mode_config_cleanup(drm); drm_dev_put(drm); - }
static const struct component_master_ops meson_drv_master_ops = { diff --git a/drivers/gpu/drm/meson/meson_drv.h b/drivers/gpu/drm/meson/meson_drv.h index de25349be8aa..9995d74c5ded 100644 --- a/drivers/gpu/drm/meson/meson_drv.h +++ b/drivers/gpu/drm/meson/meson_drv.h @@ -139,6 +139,12 @@ struct meson_drm { u64 modifier; u32 format; } afbcd; + + struct { + dma_addr_t addr_phys; + uint32_t *addr; + unsigned int offset; + } rdma; };
static inline int meson_vpu_is_compatible(struct meson_drm *priv, diff --git a/drivers/gpu/drm/meson/meson_rdma.c b/drivers/gpu/drm/meson/meson_rdma.c new file mode 100644 index 000000000000..4ef5e402d5ca --- /dev/null +++ b/drivers/gpu/drm/meson/meson_rdma.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 BayLibre, SAS + * Author: Neil Armstrong narmstrong@baylibre.com + */ + +#include <linux/bitfield.h> +#include <linux/dma-mapping.h> + +#include "meson_drv.h" +#include "meson_registers.h" +#include "meson_rdma.h" + +/* + * The VPU embeds a "Register DMA" that can write a sequence of registers + * on the VPU AHB bus, either manually or triggered by an internal IRQ + * event like VSYNC or a line input counter. + * The initial implementation handles a single channel (over 8), triggered + * by the VSYNC irq and does not handle the RDMA irq. + */ + +#define RDMA_DESC_SIZE (sizeof(uint32_t) * 2) + +int meson_rdma_init(struct meson_drm *priv) +{ + /* Allocate a 4k buffer */ + priv->rdma.addr = dma_alloc_coherent(priv->dev, SZ_4K, + &priv->rdma.addr_phys, + GFP_KERNEL); + if (!priv->rdma.addr) + return -ENOMEM; + + priv->rdma.offset = 0; + + writel_relaxed(RDMA_CTRL_SW_RESET, + priv->io_base + _REG(RDMA_CTRL)); + writel_relaxed(RDMA_DEFAULT_CONFIG | + FIELD_PREP(RDMA_CTRL_AHB_WR_BURST, 3) | + FIELD_PREP(RDMA_CTRL_AHB_RD_BURST, 0), + priv->io_base + _REG(RDMA_CTRL)); + + return 0; +} + +void meson_rdma_free(struct meson_drm *priv) +{ + if (!priv->rdma.addr && !priv->rdma.addr_phys) + return; + + meson_rdma_stop(priv); + + dma_free_coherent(priv->dev, SZ_4K, + priv->rdma.addr, priv->rdma.addr_phys); + + priv->rdma.addr = NULL; + priv->rdma.addr_phys = (dma_addr_t)NULL; +} + +void meson_rdma_setup(struct meson_drm *priv) +{ + /* Channel 1: Write Flag, No Address Increment */ + writel_bits_relaxed(RDMA_ACCESS_RW_FLAG_CHAN1 | + RDMA_ACCESS_ADDR_INC_CHAN1, + RDMA_ACCESS_RW_FLAG_CHAN1, + priv->io_base + _REG(RDMA_ACCESS_AUTO)); +} + +void meson_rdma_stop(struct meson_drm *priv) +{ + writel_bits_relaxed(RDMA_IRQ_CLEAR_CHAN1, + RDMA_IRQ_CLEAR_CHAN1, + priv->io_base + _REG(RDMA_CTRL)); + + /* Stop Channel 1 */ + writel_bits_relaxed(RDMA_ACCESS_TRIGGER_CHAN1, + FIELD_PREP(RDMA_ACCESS_ADDR_INC_CHAN1, + RDMA_ACCESS_TRIGGER_STOP), + priv->io_base + _REG(RDMA_ACCESS_AUTO)); +} + +void meson_rdma_reset(struct meson_drm *priv) +{ + meson_rdma_stop(priv); + + priv->rdma.offset = 0; +} + +static void meson_rdma_writel(struct meson_drm *priv, uint32_t val, + uint32_t reg) +{ + if (priv->rdma.offset >= (SZ_4K / RDMA_DESC_SIZE)) { + dev_warn_once(priv->dev, "%s: overflow\n", __func__); + return; + } + + priv->rdma.addr[priv->rdma.offset++] = reg; + priv->rdma.addr[priv->rdma.offset++] = val; +} + +/* + * This will add the register to the RDMA buffer and write it to the + * hardware at the same time. + * When meson_rdma_flush is called, the RDMA will replay the register + * writes in order. + */ +void meson_rdma_writel_sync(struct meson_drm *priv, uint32_t val, uint32_t reg) +{ + meson_rdma_writel(priv, val, reg); + + writel_relaxed(val, priv->io_base + _REG(reg)); +} + +void meson_rdma_flush(struct meson_drm *priv) +{ + meson_rdma_stop(priv); + + /* Start of Channel 1 register writes buffer */ + writel(priv->rdma.addr_phys, + priv->io_base + _REG(RDMA_AHB_START_ADDR_1)); + + /* Last byte on Channel 1 register writes buffer */ + writel(priv->rdma.addr_phys + (priv->rdma.offset * RDMA_DESC_SIZE) - 1, + priv->io_base + _REG(RDMA_AHB_END_ADDR_1)); + + /* Trigger Channel 1 on VSYNC event */ + writel_bits_relaxed(RDMA_ACCESS_TRIGGER_CHAN1, + FIELD_PREP(RDMA_ACCESS_TRIGGER_CHAN1, + RDMA_ACCESS_TRIGGER_VSYNC), + priv->io_base + _REG(RDMA_ACCESS_AUTO)); + + priv->rdma.offset = 0; +} diff --git a/drivers/gpu/drm/meson/meson_rdma.h b/drivers/gpu/drm/meson/meson_rdma.h new file mode 100644 index 000000000000..3870bff7b47f --- /dev/null +++ b/drivers/gpu/drm/meson/meson_rdma.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 BayLibre, SAS + * Author: Neil Armstrong narmstrong@baylibre.com + */ + +#ifndef __MESON_RDMA_H +#define __MESON_RDMA_H + +#include "meson_drv.h" + +int meson_rdma_init(struct meson_drm *priv); +void meson_rdma_free(struct meson_drm *priv); +void meson_rdma_setup(struct meson_drm *priv); +void meson_rdma_reset(struct meson_drm *priv); +void meson_rdma_stop(struct meson_drm *priv); + +void meson_rdma_writel_sync(struct meson_drm *priv, uint32_t val, uint32_t reg); +void meson_rdma_flush(struct meson_drm *priv); + +#endif /* __MESON_RDMA_H */
The VPU embeds a "Register DMA" that can write a sequence of registers on the VPU AHB bus, either manually or triggered by an internal IRQ event like VSYNC or a line input counter.
The RDMA is used here to reset and program the AFBC decoder unit on each vsync without involving the interrupt handler that can be masked for a long period of time, producing display glitches.
For this we use the meson_rdma_writel_sync() which adds the register write tuple (VPU register offset and register value) to the RDMA buffer and write the value to the HW.
When enabled, the RDMA is enabled to rewritte the same sequence at the next VSYNC event, until a new buffer is committed to the OSD plane.
The the Amlogic G12A is switched to RDMA, the Amlogic GXM Decoder doesn't need a reset/reprogram at each vsync.
Signed-off-by: Neil Armstrong narmstrong@baylibre.com --- drivers/gpu/drm/meson/meson_crtc.c | 27 ++----- drivers/gpu/drm/meson/meson_osd_afbcd.c | 100 ++++++++++++++---------- 2 files changed, 64 insertions(+), 63 deletions(-)
diff --git a/drivers/gpu/drm/meson/meson_crtc.c b/drivers/gpu/drm/meson/meson_crtc.c index d28efd0dbf11..8e0cf03e45eb 100644 --- a/drivers/gpu/drm/meson/meson_crtc.c +++ b/drivers/gpu/drm/meson/meson_crtc.c @@ -23,6 +23,7 @@ #include "meson_registers.h" #include "meson_venc.h" #include "meson_viu.h" +#include "meson_rdma.h" #include "meson_vpp.h" #include "meson_osd_afbcd.h"
@@ -39,8 +40,6 @@ struct meson_crtc { void (*enable_osd1_afbc)(struct meson_drm *priv); void (*disable_osd1_afbc)(struct meson_drm *priv); unsigned int viu_offset; - bool vsync_forced; - bool vsync_disabled; }; #define to_meson_crtc(x) container_of(x, struct meson_crtc, base)
@@ -51,7 +50,6 @@ static int meson_crtc_enable_vblank(struct drm_crtc *crtc) struct meson_crtc *meson_crtc = to_meson_crtc(crtc); struct meson_drm *priv = meson_crtc->priv;
- meson_crtc->vsync_disabled = false; meson_venc_enable_vsync(priv);
return 0; @@ -62,10 +60,7 @@ static void meson_crtc_disable_vblank(struct drm_crtc *crtc) struct meson_crtc *meson_crtc = to_meson_crtc(crtc); struct meson_drm *priv = meson_crtc->priv;
- if (!meson_crtc->vsync_forced) { - meson_crtc->vsync_disabled = true; - meson_venc_disable_vsync(priv); - } + meson_venc_disable_vsync(priv); }
static const struct drm_crtc_funcs meson_crtc_funcs = { @@ -368,10 +363,11 @@ void meson_crtc_irq(struct meson_drm *priv) if (meson_crtc->enable_osd1) meson_crtc->enable_osd1(priv);
- if (priv->viu.osd1_afbcd) - meson_crtc->vsync_forced = true; - else - meson_crtc->vsync_forced = false; + if (priv->viu.osd1_afbcd) { + priv->afbcd.ops->reset(priv); + priv->afbcd.ops->setup(priv); + priv->afbcd.ops->enable(priv); + }
priv->viu.osd1_commit = false; } @@ -595,15 +591,6 @@ void meson_crtc_irq(struct meson_drm *priv) priv->viu.vd1_commit = false; }
- if (meson_crtc->vsync_forced && priv->viu.osd1_afbcd) { - priv->afbcd.ops->reset(priv); - priv->afbcd.ops->setup(priv); - priv->afbcd.ops->enable(priv); - } - - if (meson_crtc->vsync_disabled) - return; - drm_crtc_handle_vblank(priv->crtc);
spin_lock_irqsave(&priv->drm->event_lock, flags); diff --git a/drivers/gpu/drm/meson/meson_osd_afbcd.c b/drivers/gpu/drm/meson/meson_osd_afbcd.c index aae4341bedaf..f12e0271f166 100644 --- a/drivers/gpu/drm/meson/meson_osd_afbcd.c +++ b/drivers/gpu/drm/meson/meson_osd_afbcd.c @@ -12,6 +12,7 @@ #include "meson_drv.h" #include "meson_registers.h" #include "meson_viu.h" +#include "meson_rdma.h" #include "meson_osd_afbcd.h"
/* @@ -270,6 +271,14 @@ static bool meson_g12a_afbcd_supported_fmt(u64 modifier, uint32_t format)
static int meson_g12a_afbcd_init(struct meson_drm *priv) { + int ret; + + ret = meson_rdma_init(priv); + if (ret) + return ret; + + meson_rdma_setup(priv); + /* Handle AFBC Decoder reset manually */ writel_bits_relaxed(MALI_AFBCD_MANUAL_RESET, MALI_AFBCD_MANUAL_RESET, priv->io_base + _REG(MALI_AFBCD_TOP_CTRL)); @@ -279,27 +288,32 @@ static int meson_g12a_afbcd_init(struct meson_drm *priv)
static int meson_g12a_afbcd_reset(struct meson_drm *priv) { - writel_relaxed(VIU_SW_RESET_G12A_AFBC_ARB | - VIU_SW_RESET_G12A_OSD1_AFBCD, - priv->io_base + _REG(VIU_SW_RESET)); - writel_relaxed(0, priv->io_base + _REG(VIU_SW_RESET)); + meson_rdma_reset(priv); + + meson_rdma_writel_sync(priv, VIU_SW_RESET_G12A_AFBC_ARB | + VIU_SW_RESET_G12A_OSD1_AFBCD, + VIU_SW_RESET); + meson_rdma_writel_sync(priv, 0, VIU_SW_RESET);
return 0; }
static int meson_g12a_afbcd_enable(struct meson_drm *priv) { - writel_relaxed(VPU_MAFBC_IRQ_SURFACES_COMPLETED | - VPU_MAFBC_IRQ_CONFIGURATION_SWAPPED | - VPU_MAFBC_IRQ_DECODE_ERROR | - VPU_MAFBC_IRQ_DETILING_ERROR, - priv->io_base + _REG(VPU_MAFBC_IRQ_MASK)); + meson_rdma_writel_sync(priv, VPU_MAFBC_IRQ_SURFACES_COMPLETED | + VPU_MAFBC_IRQ_CONFIGURATION_SWAPPED | + VPU_MAFBC_IRQ_DECODE_ERROR | + VPU_MAFBC_IRQ_DETILING_ERROR, + VPU_MAFBC_IRQ_MASK);
- writel_bits_relaxed(VPU_MAFBC_S0_ENABLE, VPU_MAFBC_S0_ENABLE, - priv->io_base + _REG(VPU_MAFBC_SURFACE_CFG)); + meson_rdma_writel_sync(priv, VPU_MAFBC_S0_ENABLE, + VPU_MAFBC_SURFACE_CFG); + + meson_rdma_writel_sync(priv, VPU_MAFBC_DIRECT_SWAP, + VPU_MAFBC_COMMAND);
- writel_relaxed(VPU_MAFBC_DIRECT_SWAP, - priv->io_base + _REG(VPU_MAFBC_COMMAND)); + /* This will enable the RDMA replaying the register writes on vsync */ + meson_rdma_flush(priv);
return 0; } @@ -330,36 +344,36 @@ static int meson_g12a_afbcd_setup(struct meson_drm *priv) AFBC_FORMAT_MOD_BLOCK_SIZE_32x8) format |= FIELD_PREP(VPU_MAFBC_SUPER_BLOCK_ASPECT, 1);
- writel_relaxed(format, - priv->io_base + _REG(VPU_MAFBC_FORMAT_SPECIFIER_S0)); - - writel_relaxed(priv->viu.osd1_addr, - priv->io_base + _REG(VPU_MAFBC_HEADER_BUF_ADDR_LOW_S0)); - writel_relaxed(0, - priv->io_base + _REG(VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S0)); - - writel_relaxed(priv->viu.osd1_width, - priv->io_base + _REG(VPU_MAFBC_BUFFER_WIDTH_S0)); - writel_relaxed(ALIGN(priv->viu.osd1_height, 32), - priv->io_base + _REG(VPU_MAFBC_BUFFER_HEIGHT_S0)); - - writel_relaxed(0, - priv->io_base + _REG(VPU_MAFBC_BOUNDING_BOX_X_START_S0)); - writel_relaxed(priv->viu.osd1_width - 1, - priv->io_base + _REG(VPU_MAFBC_BOUNDING_BOX_X_END_S0)); - writel_relaxed(0, - priv->io_base + _REG(VPU_MAFBC_BOUNDING_BOX_Y_START_S0)); - writel_relaxed(priv->viu.osd1_height - 1, - priv->io_base + _REG(VPU_MAFBC_BOUNDING_BOX_Y_END_S0)); - - writel_relaxed(MESON_G12A_AFBCD_OUT_ADDR, - priv->io_base + _REG(VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S0)); - writel_relaxed(0, - priv->io_base + _REG(VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S0)); - - writel_relaxed(priv->viu.osd1_width * - (meson_g12a_afbcd_bpp(priv->afbcd.format) / 8), - priv->io_base + _REG(VPU_MAFBC_OUTPUT_BUF_STRIDE_S0)); + meson_rdma_writel_sync(priv, format, + VPU_MAFBC_FORMAT_SPECIFIER_S0); + + meson_rdma_writel_sync(priv, priv->viu.osd1_addr, + VPU_MAFBC_HEADER_BUF_ADDR_LOW_S0); + meson_rdma_writel_sync(priv, 0, + VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S0); + + meson_rdma_writel_sync(priv, priv->viu.osd1_width, + VPU_MAFBC_BUFFER_WIDTH_S0); + meson_rdma_writel_sync(priv, ALIGN(priv->viu.osd1_height, 32), + VPU_MAFBC_BUFFER_HEIGHT_S0); + + meson_rdma_writel_sync(priv, 0, + VPU_MAFBC_BOUNDING_BOX_X_START_S0); + meson_rdma_writel_sync(priv, priv->viu.osd1_width - 1, + VPU_MAFBC_BOUNDING_BOX_X_END_S0); + meson_rdma_writel_sync(priv, 0, + VPU_MAFBC_BOUNDING_BOX_Y_START_S0); + meson_rdma_writel_sync(priv, priv->viu.osd1_height - 1, + VPU_MAFBC_BOUNDING_BOX_Y_END_S0); + + meson_rdma_writel_sync(priv, MESON_G12A_AFBCD_OUT_ADDR, + VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S0); + meson_rdma_writel_sync(priv, 0, + VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S0); + + meson_rdma_writel_sync(priv, priv->viu.osd1_width * + (meson_g12a_afbcd_bpp(priv->afbcd.format) / 8), + VPU_MAFBC_OUTPUT_BUF_STRIDE_S0);
return 0; }
Neil Armstrong narmstrong@baylibre.com writes:
The VPU embeds a "Register DMA" that can write a sequence of registers on the VPU AHB bus, either manually or triggered by an internal IRQ event like VSYNC or a line input counter.
The initial implementation handles a single channel (over 8), triggered by the VSYNC irq and does not handle the RDMA irq.
The RDMA will be usefull to reset and program the AFBC decoder unit on each vsync without involving the interrupt handler that can be masked for a long period of time, producing display glitches.
For this we use the meson_rdma_writel_sync() which adds the register write tuple (VPU register offset and register value) to the RDMA buffer and write the value to the HW.
When enabled, the RDMA is enabled to rewritte the same sequence at the next VSYNC event, until a new buffer is committed to the OSD plane.
The the Amlogic G12A is switched to RDMA, the Amlogic GXM Decoder doesn't need a reset/reprogram at each vsync.
Changes since v1 at [1]:
- Fixed a regression when AFBC was not used, adding a reset() call for the afbc module
- Added a define for the RDMA descriptor size
- Fixed overflow detection
Reviewed-by: Kevin Hilman khilman@baylibre.com
dri-devel@lists.freedesktop.org
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Kevin Hilman -
Neil Armstrong