This patch enables a QHD HDMI monitor to work at native resolution. Tested on a Sapphire board with RK3399 connected to a Q27q-10 monitor at 2560x1440@60

Messages like dwhdmi-rockchip ff940000.hdmi: PHY configuration failed (clock 148501000) and like dwhdmi-rockchip ff940000.hdmi: PHY configuration failed (clock 241501000) were present and still are because of vop_crtc_mode_fixup in drivers/gpu/drm/rockchip/rockchip_drm_vop.c but this time the display ends up working fine, just after an extra delay of a few seconds.

Changes since v2: Just add the strictly required frequency for backwards compatibility.

Changes since v1: Use alternative clock rounding code proposed by Doug Anderson

Signed-off-by: Vicente Bergas vicencb@gmail.com --- drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 6 ++++++ 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index 23de359a1..e1515d55b 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -148,6 +148,10 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { { 0x214c, 0x0003}, { 0x4064, 0x0003} }, + }, { + 241500000, { + { 0x0040, 0x0003}, + }, }, { ~0UL, { { 0x00a0, 0x000a }, @@ -173,6 +177,8 @@ static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = { 146250000, { 0x0038, 0x0038, 0x0038 }, }, { 148500000, { 0x0000, 0x0038, 0x0038 }, + }, { + 241500000, { 0x0000, }, }, { ~0UL, { 0x0000, 0x0000, 0x0000}, }