DAL has a concept of storing the graphics object ids in a special small struct, and adding type safety to them.
I'm starting to contemplate bringing some pieces of DAL into the mainline modesetting code (like the bios parser for a start), and I think this is the best first step in that direction.
This series converts connectors, encoders and crtcs id to the DAL objects. I haven't done PLLs yet they are a bit messier and I probably need to think about them a bit more.
Also DAL doesn't support any of the DVO/external encoders, I've no idea if they even exist on DCE8 or newer GPUs, so I've done a separate patch to drop them.
Dave.
From: Dave Airlie airlied@redhat.com
This isn't being used so drop it.
Signed-off-by: Dave Airlie airlied@redhat.com --- drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 15 --------------- 1 file changed, 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c index 84b0ce3..3b469ea 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c @@ -234,16 +234,6 @@ amdgpu_atombios_get_hpd_info_from_gpio(struct amdgpu_device *adev, return hpd; }
-static bool amdgpu_atombios_apply_quirks(struct amdgpu_device *adev, - uint32_t supported_device, - int *connector_type, - struct amdgpu_i2c_bus_rec *i2c_bus, - uint16_t *line_mux, - struct amdgpu_hpd *hpd) -{ - return true; -} - static const int object_connector_convert[] = { DRM_MODE_CONNECTOR_Unknown, DRM_MODE_CONNECTOR_DVII, @@ -514,11 +504,6 @@ bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *
conn_id = le16_to_cpu(path->usConnObjectId);
- if (!amdgpu_atombios_apply_quirks - (adev, le16_to_cpu(path->usDeviceTag), &connector_type, - &ddc_bus, &conn_id, &hpd)) - continue; - amdgpu_display_add_connector(adev, conn_id, le16_to_cpu(path->usDeviceTag),
From: Dave Airlie airlied@redhat.com
DAL has a graphics object id we should re-use this in the mainline driver, and wrap around it for now.
This patch introduces the core of the grph functionality ported from DAL.
Signed-off-by: Dave Airlie airlied@redhat.com --- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 2 + .../gpu/drm/amd/include/display_grph_object_id.h | 318 +++++++++++++++++++++ 2 files changed, 320 insertions(+) create mode 100644 drivers/gpu/drm/amd/include/display_grph_object_id.h
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 8d432e6..4b80978 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -40,6 +40,8 @@ #include <linux/i2c.h> #include <linux/i2c-algo-bit.h>
+#include "display_grph_object_id.h" + struct amdgpu_bo; struct amdgpu_device; struct amdgpu_encoder; diff --git a/drivers/gpu/drm/amd/include/display_grph_object_id.h b/drivers/gpu/drm/amd/include/display_grph_object_id.h new file mode 100644 index 0000000..2bb8642 --- /dev/null +++ b/drivers/gpu/drm/amd/include/display_grph_object_id.h @@ -0,0 +1,318 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DISPLAY_GRPH_OBJECT_ID_H__ +#define __DISPLAY_GRPH_OBJECT_ID_H__ + +/* Types of graphics objects */ +enum object_type { + OBJECT_TYPE_UNKNOWN = 0, + + /* Direct ATOM BIOS translation */ + OBJECT_TYPE_GPU, + OBJECT_TYPE_ENCODER, + OBJECT_TYPE_CONNECTOR, + OBJECT_TYPE_ROUTER, + OBJECT_TYPE_GENERIC, + + /* Driver specific */ + OBJECT_TYPE_AUDIO, + OBJECT_TYPE_CONTROLLER, + OBJECT_TYPE_CLOCK_SOURCE, + OBJECT_TYPE_ENGINE, + + OBJECT_TYPE_COUNT +}; + +/* Enumeration inside one type of graphics objects */ +enum object_enum_id { + ENUM_ID_UNKNOWN = 0, + ENUM_ID_1, + ENUM_ID_2, + ENUM_ID_3, + ENUM_ID_4, + ENUM_ID_5, + ENUM_ID_6, + ENUM_ID_7, + + ENUM_ID_COUNT +}; + +/* Generic object ids */ +enum generic_id { + GENERIC_ID_UNKNOWN = 0, + GENERIC_ID_MXM_OPM, + GENERIC_ID_GLSYNC, + GENERIC_ID_STEREO, + + GENERIC_ID_COUNT +}; + +/* Controller object ids */ +enum controller_id { + CONTROLLER_ID_UNDEFINED = 0, + CONTROLLER_ID_D0, + CONTROLLER_ID_D1, + CONTROLLER_ID_D2, + CONTROLLER_ID_D3, + CONTROLLER_ID_D4, + CONTROLLER_ID_D5, + CONTROLLER_ID_UNDERLAY0, + CONTROLLER_ID_MAX = CONTROLLER_ID_UNDERLAY0 +}; + +#define IS_UNDERLAY_CONTROLLER(ctrlr_id) (ctrlr_id >= CONTROLLER_ID_UNDERLAY0) + +/* + * ClockSource object ids. + * We maintain the order matching (more or less) ATOM BIOS + * to improve optimized acquire + */ +enum clock_source_id { + CLOCK_SOURCE_ID_UNDEFINED = 0, + CLOCK_SOURCE_ID_PLL0, + CLOCK_SOURCE_ID_PLL1, + CLOCK_SOURCE_ID_PLL2, + CLOCK_SOURCE_ID_EXTERNAL, /* ID (Phy) ref. clk. for DP */ + CLOCK_SOURCE_ID_DCPLL, + CLOCK_SOURCE_ID_DFS, /* DENTIST */ + CLOCK_SOURCE_ID_VCE, /* VCE does not need a real PLL */ + /* Used to distinguish between programming pixel clock and ID (Phy) clock */ + CLOCK_SOURCE_ID_DP_DTO, + + CLOCK_SOURCE_COMBO_PHY_PLL0, /*combo PHY PLL defines (DC 11.2 and up)*/ + CLOCK_SOURCE_COMBO_PHY_PLL1, + CLOCK_SOURCE_COMBO_PHY_PLL2, + CLOCK_SOURCE_COMBO_PHY_PLL3, + CLOCK_SOURCE_COMBO_PHY_PLL4, + CLOCK_SOURCE_COMBO_PHY_PLL5, + CLOCK_SOURCE_COMBO_DISPLAY_PLL0 +}; + +/* Encoder object ids */ +enum encoder_id { + ENCODER_ID_UNKNOWN = 0, + + /* Radeon Class Display Hardware */ + ENCODER_ID_INTERNAL_LVDS, + ENCODER_ID_INTERNAL_TMDS1, + ENCODER_ID_INTERNAL_TMDS2, + ENCODER_ID_INTERNAL_DAC1, + ENCODER_ID_INTERNAL_DAC2, /* TV/CV DAC */ + + /* External Third Party Encoders */ + ENCODER_ID_INTERNAL_LVTM1, /* not used for Radeon */ + ENCODER_ID_INTERNAL_HDMI, + + /* Kaledisope (KLDSCP) Class Display Hardware */ + ENCODER_ID_INTERNAL_KLDSCP_TMDS1, + ENCODER_ID_INTERNAL_KLDSCP_DAC1, + ENCODER_ID_INTERNAL_KLDSCP_DAC2, /* Shared with CV/TV and CRT */ + /* External TMDS (dual link) */ + ENCODER_ID_EXTERNAL_MVPU_FPGA, /* MVPU FPGA chip */ + ENCODER_ID_INTERNAL_DDI, + ENCODER_ID_INTERNAL_UNIPHY, + ENCODER_ID_INTERNAL_KLDSCP_LVTMA, + ENCODER_ID_INTERNAL_UNIPHY1, + ENCODER_ID_INTERNAL_UNIPHY2, + ENCODER_ID_EXTERNAL_NUTMEG, + ENCODER_ID_EXTERNAL_TRAVIS, + + ENCODER_ID_INTERNAL_WIRELESS, /* Internal wireless display encoder */ + ENCODER_ID_INTERNAL_UNIPHY3, + ENCODER_ID_INTERNAL_VIRTUAL, +}; + +/* Connector object ids */ +enum connector_id { + CONNECTOR_ID_UNKNOWN = 0, + CONNECTOR_ID_SINGLE_LINK_DVII = 1, + CONNECTOR_ID_DUAL_LINK_DVII = 2, + CONNECTOR_ID_SINGLE_LINK_DVID = 3, + CONNECTOR_ID_DUAL_LINK_DVID = 4, + CONNECTOR_ID_VGA = 5, + CONNECTOR_ID_HDMI_TYPE_A = 12, + CONNECTOR_ID_LVDS = 14, + CONNECTOR_ID_PCIE = 16, + CONNECTOR_ID_HARDCODE_DVI = 18, + CONNECTOR_ID_DISPLAY_PORT = 19, + CONNECTOR_ID_EDP = 20, + CONNECTOR_ID_MXM = 21, + CONNECTOR_ID_WIRELESS = 22, + CONNECTOR_ID_MIRACAST = 23, + + CONNECTOR_ID_VIRTUAL = 100 +}; + + +/* Audio object ids */ +enum audio_id { + AUDIO_ID_UNKNOWN = 0, + AUDIO_ID_INTERNAL_AZALIA +}; + + +/* Engine object ids */ +enum engine_id { + ENGINE_ID_DIGA, + ENGINE_ID_DIGB, + ENGINE_ID_DIGC, + ENGINE_ID_DIGD, + ENGINE_ID_DIGE, + ENGINE_ID_DIGF, + ENGINE_ID_DIGG, + ENGINE_ID_DACA, + ENGINE_ID_DACB, + ENGINE_ID_VCE, /* wireless display pseudo-encoder */ + ENGINE_ID_VIRTUAL, + + ENGINE_ID_COUNT, + ENGINE_ID_UNKNOWN = (-1L) +}; + +union supported_stream_engines { + struct { + uint32_t ENGINE_ID_DIGA:1; + uint32_t ENGINE_ID_DIGB:1; + uint32_t ENGINE_ID_DIGC:1; + uint32_t ENGINE_ID_DIGD:1; + uint32_t ENGINE_ID_DIGE:1; + uint32_t ENGINE_ID_DIGF:1; + uint32_t ENGINE_ID_DIGG:1; + uint32_t ENGINE_ID_DACA:1; + uint32_t ENGINE_ID_DACB:1; + uint32_t ENGINE_ID_VCE:1; + } engine; + uint32_t u_all; +}; + +enum transmitter_color_depth { + TRANSMITTER_COLOR_DEPTH_24 = 0, /* 8 bits */ + TRANSMITTER_COLOR_DEPTH_30, /* 10 bits */ + TRANSMITTER_COLOR_DEPTH_36, /* 12 bits */ + TRANSMITTER_COLOR_DEPTH_48 /* 16 bits */ +}; + +/* + * graphics_object_id struct + * + * graphics_object_id is a very simple struct wrapping 32bit Graphics + * Object identication + * + * This struct should stay very simple + * No dependencies at all (no includes) + * No debug messages or asserts + * No #ifndef and preprocessor directives + * No grow in space (no more data member) + */ + +struct graphics_object_id { + uint32_t id:8; + uint32_t enum_id:4; + uint32_t type:4; + uint32_t reserved:16; /* for padding. total size should be u32 */ +}; + +static inline struct graphics_object_id display_graphics_object_id_init( + uint32_t id, + enum object_enum_id enum_id, + enum object_type type) +{ + struct graphics_object_id result = { + id, enum_id, type, 0 + }; + + return result; +} + +static inline bool display_graphics_object_id_is_equal_unchecked( + struct graphics_object_id id1, + struct graphics_object_id id2) +{ + if (id1.id == id2.id && id1.enum_id == id2.enum_id + && id1.type == id2.type) + return true; + + return false; +} + +static inline enum controller_id display_graphics_object_id_get_controller_id( + struct graphics_object_id id) +{ + if (id.type == OBJECT_TYPE_CONTROLLER) + return id.id; + return CONTROLLER_ID_UNDEFINED; +} + +static inline enum clock_source_id display_graphics_object_id_get_clock_source_id( + struct graphics_object_id id) +{ + if (id.type == OBJECT_TYPE_CLOCK_SOURCE) + return id.id; + return CLOCK_SOURCE_ID_UNDEFINED; +} + +static inline enum encoder_id display_graphics_object_id_get_encoder_id( + struct graphics_object_id id) +{ + if (id.type == OBJECT_TYPE_ENCODER) + return id.id; + return ENCODER_ID_UNKNOWN; +} + +static inline enum connector_id display_graphics_object_id_get_connector_id( + struct graphics_object_id id) +{ + if (id.type == OBJECT_TYPE_CONNECTOR) + return id.id; + return CONNECTOR_ID_UNKNOWN; +} + +static inline enum audio_id display_graphics_object_id_get_audio_id( + struct graphics_object_id id) +{ + if (id.type == OBJECT_TYPE_AUDIO) + return id.id; + return AUDIO_ID_UNKNOWN; +} + +static inline enum engine_id display_graphics_object_id_get_engine_id( + struct graphics_object_id id) +{ + if (id.type == OBJECT_TYPE_ENGINE) + return id.id; + return ENGINE_ID_UNKNOWN; +} + +/* Based on internal data members memory layout */ +static inline uint32_t display_graphics_object_id_to_uint(struct graphics_object_id id) +{ + uint32_t object_id = 0; + + object_id = id.id + (id.enum_id << 0x8) + (id.type << 0xc); + return object_id; +} + +#endif
From: Dave Airlie airlied@redhat.com
DAL hides these inside the bios parser, we need them separate to use here, so copy them over. I'll add more to this as I go.
This also needs the ones to translate objects back that aren't in here currently.
Signed-off-by: Dave Airlie airlied@redhat.com --- drivers/gpu/drm/amd/amdgpu/Makefile | 3 +- .../drm/amd/amdgpu/amdgpu_grph_object_id_helpers.c | 183 +++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 2 + 3 files changed, 187 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_grph_object_id_helpers.c
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index c7fcdce..376d08a 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -23,7 +23,8 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \ amdgpu_pm.o atombios_dp.o amdgpu_afmt.o amdgpu_trace_points.o \ atombios_encoders.o amdgpu_sa.o atombios_i2c.o \ amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \ - amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o + amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \ + amdgpu_grph_object_id_helpers.o
# add asic specific block amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_grph_object_id_helpers.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_grph_object_id_helpers.c new file mode 100644 index 0000000..c916d93 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_grph_object_id_helpers.c @@ -0,0 +1,183 @@ +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "amdgpu.h" +#include "atom.h" +#include "display_grph_object_id.h" + +/* these are taken from AMD's DAL bios parser code */ + +static uint32_t gpu_id_from_bios_object_id(uint32_t bios_object_id) +{ + return (bios_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; +} + +static enum connector_id connector_id_from_bios_object_id(uint32_t bios_object_id) +{ + uint32_t bios_connector_id = gpu_id_from_bios_object_id(bios_object_id); + + enum connector_id id; + + switch (bios_connector_id) { + case CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I: + id = CONNECTOR_ID_SINGLE_LINK_DVII; + break; + case CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I: + id = CONNECTOR_ID_DUAL_LINK_DVII; + break; + case CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D: + id = CONNECTOR_ID_SINGLE_LINK_DVID; + break; + case CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D: + id = CONNECTOR_ID_DUAL_LINK_DVID; + break; + case CONNECTOR_OBJECT_ID_VGA: + id = CONNECTOR_ID_VGA; + break; + case CONNECTOR_OBJECT_ID_HDMI_TYPE_A: + id = CONNECTOR_ID_HDMI_TYPE_A; + break; + case CONNECTOR_OBJECT_ID_LVDS: + id = CONNECTOR_ID_LVDS; + break; + case CONNECTOR_OBJECT_ID_PCIE_CONNECTOR: + id = CONNECTOR_ID_PCIE; + break; + case CONNECTOR_OBJECT_ID_HARDCODE_DVI: + id = CONNECTOR_ID_HARDCODE_DVI; + break; + case CONNECTOR_OBJECT_ID_DISPLAYPORT: + id = CONNECTOR_ID_DISPLAY_PORT; + break; + case CONNECTOR_OBJECT_ID_eDP: + id = CONNECTOR_ID_EDP; + break; + case CONNECTOR_OBJECT_ID_MXM: + id = CONNECTOR_ID_MXM; + break; + default: + id = CONNECTOR_ID_UNKNOWN; + break; + } + + return id; +} + +static enum object_enum_id enum_id_from_bios_object_id(uint32_t bios_object_id) +{ + uint32_t bios_enum_id = + (bios_object_id & ENUM_ID_MASK) >> ENUM_ID_SHIFT; + enum object_enum_id id; + + switch (bios_enum_id) { + case GRAPH_OBJECT_ENUM_ID1: + id = ENUM_ID_1; + break; + case GRAPH_OBJECT_ENUM_ID2: + id = ENUM_ID_2; + break; + case GRAPH_OBJECT_ENUM_ID3: + id = ENUM_ID_3; + break; + case GRAPH_OBJECT_ENUM_ID4: + id = ENUM_ID_4; + break; + case GRAPH_OBJECT_ENUM_ID5: + id = ENUM_ID_5; + break; + case GRAPH_OBJECT_ENUM_ID6: + id = ENUM_ID_6; + break; + case GRAPH_OBJECT_ENUM_ID7: + id = ENUM_ID_7; + break; + default: + id = ENUM_ID_UNKNOWN; + break; + } + + return id; +} + +static enum object_type object_type_from_bios_object_id(uint32_t bios_object_id) +{ + uint32_t bios_object_type = (bios_object_id & OBJECT_TYPE_MASK) + >> OBJECT_TYPE_SHIFT; + enum object_type object_type; + + switch (bios_object_type) { + case GRAPH_OBJECT_TYPE_GPU: + object_type = OBJECT_TYPE_GPU; + break; + case GRAPH_OBJECT_TYPE_ENCODER: + object_type = OBJECT_TYPE_ENCODER; + break; + case GRAPH_OBJECT_TYPE_CONNECTOR: + object_type = OBJECT_TYPE_CONNECTOR; + break; + case GRAPH_OBJECT_TYPE_ROUTER: + object_type = OBJECT_TYPE_ROUTER; + break; + case GRAPH_OBJECT_TYPE_GENERIC: + object_type = OBJECT_TYPE_GENERIC; + break; + default: + object_type = OBJECT_TYPE_UNKNOWN; + break; + } + + return object_type; +} + +static uint32_t id_from_bios_object_id(enum object_type type, + uint32_t bios_object_id) +{ + switch (type) { + case OBJECT_TYPE_CONNECTOR: + return (uint32_t)connector_id_from_bios_object_id(bios_object_id); + default: + return 0; + } +} + +struct graphics_object_id amdgpu_object_id_from_bios_object_id(uint32_t bios_object_id) +{ + enum object_type type; + enum object_enum_id enum_id; + struct graphics_object_id go_id = { 0 }; + + type = object_type_from_bios_object_id(bios_object_id); + if (OBJECT_TYPE_UNKNOWN == type) + return go_id; + + enum_id = enum_id_from_bios_object_id(bios_object_id); + if (ENUM_ID_UNKNOWN == enum_id) + return go_id; + + go_id = display_graphics_object_id_init( + id_from_bios_object_id(type, bios_object_id), enum_id, type); + + return go_id; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 4b80978..adf10c9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -595,4 +595,6 @@ int amdgpu_crtc_page_flip(struct drm_crtc *crtc, uint32_t page_flip_flags); extern const struct drm_mode_config_funcs amdgpu_mode_funcs;
+/* amdgpu_grph_object_id_helpers.c */ +struct graphics_object_id amdgpu_object_id_from_bios_object_id(uint32_t bios_object_id); #endif
Hi Dave,
On 14 April 2016 at 03:56, Dave Airlie airlied@gmail.com wrote:
+static enum connector_id connector_id_from_bios_object_id(uint32_t bios_object_id) +{
uint32_t bios_connector_id = gpu_id_from_bios_object_id(bios_object_id);enum connector_id id;switch (bios_connector_id) {case CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I:id = CONNECTOR_ID_SINGLE_LINK_DVII;break;case CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I:id = CONNECTOR_ID_DUAL_LINK_DVII;break;case CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D:id = CONNECTOR_ID_SINGLE_LINK_DVID;break;case CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D:id = CONNECTOR_ID_DUAL_LINK_DVID;break;case CONNECTOR_OBJECT_ID_VGA:id = CONNECTOR_ID_VGA;break;case CONNECTOR_OBJECT_ID_HDMI_TYPE_A:id = CONNECTOR_ID_HDMI_TYPE_A;break;case CONNECTOR_OBJECT_ID_LVDS:id = CONNECTOR_ID_LVDS;break;case CONNECTOR_OBJECT_ID_PCIE_CONNECTOR:id = CONNECTOR_ID_PCIE;break;case CONNECTOR_OBJECT_ID_HARDCODE_DVI:id = CONNECTOR_ID_HARDCODE_DVI;break;case CONNECTOR_OBJECT_ID_DISPLAYPORT:id = CONNECTOR_ID_DISPLAY_PORT;break;case CONNECTOR_OBJECT_ID_eDP:id = CONNECTOR_ID_EDP;break;case CONNECTOR_OBJECT_ID_MXM:id = CONNECTOR_ID_MXM;break;default:id = CONNECTOR_ID_UNKNOWN;break;
One could move all the new mappings (meaning - here and follow up patches) to static const table(s), saving a wee bit of space ;-)
-Emil
From: Dave Airlie airlied@redhat.com
This introduces graphics objects for the connectors code, and replaces the atombios enums with the graphics object ones.
These correspond currently so we don't really need a back translation pass for them.
Signed-off-by: Dave Airlie airlied@redhat.com --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 22 +++------------ drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 37 +++++++++++++------------- drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.h | 3 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c | 4 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 8 +++--- drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 8 +++--- drivers/gpu/drm/amd/amdgpu/atombios_encoders.c | 10 +++---- 8 files changed, 37 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index a7a53ac..0e54f4a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -2204,7 +2204,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) #define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base)) #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos)) #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c)) -#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r)) +#define amdgpu_display_add_connector(adev, coi, sd, ct, ib, h, r) (adev)->mode_info.funcs->add_connector((adev), (coi), (sd), (ct), (ib), (h), (r)) #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s)) #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s)) #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c index 3b469ea..5f236d9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c @@ -273,7 +273,7 @@ bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device * ATOM_OBJECT_HEADER *obj_header; int i, j, k, path_size, device_support; int connector_type; - u16 conn_id, connector_object_id; + struct graphics_object_id connector_object_id; struct amdgpu_i2c_bus_rec ddc_bus; struct amdgpu_router router; struct amdgpu_gpio_rec gpio; @@ -309,21 +309,10 @@ bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device * path_size += le16_to_cpu(path->usSize);
if (device_support & le16_to_cpu(path->usDeviceTag)) { - uint8_t con_obj_id, con_obj_num, con_obj_type; - - con_obj_id = - (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK) - >> OBJECT_ID_SHIFT; - con_obj_num = - (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK) - >> ENUM_ID_SHIFT; - con_obj_type = - (le16_to_cpu(path->usConnObjectId) & - OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; + connector_object_id = amdgpu_object_id_from_bios_object_id(path->usConnObjectId);
connector_type = - object_connector_convert[con_obj_id]; - connector_object_id = con_obj_id; + object_connector_convert[connector_object_id.id];
if (connector_type == DRM_MODE_CONNECTOR_Unknown) continue; @@ -502,13 +491,10 @@ bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device * /* needed for aux chan transactions */ ddc_bus.hpd = hpd.hpd;
- conn_id = le16_to_cpu(path->usConnObjectId); - amdgpu_display_add_connector(adev, - conn_id, + connector_object_id, le16_to_cpu(path->usDeviceTag), connector_type, &ddc_bus, - connector_object_id, &hpd, &router);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index 60a0c9a..765309e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -61,7 +61,7 @@ void amdgpu_connector_hotplug(struct drm_connector *connector) amdgpu_connector->con_priv;
/* if existing sink type was not DP no need to retrain */ - if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) + if (dig_connector->dp_sink_type != CONNECTOR_ID_DISPLAY_PORT) return;
/* first get sink type as it may be reset after (un)plug */ @@ -69,7 +69,7 @@ void amdgpu_connector_hotplug(struct drm_connector *connector) /* don't do anything if sink is not display port, i.e., * passive dp->(dvi|hdmi) adaptor */ - if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { + if (dig_connector->dp_sink_type == CONNECTOR_ID_DISPLAY_PORT) { int saved_dpms = connector->dpms; /* Only turn off the display if it's physically disconnected */ if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { @@ -128,8 +128,8 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) break; case DRM_MODE_CONNECTOR_DisplayPort: dig_connector = amdgpu_connector->con_priv; - if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || - (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) || + if ((dig_connector->dp_sink_type == CONNECTOR_ID_DISPLAY_PORT) || + (dig_connector->dp_sink_type == CONNECTOR_ID_EDP) || drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { if (connector->display_info.bpc) bpc = connector->display_info.bpc; @@ -321,8 +321,8 @@ static void amdgpu_connector_get_edid(struct drm_connector *connector) (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv;
- if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || - dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && + if ((dig->dp_sink_type == CONNECTOR_ID_DISPLAY_PORT || + dig->dp_sink_type == CONNECTOR_ID_EDP) && amdgpu_connector->ddc_bus->has_aux) amdgpu_connector->edid = drm_get_edid(connector, &amdgpu_connector->ddc_bus->aux.ddc); @@ -1168,9 +1168,9 @@ static int amdgpu_connector_dvi_mode_valid(struct drm_connector *connector, /* XXX check mode bandwidth */
if (amdgpu_connector->use_digital && (mode->clock > 165000)) { - if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) || - (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) || - (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) { + enum connector_id conn_obj_id = display_graphics_object_id_get_connector_id(amdgpu_connector->connector_object_id); + if ((conn_obj_id == CONNECTOR_ID_DUAL_LINK_DVII) || + (conn_obj_id == CONNECTOR_ID_DUAL_LINK_DVID)) { return MODE_OK; } else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { /* HDMI 1.3+ supports max clock of 340 Mhz */ @@ -1373,7 +1373,7 @@ amdgpu_connector_dp_detect(struct drm_connector *connector, bool force) ret = connector_status_connected; } /* eDP is always DP */ - amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; + amdgpu_dig_connector->dp_sink_type = CONNECTOR_ID_DISPLAY_PORT; if (!amdgpu_dig_connector->edp_on) amdgpu_atombios_encoder_set_edp_panel_power(connector, ATOM_TRANSMITTER_ACTION_POWER_ON); @@ -1385,7 +1385,7 @@ amdgpu_connector_dp_detect(struct drm_connector *connector, bool force) } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != ENCODER_OBJECT_ID_NONE) { /* DP bridges are always DP */ - amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; + amdgpu_dig_connector->dp_sink_type = CONNECTOR_ID_DISPLAY_PORT; /* get the DPCD from the bridge */ amdgpu_atombios_dp_get_dpcd(amdgpu_connector);
@@ -1405,10 +1405,10 @@ amdgpu_connector_dp_detect(struct drm_connector *connector, bool force) amdgpu_atombios_dp_get_sinktype(amdgpu_connector); if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { ret = connector_status_connected; - if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) + if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_ID_DISPLAY_PORT) amdgpu_atombios_dp_get_dpcd(amdgpu_connector); } else { - if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { + if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_ID_DISPLAY_PORT) { if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) ret = connector_status_connected; } else { @@ -1462,8 +1462,8 @@ static int amdgpu_connector_dp_mode_valid(struct drm_connector *connector, } return MODE_OK; } else { - if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || - (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { + if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_ID_DISPLAY_PORT) || + (amdgpu_dig_connector->dp_sink_type == CONNECTOR_ID_EDP)) { return amdgpu_atombios_dp_mode_valid_helper(connector, mode); } else { if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { @@ -1506,11 +1506,11 @@ static const struct drm_connector_funcs amdgpu_connector_edp_funcs = {
void amdgpu_connector_add(struct amdgpu_device *adev, - uint32_t connector_id, + struct graphics_object_id connector_object_id, uint32_t supported_device, int connector_type, struct amdgpu_i2c_bus_rec *i2c_bus, - uint16_t connector_object_id, + struct amdgpu_hpd *hpd, struct amdgpu_router *router) { @@ -1531,7 +1531,7 @@ amdgpu_connector_add(struct amdgpu_device *adev, /* see if we already added it */ list_for_each_entry(connector, &dev->mode_config.connector_list, head) { amdgpu_connector = to_amdgpu_connector(connector); - if (amdgpu_connector->connector_id == connector_id) { + if (display_graphics_object_id_is_equal_unchecked(amdgpu_connector->connector_object_id, connector_object_id)) { amdgpu_connector->devices |= supported_device; return; } @@ -1569,7 +1569,6 @@ amdgpu_connector_add(struct amdgpu_device *adev,
connector = &amdgpu_connector->base;
- amdgpu_connector->connector_id = connector_id; amdgpu_connector->devices = supported_device; amdgpu_connector->shared_ddc = shared_ddc; amdgpu_connector->connector_object_id = connector_object_id; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.h index 61fcef1..70b2663 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.h @@ -31,11 +31,10 @@ u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *conn bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector); void amdgpu_connector_add(struct amdgpu_device *adev, - uint32_t connector_id, + struct graphics_object_id connector_object_id, uint32_t supported_device, int connector_type, struct amdgpu_i2c_bus_rec *i2c_bus, - uint16_t connector_object_id, struct amdgpu_hpd *hpd, struct amdgpu_router *router);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c index 94138ab..574e9cb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c @@ -222,8 +222,8 @@ bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder, case DRM_MODE_CONNECTOR_HDMIA: case DRM_MODE_CONNECTOR_DisplayPort: dig_connector = amdgpu_connector->con_priv; - if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || - (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) + if ((dig_connector->dp_sink_type == CONNECTOR_ID_DISPLAY_PORT) || + (dig_connector->dp_sink_type == CONNECTOR_ID_EDP)) return false; else { /* HDMI 1.3 supports up to 340 Mhz over single link */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index adf10c9..33284c8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -294,11 +294,10 @@ struct amdgpu_display_funcs { uint32_t supported_device, u16 caps); void (*add_connector)(struct amdgpu_device *adev, - uint32_t connector_id, + struct graphics_object_id connector_object_id, uint32_t supported_device, int connector_type, struct amdgpu_i2c_bus_rec *i2c_bus, - uint16_t connector_object_id, struct amdgpu_hpd *hpd, struct amdgpu_router *router); void (*stop_mc_access)(struct amdgpu_device *adev, @@ -453,10 +452,10 @@ struct amdgpu_encoder { struct amdgpu_connector_atom_dig { /* displayport */ u8 dpcd[DP_RECEIVER_CAP_SIZE]; - u8 dp_sink_type; int dp_clock; int dp_lane_count; bool edp_on; + enum connector_id dp_sink_type; };
struct amdgpu_gpio_rec { @@ -502,7 +501,7 @@ enum amdgpu_connector_dither {
struct amdgpu_connector { struct drm_connector base; - uint32_t connector_id; + struct graphics_object_id connector_object_id; uint32_t devices; struct amdgpu_i2c_chan *ddc_bus; /* some systems have an hdmi and vga port with a shared ddc line */ @@ -514,7 +513,6 @@ struct amdgpu_connector { void *con_priv; bool dac_load_detect; bool detected_by_load; /* if the connection status was determined by load */ - uint16_t connector_object_id; struct amdgpu_hpd hpd; struct amdgpu_router router; struct amdgpu_i2c_chan *router_bus; diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c index bf731e9..29d698b 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c @@ -408,8 +408,8 @@ void amdgpu_atombios_dp_set_link_config(struct drm_connector *connector, return; dig_connector = amdgpu_connector->con_priv;
- if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || - (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { + if ((dig_connector->dp_sink_type == CONNECTOR_ID_DISPLAY_PORT) || + (dig_connector->dp_sink_type == CONNECTOR_ID_EDP)) { ret = amdgpu_atombios_dp_get_dp_link_config(connector, dig_connector->dpcd, mode->clock, &dig_connector->dp_lane_count, @@ -730,8 +730,8 @@ void amdgpu_atombios_dp_link_train(struct drm_encoder *encoder, return; dig_connector = amdgpu_connector->con_priv;
- if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) && - (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP)) + if ((dig_connector->dp_sink_type != CONNECTOR_ID_DISPLAY_PORT) && + (dig_connector->dp_sink_type != CONNECTOR_ID_EDP)) return;
if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp) diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c index 1e0bba2..4367941 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c @@ -503,8 +503,8 @@ int amdgpu_atombios_encoder_get_encoder_mode(struct drm_encoder *encoder) break; case DRM_MODE_CONNECTOR_DisplayPort: dig_connector = amdgpu_connector->con_priv; - if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || - (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { + if ((dig_connector->dp_sink_type == CONNECTOR_ID_DISPLAY_PORT) || + (dig_connector->dp_sink_type == CONNECTOR_ID_EDP)) { return ATOM_ENCODER_MODE_DP; } else if (amdgpu_audio != 0) { if (amdgpu_connector->audio == AMDGPU_AUDIO_ENABLE) @@ -750,8 +750,7 @@ amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder *encoder, int a hpd_id = amdgpu_connector->hpd.hpd; dp_clock = dig_connector->dp_clock; dp_lane_count = dig_connector->dp_lane_count; - connector_object_id = - (amdgpu_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; + connector_object_id = display_graphics_object_id_get_connector_id(amdgpu_connector->connector_object_id); }
if (encoder->crtc) { @@ -1156,8 +1155,7 @@ amdgpu_atombios_encoder_setup_external_encoder(struct drm_encoder *encoder,
dp_clock = dig_connector->dp_clock; dp_lane_count = dig_connector->dp_lane_count; - connector_object_id = - (amdgpu_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; + connector_object_id = display_graphics_object_id_get_connector_id(amdgpu_connector->connector_object_id); }
memset(&args, 0, sizeof(args));
From: Dave Airlie airlied@redhat.com
I'm a bit confused whether this is needed so it would be good to confirm if hw shipped with it.
DAL as currently is doesn't have any support for this, it doesn't have any encoder ids for DVO that I can see.
So before porting to DAL graphics objects, I'm removing this code, so we can see if any regressions land here.
Signed-off-by: Dave Airlie airlied@redhat.com --- drivers/gpu/drm/amd/amdgpu/atombios_crtc.c | 3 - drivers/gpu/drm/amd/amdgpu/atombios_encoders.c | 100 ------------------------- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 8 -- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 8 -- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 8 -- 5 files changed, 127 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c index 49aa350..072a729 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c @@ -344,9 +344,6 @@ static u32 amdgpu_atombios_crtc_adjust_pll(struct drm_crtc *crtc, } }
- /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ - if (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) - adjusted_clock = mode->clock * 2; if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) amdgpu_crtc->pll_flags |= AMDGPU_PLL_PREFER_CLOSEST_LOWER; if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c index 4367941..7ef93c6 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c @@ -272,7 +272,6 @@ bool amdgpu_atombios_encoder_is_digital(struct drm_encoder *encoder) { struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); switch (amdgpu_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: @@ -369,79 +368,8 @@ static u8 amdgpu_atombios_encoder_get_bpc(struct drm_encoder *encoder) } }
-union dvo_encoder_control { - ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds; - DVO_ENCODER_CONTROL_PS_ALLOCATION dvo; - DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3; - DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4; -}; - -static void -amdgpu_atombios_encoder_setup_dvo(struct drm_encoder *encoder, int action) -{ - struct drm_device *dev = encoder->dev; - struct amdgpu_device *adev = dev->dev_private; - struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); - union dvo_encoder_control args; - int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); - uint8_t frev, crev; - - memset(&args, 0, sizeof(args)); - - if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) - return; - - switch (frev) { - case 1: - switch (crev) { - case 1: - /* R4xx, R5xx */ - args.ext_tmds.sXTmdsEncoder.ucEnable = action; - - if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock)) - args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL; - - args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB; - break; - case 2: - /* RS600/690/740 */ - args.dvo.sDVOEncoder.ucAction = action; - args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10); - /* DFP1, CRT1, TV1 depending on the type of port */ - args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX; - - if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock)) - args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL; - break; - case 3: - /* R6xx */ - args.dvo_v3.ucAction = action; - args.dvo_v3.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10); - args.dvo_v3.ucDVOConfig = 0; /* XXX */ - break; - case 4: - /* DCE8 */ - args.dvo_v4.ucAction = action; - args.dvo_v4.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10); - args.dvo_v4.ucDVOConfig = 0; /* XXX */ - args.dvo_v4.ucBitPerColor = amdgpu_atombios_encoder_get_bpc(encoder); - break; - default: - DRM_ERROR("Unknown table version %d, %d\n", frev, crev); - break; - } - break; - default: - DRM_ERROR("Unknown table version %d, %d\n", frev, crev); - break; - } - - amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); -} - int amdgpu_atombios_encoder_get_encoder_mode(struct drm_encoder *encoder) { - struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct drm_connector *connector; struct amdgpu_connector *amdgpu_connector; struct amdgpu_connector_atom_dig *dig_connector; @@ -450,11 +378,6 @@ int amdgpu_atombios_encoder_get_encoder_mode(struct drm_encoder *encoder) if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) return ATOM_ENCODER_MODE_DP;
- /* DVO is always DVO */ - if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) || - (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)) - return ATOM_ENCODER_MODE_DVO; - connector = amdgpu_get_connector_for_encoder(encoder); /* if we don't have an active device yet, just use one of * the connectors tied to the encoder. @@ -768,9 +691,6 @@ amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder *encoder, int a memset(&args, 0, sizeof(args));
switch (amdgpu_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: - index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); - break; case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: @@ -1332,18 +1252,6 @@ amdgpu_atombios_encoder_dpms(struct drm_encoder *encoder, int mode) break; } break; - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: - switch (mode) { - case DRM_MODE_DPMS_ON: - amdgpu_atombios_encoder_setup_dvo(encoder, ATOM_ENABLE); - break; - case DRM_MODE_DPMS_STANDBY: - case DRM_MODE_DPMS_SUSPEND: - case DRM_MODE_DPMS_OFF: - amdgpu_atombios_encoder_setup_dvo(encoder, ATOM_DISABLE); - break; - } - break; case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: switch (mode) { case DRM_MODE_DPMS_ON: @@ -1402,9 +1310,7 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder) else args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; break; - case ENCODER_OBJECT_ID_INTERNAL_DVO1: case ENCODER_OBJECT_ID_INTERNAL_DDI: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; break; case ENCODER_OBJECT_ID_INTERNAL_DAC1: @@ -1474,9 +1380,6 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder) break; } break; - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: - args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; - break; case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; @@ -1543,9 +1446,6 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder) break; } break; - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: - args.v3.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; - break; case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) args.v3.ucEncoderID = ASIC_INT_TV_ENCODER_ID; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 6de2ce53..90dc73b 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -3733,7 +3733,6 @@ static void dce_v10_0_encoder_add(struct amdgpu_device *adev, DRM_MODE_ENCODER_DAC, NULL); drm_encoder_helper_add(encoder, &dce_v10_0_dac_helper_funcs); break; - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: @@ -3754,13 +3753,6 @@ static void dce_v10_0_encoder_add(struct amdgpu_device *adev, } drm_encoder_helper_add(encoder, &dce_v10_0_dig_helper_funcs); break; - case ENCODER_OBJECT_ID_SI170B: - case ENCODER_OBJECT_ID_CH7303: - case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: - case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: - case ENCODER_OBJECT_ID_TITFP513: - case ENCODER_OBJECT_ID_VT1623: - case ENCODER_OBJECT_ID_HDMI_SI1930: case ENCODER_OBJECT_ID_TRAVIS: case ENCODER_OBJECT_ID_NUTMEG: /* these are handled by the primary encoders */ diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index 89aab0a..d3c9fb7 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -3674,7 +3674,6 @@ static void dce_v11_0_encoder_add(struct amdgpu_device *adev, DRM_MODE_ENCODER_DAC, NULL); drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs); break; - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: @@ -3695,13 +3694,6 @@ static void dce_v11_0_encoder_add(struct amdgpu_device *adev, } drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs); break; - case ENCODER_OBJECT_ID_SI170B: - case ENCODER_OBJECT_ID_CH7303: - case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: - case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: - case ENCODER_OBJECT_ID_TITFP513: - case ENCODER_OBJECT_ID_VT1623: - case ENCODER_OBJECT_ID_HDMI_SI1930: case ENCODER_OBJECT_ID_TRAVIS: case ENCODER_OBJECT_ID_NUTMEG: /* these are handled by the primary encoders */ diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index e56b55d..ddb8eba 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -3663,7 +3663,6 @@ static void dce_v8_0_encoder_add(struct amdgpu_device *adev, DRM_MODE_ENCODER_DAC, NULL); drm_encoder_helper_add(encoder, &dce_v8_0_dac_helper_funcs); break; - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: @@ -3684,13 +3683,6 @@ static void dce_v8_0_encoder_add(struct amdgpu_device *adev, } drm_encoder_helper_add(encoder, &dce_v8_0_dig_helper_funcs); break; - case ENCODER_OBJECT_ID_SI170B: - case ENCODER_OBJECT_ID_CH7303: - case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: - case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: - case ENCODER_OBJECT_ID_TITFP513: - case ENCODER_OBJECT_ID_VT1623: - case ENCODER_OBJECT_ID_HDMI_SI1930: case ENCODER_OBJECT_ID_TRAVIS: case ENCODER_OBJECT_ID_NUTMEG: /* these are handled by the primary encoders */
DVO was mainly used for crossfire pre-DCE 8, and possibly on some DCE 8 (Tonga) SKUs as well. On newer ASICs crossfire uses XDMA so there's no longer a need for DVO.
It's probably safe to drop it for amdgpu. Radeon driver might still want to keep it if there's support for it.
Harry
On 2016-04-13 10:56 PM, Dave Airlie wrote:
From: Dave Airlie airlied@redhat.com
I'm a bit confused whether this is needed so it would be good to confirm if hw shipped with it.
DAL as currently is doesn't have any support for this, it doesn't have any encoder ids for DVO that I can see.
So before porting to DAL graphics objects, I'm removing this code, so we can see if any regressions land here.
Signed-off-by: Dave Airlie airlied@redhat.com
drivers/gpu/drm/amd/amdgpu/atombios_crtc.c | 3 - drivers/gpu/drm/amd/amdgpu/atombios_encoders.c | 100 ------------------------- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 8 -- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 8 -- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 8 -- 5 files changed, 127 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c index 49aa350..072a729 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c @@ -344,9 +344,6 @@ static u32 amdgpu_atombios_crtc_adjust_pll(struct drm_crtc *crtc, } }
- /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
- if (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
adjusted_clock = mode->clock * 2;diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c index 4367941..7ef93c6 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c @@ -272,7 +272,6 @@ bool amdgpu_atombios_encoder_is_digital(struct drm_encoder *encoder) { struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); switch (amdgpu_encoder->encoder_id) {
- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
@@ -369,79 +368,8 @@ static u8 amdgpu_atombios_encoder_get_bpc(struct drm_encoder *encoder) } }
-union dvo_encoder_control {
- ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
- DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
- DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
- DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4;
-};
-static void -amdgpu_atombios_encoder_setup_dvo(struct drm_encoder *encoder, int action) -{
- struct drm_device *dev = encoder->dev;
- struct amdgpu_device *adev = dev->dev_private;
- struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
- union dvo_encoder_control args;
- int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
- uint8_t frev, crev;
- memset(&args, 0, sizeof(args));
- if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))
return;- switch (frev) {
- case 1:
switch (crev) {case 1:/* R4xx, R5xx */args.ext_tmds.sXTmdsEncoder.ucEnable = action;if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock))args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;break;case 2:/* RS600/690/740 */args.dvo.sDVOEncoder.ucAction = action;args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);/* DFP1, CRT1, TV1 depending on the type of port */args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;if (amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock))args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;break;case 3:/* R6xx */args.dvo_v3.ucAction = action;args.dvo_v3.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);args.dvo_v3.ucDVOConfig = 0; /* XXX */break;case 4:/* DCE8 */args.dvo_v4.ucAction = action;args.dvo_v4.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);args.dvo_v4.ucDVOConfig = 0; /* XXX */args.dvo_v4.ucBitPerColor = amdgpu_atombios_encoder_get_bpc(encoder);break;default:DRM_ERROR("Unknown table version %d, %d\n", frev, crev);break;}break;- default:
DRM_ERROR("Unknown table version %d, %d\n", frev, crev);break;- }
- amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
-}
- int amdgpu_atombios_encoder_get_encoder_mode(struct drm_encoder *encoder) {
- struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct drm_connector *connector; struct amdgpu_connector *amdgpu_connector; struct amdgpu_connector_atom_dig *dig_connector;
@@ -450,11 +378,6 @@ int amdgpu_atombios_encoder_get_encoder_mode(struct drm_encoder *encoder) if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) return ATOM_ENCODER_MODE_DP;
- /* DVO is always DVO */
- if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
(amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))return ATOM_ENCODER_MODE_DVO;- connector = amdgpu_get_connector_for_encoder(encoder); /* if we don't have an active device yet, just use one of
- the connectors tied to the encoder.
@@ -768,9 +691,6 @@ amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder *encoder, int a memset(&args, 0, sizeof(args));
switch (amdgpu_encoder->encoder_id) {
- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);break;@@ -1332,18 +1252,6 @@ amdgpu_atombios_encoder_dpms(struct drm_encoder *encoder, int mode) break; } break;
- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
switch (mode) {case DRM_MODE_DPMS_ON:amdgpu_atombios_encoder_setup_dvo(encoder, ATOM_ENABLE);break;case DRM_MODE_DPMS_STANDBY:case DRM_MODE_DPMS_SUSPEND:case DRM_MODE_DPMS_OFF:amdgpu_atombios_encoder_setup_dvo(encoder, ATOM_DISABLE);break;}break;@@ -1402,9 +1310,7 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder) else args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; break;
case ENCODER_OBJECT_ID_INTERNAL_DVO1: case ENCODER_OBJECT_ID_INTERNAL_DDI:case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; break; case ENCODER_OBJECT_ID_INTERNAL_DAC1:@@ -1474,9 +1380,6 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder) break; } break;
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;break; case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;@@ -1543,9 +1446,6 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder) break; } break;
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:args.v3.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;break; case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) args.v3.ucEncoderID = ASIC_INT_TV_ENCODER_ID;diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 6de2ce53..90dc73b 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -3733,7 +3733,6 @@ static void dce_v10_0_encoder_add(struct amdgpu_device *adev, DRM_MODE_ENCODER_DAC, NULL); drm_encoder_helper_add(encoder, &dce_v10_0_dac_helper_funcs); break;
- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
@@ -3754,13 +3753,6 @@ static void dce_v10_0_encoder_add(struct amdgpu_device *adev, } drm_encoder_helper_add(encoder, &dce_v10_0_dig_helper_funcs); break;
- case ENCODER_OBJECT_ID_SI170B:
- case ENCODER_OBJECT_ID_CH7303:
- case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
- case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
- case ENCODER_OBJECT_ID_TITFP513:
- case ENCODER_OBJECT_ID_VT1623:
- case ENCODER_OBJECT_ID_HDMI_SI1930: case ENCODER_OBJECT_ID_TRAVIS: case ENCODER_OBJECT_ID_NUTMEG: /* these are handled by the primary encoders */
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index 89aab0a..d3c9fb7 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -3674,7 +3674,6 @@ static void dce_v11_0_encoder_add(struct amdgpu_device *adev, DRM_MODE_ENCODER_DAC, NULL); drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs); break;
- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
@@ -3695,13 +3694,6 @@ static void dce_v11_0_encoder_add(struct amdgpu_device *adev, } drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs); break;
- case ENCODER_OBJECT_ID_SI170B:
- case ENCODER_OBJECT_ID_CH7303:
- case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
- case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
- case ENCODER_OBJECT_ID_TITFP513:
- case ENCODER_OBJECT_ID_VT1623:
- case ENCODER_OBJECT_ID_HDMI_SI1930: case ENCODER_OBJECT_ID_TRAVIS: case ENCODER_OBJECT_ID_NUTMEG: /* these are handled by the primary encoders */
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index e56b55d..ddb8eba 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -3663,7 +3663,6 @@ static void dce_v8_0_encoder_add(struct amdgpu_device *adev, DRM_MODE_ENCODER_DAC, NULL); drm_encoder_helper_add(encoder, &dce_v8_0_dac_helper_funcs); break;
- case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
@@ -3684,13 +3683,6 @@ static void dce_v8_0_encoder_add(struct amdgpu_device *adev, } drm_encoder_helper_add(encoder, &dce_v8_0_dig_helper_funcs); break;
- case ENCODER_OBJECT_ID_SI170B:
- case ENCODER_OBJECT_ID_CH7303:
- case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
- case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
- case ENCODER_OBJECT_ID_TITFP513:
- case ENCODER_OBJECT_ID_VT1623:
- case ENCODER_OBJECT_ID_HDMI_SI1930: case ENCODER_OBJECT_ID_TRAVIS: case ENCODER_OBJECT_ID_NUTMEG: /* these are handled by the primary encoders */
From: Dave Airlie airlied@redhat.com
This ports the encoder code over to the common graphics objects from DAL.
Note the encoders id don't match 1:1 between atombios and the graphics objects.
Signed-off-by: Dave Airlie airlied@redhat.com --- drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 5 +- drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 30 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 46 ++--- drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c | 14 +- .../drm/amd/amdgpu/amdgpu_grph_object_id_helpers.c | 129 ++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 7 +- drivers/gpu/drm/amd/amdgpu/atombios_crtc.c | 26 +-- drivers/gpu/drm/amd/amdgpu/atombios_crtc.h | 2 +- drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 8 +- drivers/gpu/drm/amd/amdgpu/atombios_encoders.c | 228 ++++++++++++--------- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 57 +++--- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 54 ++--- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 54 ++--- .../gpu/drm/amd/include/display_grph_object_id.h | 1 + 15 files changed, 409 insertions(+), 254 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c index 5f236d9..e8855a3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c @@ -341,7 +341,8 @@ bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device * le16_to_cpu(enc_obj->asObjects[k].usRecordOffset)); ATOM_ENCODER_CAP_RECORD *cap_record; u16 caps = 0; - + struct graphics_object_id encoder_object_id; + encoder_object_id = amdgpu_object_id_from_bios_object_id(encoder_obj); while (record->ucRecordSize > 0 && record->ucRecordType > 0 && record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { @@ -355,7 +356,7 @@ bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device * record = (ATOM_COMMON_RECORD_HEADER *) ((char *)record + record->ucRecordSize); } - amdgpu_display_add_encoder(adev, encoder_obj, + amdgpu_display_add_encoder(adev, encoder_object_id, le16_to_cpu(path->usDeviceTag), caps); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index 765309e..eb9b9dc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -313,7 +313,7 @@ static void amdgpu_connector_get_edid(struct drm_connector *connector) amdgpu_i2c_router_select_ddc_port(amdgpu_connector);
if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != - ENCODER_OBJECT_ID_NONE) && + ENCODER_ID_UNKNOWN) && amdgpu_connector->ddc_bus->has_aux) { amdgpu_connector->edid = drm_get_edid(connector, &amdgpu_connector->ddc_bus->aux.ddc); @@ -1228,7 +1228,7 @@ static int amdgpu_connector_dp_get_modes(struct drm_connector *connector) } else { /* need to setup ddc on the bridge */ if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != - ENCODER_OBJECT_ID_NONE) { + ENCODER_ID_UNKNOWN) { if (encoder) amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); } @@ -1262,7 +1262,7 @@ static int amdgpu_connector_dp_get_modes(struct drm_connector *connector) } else { /* need to setup ddc on the bridge */ if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != - ENCODER_OBJECT_ID_NONE) { + ENCODER_ID_UNKNOWN) { if (encoder) amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); } @@ -1275,11 +1275,12 @@ static int amdgpu_connector_dp_get_modes(struct drm_connector *connector) return ret; }
-u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector) +enum encoder_id amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector) { struct drm_encoder *encoder; struct amdgpu_encoder *amdgpu_encoder; int i; + enum encoder_id enc_id;
for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { if (connector->encoder_ids[i] == 0) @@ -1291,17 +1292,17 @@ u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *conn continue;
amdgpu_encoder = to_amdgpu_encoder(encoder); - - switch (amdgpu_encoder->encoder_id) { - case ENCODER_OBJECT_ID_TRAVIS: - case ENCODER_OBJECT_ID_NUTMEG: - return amdgpu_encoder->encoder_id; + enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id); + switch (enc_id) { + case ENCODER_ID_EXTERNAL_TRAVIS: + case ENCODER_ID_EXTERNAL_NUTMEG: + return enc_id; default: break; } }
- return ENCODER_OBJECT_ID_NONE; + return ENCODER_ID_UNKNOWN; }
static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector) @@ -1383,7 +1384,7 @@ amdgpu_connector_dp_detect(struct drm_connector *connector, bool force) amdgpu_atombios_encoder_set_edp_panel_power(connector, ATOM_TRANSMITTER_ACTION_POWER_OFF); } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != - ENCODER_OBJECT_ID_NONE) { + ENCODER_ID_UNKNOWN) { /* DP bridges are always DP */ amdgpu_dig_connector->dp_sink_type = CONNECTOR_ID_DISPLAY_PORT; /* get the DPCD from the bridge */ @@ -1552,9 +1553,10 @@ amdgpu_connector_add(struct amdgpu_device *adev, list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { amdgpu_encoder = to_amdgpu_encoder(encoder); if (amdgpu_encoder->devices & supported_device) { - switch (amdgpu_encoder->encoder_id) { - case ENCODER_OBJECT_ID_TRAVIS: - case ENCODER_OBJECT_ID_NUTMEG: + enum encoder_id enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id); + switch (enc_id) { + case ENCODER_ID_EXTERNAL_TRAVIS: + case ENCODER_ID_EXTERNAL_NUTMEG: is_dp_bridge = true; break; default: diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.h index 70b2663..f062101 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.h @@ -27,7 +27,7 @@ struct edid *amdgpu_connector_edid(struct drm_connector *connector); void amdgpu_connector_hotplug(struct drm_connector *connector); int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector); -u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector); +enum encoder_id amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector); bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector); void amdgpu_connector_add(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index c835abe..448b211 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -341,38 +341,22 @@ static const char *encoder_names[38] = { "INTERNAL_TMDS2", "INTERNAL_DAC1", "INTERNAL_DAC2", - "INTERNAL_SDVOA", - "INTERNAL_SDVOB", - "SI170B", - "CH7303", - "CH7301", - "INTERNAL_DVO1", - "EXTERNAL_SDVOA", - "EXTERNAL_SDVOB", - "TITFP513", "INTERNAL_LVTM1", - "VT1623", - "HDMI_SI1930", - "HDMI_INTERNAL", + "INTERNAL_HDMI", "INTERNAL_KLDSCP_TMDS1", - "INTERNAL_KLDSCP_DVO1", "INTERNAL_KLDSCP_DAC1", "INTERNAL_KLDSCP_DAC2", - "SI178", "MVPU_FPGA", "INTERNAL_DDI", - "VT1625", - "HDMI_SI1932", - "DP_AN9801", - "DP_DP501", "INTERNAL_UNIPHY", "INTERNAL_KLDSCP_LVTMA", "INTERNAL_UNIPHY1", "INTERNAL_UNIPHY2", "NUTMEG", "TRAVIS", - "INTERNAL_VCE", + "INTERNAL_WIRELESS", "INTERNAL_UNIPHY3", + "INTERNAL_VIRTUAL", };
static const char *hpd_names[6] = { @@ -429,31 +413,33 @@ void amdgpu_print_display_setup(struct drm_device *dev) } DRM_INFO(" Encoders:\n"); list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { + enum encoder_id enc_id; amdgpu_encoder = to_amdgpu_encoder(encoder); devices = amdgpu_encoder->devices & amdgpu_connector->devices; + enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id); if (devices) { if (devices & ATOM_DEVICE_CRT1_SUPPORT) - DRM_INFO(" CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); + DRM_INFO(" CRT1: %s\n", encoder_names[enc_id]); if (devices & ATOM_DEVICE_CRT2_SUPPORT) - DRM_INFO(" CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); + DRM_INFO(" CRT2: %s\n", encoder_names[enc_id]); if (devices & ATOM_DEVICE_LCD1_SUPPORT) - DRM_INFO(" LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); + DRM_INFO(" LCD1: %s\n", encoder_names[enc_id]); if (devices & ATOM_DEVICE_DFP1_SUPPORT) - DRM_INFO(" DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); + DRM_INFO(" DFP1: %s\n", encoder_names[enc_id]); if (devices & ATOM_DEVICE_DFP2_SUPPORT) - DRM_INFO(" DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); + DRM_INFO(" DFP2: %s\n", encoder_names[enc_id]); if (devices & ATOM_DEVICE_DFP3_SUPPORT) - DRM_INFO(" DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]); + DRM_INFO(" DFP3: %s\n", encoder_names[enc_id]); if (devices & ATOM_DEVICE_DFP4_SUPPORT) - DRM_INFO(" DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]); + DRM_INFO(" DFP4: %s\n", encoder_names[enc_id]); if (devices & ATOM_DEVICE_DFP5_SUPPORT) - DRM_INFO(" DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]); + DRM_INFO(" DFP5: %s\n", encoder_names[enc_id]); if (devices & ATOM_DEVICE_DFP6_SUPPORT) - DRM_INFO(" DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]); + DRM_INFO(" DFP6: %s\n", encoder_names[enc_id]); if (devices & ATOM_DEVICE_TV1_SUPPORT) - DRM_INFO(" TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); + DRM_INFO(" TV1: %s\n", encoder_names[enc_id]); if (devices & ATOM_DEVICE_CV_SUPPORT) - DRM_INFO(" CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]); + DRM_INFO(" CV: %s\n", encoder_names[enc_id]); } } i++; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c index 574e9cb..f51e0ee 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c @@ -132,16 +132,16 @@ u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder)
if (other_encoder) { struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(other_encoder); - - switch (amdgpu_encoder->encoder_id) { - case ENCODER_OBJECT_ID_TRAVIS: - case ENCODER_OBJECT_ID_NUTMEG: - return amdgpu_encoder->encoder_id; + uint8_t enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id); + switch (enc_id) { + case ENCODER_ID_EXTERNAL_TRAVIS: + case ENCODER_ID_EXTERNAL_NUTMEG: + return enc_id; default: - return ENCODER_OBJECT_ID_NONE; + return ENCODER_ID_UNKNOWN; } } - return ENCODER_OBJECT_ID_NONE; + return ENCODER_ID_UNKNOWN; }
void amdgpu_panel_mode_fixup(struct drm_encoder *encoder, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_grph_object_id_helpers.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_grph_object_id_helpers.c index c916d93..122dfdb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_grph_object_id_helpers.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_grph_object_id_helpers.c @@ -85,6 +85,77 @@ static enum connector_id connector_id_from_bios_object_id(uint32_t bios_object_i return id; }
+static enum encoder_id encoder_id_from_bios_object_id(uint32_t bios_object_id) +{ + uint32_t bios_encoder_id = gpu_id_from_bios_object_id(bios_object_id); + enum encoder_id id; + + switch (bios_encoder_id) { + case ENCODER_OBJECT_ID_INTERNAL_LVDS: + id = ENCODER_ID_INTERNAL_LVDS; + break; + case ENCODER_OBJECT_ID_INTERNAL_TMDS1: + id = ENCODER_ID_INTERNAL_TMDS1; + break; + case ENCODER_OBJECT_ID_INTERNAL_TMDS2: + id = ENCODER_ID_INTERNAL_TMDS2; + break; + case ENCODER_OBJECT_ID_INTERNAL_DAC1: + id = ENCODER_ID_INTERNAL_DAC1; + break; + case ENCODER_OBJECT_ID_INTERNAL_DAC2: + id = ENCODER_ID_INTERNAL_DAC2; + break; + case ENCODER_OBJECT_ID_INTERNAL_LVTM1: + id = ENCODER_ID_INTERNAL_LVTM1; + break; + case ENCODER_OBJECT_ID_HDMI_INTERNAL: + id = ENCODER_ID_INTERNAL_HDMI; + break; + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: + id = ENCODER_ID_INTERNAL_KLDSCP_TMDS1; + break; + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: + id = ENCODER_ID_INTERNAL_KLDSCP_DAC1; + break; + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: + id = ENCODER_ID_INTERNAL_KLDSCP_DAC2; + break; + case ENCODER_OBJECT_ID_MVPU_FPGA: + id = ENCODER_ID_EXTERNAL_MVPU_FPGA; + break; + case ENCODER_OBJECT_ID_INTERNAL_DDI: + id = ENCODER_ID_INTERNAL_DDI; + break; + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: + id = ENCODER_ID_INTERNAL_UNIPHY; + break; + case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: + id = ENCODER_ID_INTERNAL_KLDSCP_LVTMA; + break; + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: + id = ENCODER_ID_INTERNAL_UNIPHY1; + break; + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: + id = ENCODER_ID_INTERNAL_UNIPHY2; + break; + case ENCODER_OBJECT_ID_ALMOND: /* ENCODER_OBJECT_ID_NUTMEG */ + id = ENCODER_ID_EXTERNAL_NUTMEG; + break; + case ENCODER_OBJECT_ID_TRAVIS: + id = ENCODER_ID_EXTERNAL_TRAVIS; + break; + case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: + id = ENCODER_ID_INTERNAL_UNIPHY3; + break; + default: + id = ENCODER_ID_UNKNOWN; + break; + } + + return id; +} + static enum object_enum_id enum_id_from_bios_object_id(uint32_t bios_object_id) { uint32_t bios_enum_id = @@ -157,6 +228,8 @@ static uint32_t id_from_bios_object_id(enum object_type type, switch (type) { case OBJECT_TYPE_CONNECTOR: return (uint32_t)connector_id_from_bios_object_id(bios_object_id); + case OBJECT_TYPE_ENCODER: + return (uint32_t)encoder_id_from_bios_object_id(bios_object_id); default: return 0; } @@ -181,3 +254,59 @@ struct graphics_object_id amdgpu_object_id_from_bios_object_id(uint32_t bios_obj
return go_id; } + +uint8_t amdgpu_encoder_id_to_atom(enum encoder_id id) +{ + switch (id) { + case ENCODER_ID_INTERNAL_LVDS: + return ENCODER_OBJECT_ID_INTERNAL_LVDS; + case ENCODER_ID_INTERNAL_TMDS1: + return ENCODER_OBJECT_ID_INTERNAL_TMDS1; + case ENCODER_ID_INTERNAL_TMDS2: + return ENCODER_OBJECT_ID_INTERNAL_TMDS2; + case ENCODER_ID_INTERNAL_DAC1: + return ENCODER_OBJECT_ID_INTERNAL_DAC1; + case ENCODER_ID_INTERNAL_DAC2: + return ENCODER_OBJECT_ID_INTERNAL_DAC2; + case ENCODER_ID_INTERNAL_LVTM1: + return ENCODER_OBJECT_ID_INTERNAL_LVTM1; + case ENCODER_ID_INTERNAL_HDMI: + return ENCODER_OBJECT_ID_HDMI_INTERNAL; + case ENCODER_ID_EXTERNAL_TRAVIS: + return ENCODER_OBJECT_ID_TRAVIS; + case ENCODER_ID_EXTERNAL_NUTMEG: + return ENCODER_OBJECT_ID_NUTMEG; + case ENCODER_ID_INTERNAL_KLDSCP_TMDS1: + return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1; + case ENCODER_ID_INTERNAL_KLDSCP_DAC1: + return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1; + case ENCODER_ID_INTERNAL_KLDSCP_DAC2: + return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2; + case ENCODER_ID_EXTERNAL_MVPU_FPGA: + return ENCODER_OBJECT_ID_MVPU_FPGA; + case ENCODER_ID_INTERNAL_DDI: + return ENCODER_OBJECT_ID_INTERNAL_DDI; + case ENCODER_ID_INTERNAL_UNIPHY: + return ENCODER_OBJECT_ID_INTERNAL_UNIPHY; + case ENCODER_ID_INTERNAL_KLDSCP_LVTMA: + return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA; + case ENCODER_ID_INTERNAL_UNIPHY1: + return ENCODER_OBJECT_ID_INTERNAL_UNIPHY1; + case ENCODER_ID_INTERNAL_UNIPHY2: + return ENCODER_OBJECT_ID_INTERNAL_UNIPHY2; + case ENCODER_ID_INTERNAL_UNIPHY3: + return ENCODER_OBJECT_ID_INTERNAL_UNIPHY3; + case ENCODER_ID_INTERNAL_WIRELESS: + return ENCODER_OBJECT_ID_INTERNAL_VCE; + case ENCODER_ID_UNKNOWN: + return ENCODER_OBJECT_ID_NONE; + default: + return ENCODER_OBJECT_ID_NONE; + } +} + +uint8_t amdgpu_encoder_object_to_atom(struct graphics_object_id object_id) +{ + enum encoder_id enc_id = display_graphics_object_id_get_encoder_id(object_id); + return amdgpu_encoder_id_to_atom(enc_id); +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 33284c8..96e1de8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -290,7 +290,7 @@ struct amdgpu_display_funcs { u32 *vbl, u32 *position); /* display topology setup */ void (*add_encoder)(struct amdgpu_device *adev, - uint32_t encoder_enum, + struct graphics_object_id encoder_id, uint32_t supported_device, u16 caps); void (*add_connector)(struct amdgpu_device *adev, @@ -432,8 +432,7 @@ struct amdgpu_encoder_atom_dig {
struct amdgpu_encoder { struct drm_encoder base; - uint32_t encoder_enum; - uint32_t encoder_id; + struct graphics_object_id encoder_object_id; uint32_t devices; uint32_t active_device; uint32_t flags; @@ -595,4 +594,6 @@ extern const struct drm_mode_config_funcs amdgpu_mode_funcs;
/* amdgpu_grph_object_id_helpers.c */ struct graphics_object_id amdgpu_object_id_from_bios_object_id(uint32_t bios_object_id); +uint8_t amdgpu_encoder_object_to_atom(struct graphics_object_id object_id); +uint8_t amdgpu_encoder_id_to_atom(enum encoder_id id); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c index 072a729..5b8d3c6 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c @@ -319,11 +319,11 @@ static u32 amdgpu_atombios_crtc_adjust_pll(struct drm_crtc *crtc, union adjust_pixel_clock args; u8 frev, crev; int index; - + uint8_t atom_enc_id; amdgpu_crtc->pll_flags = AMDGPU_PLL_USE_FRAC_FB_DIV;
if ((amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || - (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) { + (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_ID_UNKNOWN)) { if (connector) { struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); struct amdgpu_connector_atom_dig *dig_connector = @@ -368,6 +368,7 @@ static u32 amdgpu_atombios_crtc_adjust_pll(struct drm_crtc *crtc, } }
+ atom_enc_id = amdgpu_encoder_object_to_atom(amdgpu_encoder->encoder_object_id); /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock * accordingly based on the encoder/transmitter to work around * special hw requirements. @@ -385,7 +386,7 @@ static u32 amdgpu_atombios_crtc_adjust_pll(struct drm_crtc *crtc, case 1: case 2: args.v1.usPixelClock = cpu_to_le16(clock / 10); - args.v1.ucTransmitterID = amdgpu_encoder->encoder_id; + args.v1.ucTransmitterID = atom_enc_id; args.v1.ucEncodeMode = encoder_mode; if (amdgpu_crtc->ss_enabled && amdgpu_crtc->ss.percentage) args.v1.ucConfig |= @@ -397,7 +398,7 @@ static u32 amdgpu_atombios_crtc_adjust_pll(struct drm_crtc *crtc, break; case 3: args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10); - args.v3.sInput.ucTransmitterID = amdgpu_encoder->encoder_id; + args.v3.sInput.ucTransmitterID = atom_enc_id; args.v3.sInput.ucEncodeMode = encoder_mode; args.v3.sInput.ucDispPllConfig = 0; if (amdgpu_crtc->ss_enabled && amdgpu_crtc->ss.percentage) @@ -418,9 +419,9 @@ static u32 amdgpu_atombios_crtc_adjust_pll(struct drm_crtc *crtc, DISPPLL_CONFIG_DUAL_LINK; } if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != - ENCODER_OBJECT_ID_NONE) + ENCODER_ID_UNKNOWN) args.v3.sInput.ucExtTransmitterID = - amdgpu_encoder_get_dp_bridge_encoder_id(encoder); + amdgpu_encoder_id_to_atom(amdgpu_encoder_get_dp_bridge_encoder_id(encoder)); else args.v3.sInput.ucExtTransmitterID = 0;
@@ -523,7 +524,7 @@ void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc, u32 crtc_id, int pll_id, u32 encoder_mode, - u32 encoder_id, + struct graphics_object_id encoder_object_id, u32 clock, u32 ref_div, u32 fb_div, @@ -538,6 +539,7 @@ void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc, u8 frev, crev; int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); union set_pixel_clock args; + uint8_t atom_enc_id = amdgpu_encoder_object_to_atom(encoder_object_id);
memset(&args, 0, sizeof(args));
@@ -583,7 +585,7 @@ void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc, args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1; if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC; - args.v3.ucTransmitterId = encoder_id; + args.v3.ucTransmitterId = atom_enc_id; args.v3.ucEncoderMode = encoder_mode; break; case 5: @@ -613,7 +615,7 @@ void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc, break; } } - args.v5.ucTransmitterID = encoder_id; + args.v5.ucTransmitterID = atom_enc_id; args.v5.ucEncoderMode = encoder_mode; args.v5.ucPpll = pll_id; break; @@ -645,7 +647,7 @@ void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc, break; } } - args.v6.ucTransmitterID = encoder_id; + args.v6.ucTransmitterID = atom_enc_id; args.v6.ucEncoderMode = encoder_mode; args.v6.ucPpll = pll_id; break; @@ -676,7 +678,7 @@ int amdgpu_atombios_crtc_prepare_pll(struct drm_crtc *crtc, amdgpu_crtc->ss_enabled = false;
if ((amdgpu_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || - (amdgpu_encoder_get_dp_bridge_encoder_id(amdgpu_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) { + (amdgpu_encoder_get_dp_bridge_encoder_id(amdgpu_crtc->encoder) != ENCODER_ID_UNKNOWN)) { struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector = amdgpu_get_connector_for_encoder(amdgpu_crtc->encoder); @@ -776,7 +778,7 @@ void amdgpu_atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode amdgpu_crtc->crtc_id, &amdgpu_crtc->ss);
amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, - encoder_mode, amdgpu_encoder->encoder_id, clock, + encoder_mode, amdgpu_encoder->encoder_object_id, clock, ref_div, fb_div, frac_fb_div, post_div, amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss);
diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_crtc.h b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.h index c670833..452245f 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_crtc.h +++ b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.h @@ -41,7 +41,7 @@ void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc, u32 crtc_id, int pll_id, u32 encoder_mode, - u32 encoder_id, + struct graphics_object_id encoder_object_id, u32 clock, u32 ref_div, u32 fb_div, diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c index 29d698b..5296c99 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c @@ -266,7 +266,7 @@ static int amdgpu_atombios_dp_get_dp_link_config(struct drm_connector *connector unsigned lane_num, i, max_pix_clock;
if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) == - ENCODER_OBJECT_ID_NUTMEG) { + ENCODER_ID_EXTERNAL_NUTMEG) { for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) { max_pix_clock = (lane_num * 270000 * 8) / bpp; if (max_pix_clock >= pix_clock) { @@ -373,14 +373,14 @@ int amdgpu_atombios_dp_get_panel_mode(struct drm_encoder *encoder,
dig_connector = amdgpu_connector->con_priv;
- if (dp_bridge != ENCODER_OBJECT_ID_NONE) { + if (dp_bridge != ENCODER_ID_UNKNOWN) { /* DP bridge chips */ if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux, DP_EDP_CONFIGURATION_CAP, &tmp) == 1) { if (tmp & 1) panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; - else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) || - (dp_bridge == ENCODER_OBJECT_ID_TRAVIS)) + else if ((dp_bridge == ENCODER_ID_EXTERNAL_NUTMEG) || + (dp_bridge == ENCODER_ID_EXTERNAL_TRAVIS)) panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; else panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c index 7ef93c6..28d306a 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c @@ -89,15 +89,16 @@ amdgpu_atombios_encoder_set_backlight_level(struct amdgpu_encoder *amdgpu_encode
if ((amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && amdgpu_encoder->enc_priv) { + enum encoder_id enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id); dig = amdgpu_encoder->enc_priv; dig->backlight_level = level; amdgpu_atombios_encoder_set_backlight_level_to_reg(adev, dig->backlight_level);
- switch (amdgpu_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: + switch (enc_id) { + case ENCODER_ID_INTERNAL_UNIPHY: + case ENCODER_ID_INTERNAL_KLDSCP_LVTMA: + case ENCODER_ID_INTERNAL_UNIPHY1: + case ENCODER_ID_INTERNAL_UNIPHY2: if (dig->backlight_level == 0) amdgpu_atombios_encoder_setup_dig_transmitter(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); @@ -271,11 +272,12 @@ void amdgpu_atombios_encoder_fini_backlight(struct amdgpu_encoder *encoder) bool amdgpu_atombios_encoder_is_digital(struct drm_encoder *encoder) { struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); - switch (amdgpu_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: + enum encoder_id enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id); + switch (enc_id) { + case ENCODER_ID_INTERNAL_UNIPHY: + case ENCODER_ID_INTERNAL_UNIPHY1: + case ENCODER_ID_INTERNAL_UNIPHY2: + case ENCODER_ID_INTERNAL_UNIPHY3: return true; default: return false; @@ -304,7 +306,7 @@ bool amdgpu_atombios_encoder_mode_fixup(struct drm_encoder *encoder, amdgpu_panel_mode_fixup(encoder, adjusted_mode);
if ((amdgpu_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || - (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) { + (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_ID_UNKNOWN)) { struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); amdgpu_atombios_dp_set_link_config(connector, adjusted_mode); } @@ -320,18 +322,20 @@ amdgpu_atombios_encoder_setup_dac(struct drm_encoder *encoder, int action) struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); DAC_ENCODER_CONTROL_PS_ALLOCATION args; int index = 0; - + enum encoder_id enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id); memset(&args, 0, sizeof(args));
- switch (amdgpu_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_DAC1: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: + switch (enc_id) { + case ENCODER_ID_INTERNAL_DAC1: + case ENCODER_ID_INTERNAL_KLDSCP_DAC1: index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); break; - case ENCODER_OBJECT_ID_INTERNAL_DAC2: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: + case ENCODER_ID_INTERNAL_DAC2: + case ENCODER_ID_INTERNAL_KLDSCP_DAC2: index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); break; + default: + return; }
args.ucAction = action; @@ -375,7 +379,7 @@ int amdgpu_atombios_encoder_get_encoder_mode(struct drm_encoder *encoder) struct amdgpu_connector_atom_dig *dig_connector;
/* dp bridges are always DP */ - if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) + if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_ID_UNKNOWN) return ATOM_ENCODER_MODE_DP;
connector = amdgpu_get_connector_for_encoder(encoder); @@ -503,6 +507,7 @@ amdgpu_atombios_encoder_setup_dig_encoder(struct drm_encoder *encoder, int dp_clock = 0; int dp_lane_count = 0; int hpd_id = AMDGPU_HPD_NONE; + enum encoder_id enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id);
if (connector) { struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); @@ -543,17 +548,19 @@ amdgpu_atombios_encoder_setup_dig_encoder(struct drm_encoder *encoder,
if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000)) args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; - switch (amdgpu_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: + switch (enc_id) { + case ENCODER_ID_INTERNAL_UNIPHY: args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; break; - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: + case ENCODER_ID_INTERNAL_UNIPHY1: + case ENCODER_ID_INTERNAL_KLDSCP_LVTMA: args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; break; - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: + case ENCODER_ID_INTERNAL_UNIPHY2: args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; break; + default: + break; } if (dig->linkb) args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; @@ -655,6 +662,7 @@ amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder *encoder, int a int igp_lane_info = 0; int dig_encoder = dig->dig_encoder; int hpd_id = AMDGPU_HPD_NONE; + enum encoder_id enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id);
if (action == ATOM_TRANSMITTER_ACTION_INIT) { connector = amdgpu_get_connector_for_encoder_init(encoder); @@ -690,16 +698,18 @@ amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder *encoder, int a
memset(&args, 0, sizeof(args));
- switch (amdgpu_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: + switch (enc_id) { + case ENCODER_ID_INTERNAL_UNIPHY: + case ENCODER_ID_INTERNAL_UNIPHY1: + case ENCODER_ID_INTERNAL_UNIPHY2: + case ENCODER_ID_INTERNAL_UNIPHY3: index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); break; - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: + case ENCODER_ID_INTERNAL_KLDSCP_LVTMA: index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl); break; + default: + return; }
if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) @@ -732,7 +742,7 @@ amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder *encoder, int a args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
if ((adev->flags & AMD_IS_APU) && - (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { + (enc_id == ENCODER_ID_INTERNAL_UNIPHY)) { if (is_dp || !amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock)) { if (igp_lane_info & 0x1) @@ -785,16 +795,18 @@ amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder *encoder, int a if (dig->linkb) args.v2.acConfig.ucLinkSel = 1;
- switch (amdgpu_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: + switch (enc_id) { + case ENCODER_ID_INTERNAL_UNIPHY: args.v2.acConfig.ucTransmitterSel = 0; break; - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: + case ENCODER_ID_INTERNAL_UNIPHY1: args.v2.acConfig.ucTransmitterSel = 1; break; - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: + case ENCODER_ID_INTERNAL_UNIPHY2: args.v2.acConfig.ucTransmitterSel = 2; break; + default: + return; }
if (is_dp) { @@ -845,16 +857,18 @@ amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder *encoder, int a else args.v3.acConfig.ucRefClkSource = pll_id;
- switch (amdgpu_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: + switch (enc_id) { + case ENCODER_ID_INTERNAL_UNIPHY: args.v3.acConfig.ucTransmitterSel = 0; break; - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: + case ENCODER_ID_INTERNAL_UNIPHY1: args.v3.acConfig.ucTransmitterSel = 1; break; - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: + case ENCODER_ID_INTERNAL_UNIPHY2: args.v3.acConfig.ucTransmitterSel = 2; break; + default: + return; }
if (is_dp) @@ -907,16 +921,18 @@ amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder *encoder, int a } else args.v4.acConfig.ucRefClkSource = pll_id;
- switch (amdgpu_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: + switch (enc_id) { + case ENCODER_ID_INTERNAL_UNIPHY: args.v4.acConfig.ucTransmitterSel = 0; break; - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: + case ENCODER_ID_INTERNAL_UNIPHY1: args.v4.acConfig.ucTransmitterSel = 1; break; - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: + case ENCODER_ID_INTERNAL_UNIPHY2: args.v4.acConfig.ucTransmitterSel = 2; break; + default: + return; }
if (is_dp) @@ -935,28 +951,30 @@ amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder *encoder, int a else args.v5.usSymClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10);
- switch (amdgpu_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: + switch (enc_id) { + case ENCODER_ID_INTERNAL_UNIPHY: if (dig->linkb) args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB; else args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA; break; - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: + case ENCODER_ID_INTERNAL_UNIPHY1: if (dig->linkb) args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD; else args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC; break; - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: + case ENCODER_ID_INTERNAL_UNIPHY2: if (dig->linkb) args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF; else args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE; break; - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: + case ENCODER_ID_INTERNAL_UNIPHY3: args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG; break; + default: + return; } if (is_dp) args.v5.ucLaneNum = dp_lane_count; @@ -1061,7 +1079,7 @@ amdgpu_atombios_encoder_setup_external_encoder(struct drm_encoder *encoder, int dp_clock = 0; int dp_lane_count = 0; int connector_object_id = 0; - u32 ext_enum = (ext_amdgpu_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; + enum object_enum_id ext_enum = ext_amdgpu_encoder->encoder_object_id.enum_id;
if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) connector = amdgpu_get_connector_for_encoder_init(encoder); @@ -1125,15 +1143,17 @@ amdgpu_atombios_encoder_setup_external_encoder(struct drm_encoder *encoder, else args.v3.sExtEncoder.ucLaneNum = 4; switch (ext_enum) { - case GRAPH_OBJECT_ENUM_ID1: + case ENUM_ID_1: args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1; break; - case GRAPH_OBJECT_ENUM_ID2: + case ENUM_ID_2: args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2; break; - case GRAPH_OBJECT_ENUM_ID3: + case ENUM_ID_3: args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3; break; + default: + return; } args.v3.sExtEncoder.ucBitPerColor = amdgpu_atombios_encoder_get_bpc(encoder); break; @@ -1232,15 +1252,15 @@ void amdgpu_atombios_encoder_dpms(struct drm_encoder *encoder, int mode) { struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); - + enum encoder_id enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id); DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", - amdgpu_encoder->encoder_id, mode, amdgpu_encoder->devices, + enc_id, mode, amdgpu_encoder->devices, amdgpu_encoder->active_device); - switch (amdgpu_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: + switch (enc_id) { + case ENCODER_ID_INTERNAL_UNIPHY: + case ENCODER_ID_INTERNAL_UNIPHY1: + case ENCODER_ID_INTERNAL_UNIPHY2: + case ENCODER_ID_INTERNAL_UNIPHY3: switch (mode) { case DRM_MODE_DPMS_ON: amdgpu_atombios_encoder_setup_dig(encoder, ATOM_ENABLE); @@ -1252,7 +1272,7 @@ amdgpu_atombios_encoder_dpms(struct drm_encoder *encoder, int mode) break; } break; - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: + case ENCODER_ID_INTERNAL_KLDSCP_DAC1: switch (mode) { case DRM_MODE_DPMS_ON: amdgpu_atombios_encoder_setup_dac(encoder, ATOM_ENABLE); @@ -1286,6 +1306,7 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder) int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); uint8_t frev, crev; struct amdgpu_encoder_atom_dig *dig; + enum encoder_id enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id);
memset(&args, 0, sizeof(args));
@@ -1298,23 +1319,23 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder) case 1: default: args.v1.ucCRTC = amdgpu_crtc->crtc_id; - switch (amdgpu_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_TMDS1: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: + switch (enc_id) { + case ENCODER_ID_INTERNAL_TMDS1: + case ENCODER_ID_INTERNAL_KLDSCP_TMDS1: args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; break; - case ENCODER_OBJECT_ID_INTERNAL_LVDS: - case ENCODER_OBJECT_ID_INTERNAL_LVTM1: + case ENCODER_ID_INTERNAL_LVDS: + case ENCODER_ID_INTERNAL_LVTM1: if (amdgpu_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; else args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; break; - case ENCODER_OBJECT_ID_INTERNAL_DDI: + case ENCODER_ID_INTERNAL_DDI: args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; break; - case ENCODER_OBJECT_ID_INTERNAL_DAC1: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: + case ENCODER_ID_INTERNAL_DAC1: + case ENCODER_ID_INTERNAL_KLDSCP_DAC1: if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; else if (amdgpu_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) @@ -1322,8 +1343,8 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder) else args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; break; - case ENCODER_OBJECT_ID_INTERNAL_DAC2: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: + case ENCODER_ID_INTERNAL_DAC2: + case ENCODER_ID_INTERNAL_KLDSCP_DAC2: if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; else if (amdgpu_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) @@ -1331,11 +1352,13 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder) else args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; break; + default: + return; } break; case 2: args.v2.ucCRTC = amdgpu_crtc->crtc_id; - if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) { + if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_ID_UNKNOWN) { struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) @@ -1349,12 +1372,12 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder) } else { args.v2.ucEncodeMode = amdgpu_atombios_encoder_get_encoder_mode(encoder); } - switch (amdgpu_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: + switch (enc_id) { + case ENCODER_ID_INTERNAL_UNIPHY: + case ENCODER_ID_INTERNAL_UNIPHY1: + case ENCODER_ID_INTERNAL_UNIPHY2: + case ENCODER_ID_INTERNAL_UNIPHY3: + case ENCODER_ID_INTERNAL_KLDSCP_LVTMA: dig = amdgpu_encoder->enc_priv; switch (dig->dig_encoder) { case 0: @@ -1380,7 +1403,7 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder) break; } break; - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: + case ENCODER_ID_INTERNAL_KLDSCP_DAC1: if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; else if (amdgpu_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) @@ -1388,7 +1411,7 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder) else args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; break; - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: + case ENCODER_ID_INTERNAL_KLDSCP_DAC2: if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; else if (amdgpu_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) @@ -1396,11 +1419,13 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder) else args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; break; + default: + return; } break; case 3: args.v3.ucCRTC = amdgpu_crtc->crtc_id; - if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) { + if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_ID_UNKNOWN) { struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) @@ -1415,12 +1440,12 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder) args.v2.ucEncodeMode = amdgpu_atombios_encoder_get_encoder_mode(encoder); } args.v3.ucDstBpc = amdgpu_atombios_encoder_get_bpc(encoder); - switch (amdgpu_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: + switch (enc_id) { + case ENCODER_ID_INTERNAL_UNIPHY: + case ENCODER_ID_INTERNAL_UNIPHY1: + case ENCODER_ID_INTERNAL_UNIPHY2: + case ENCODER_ID_INTERNAL_UNIPHY3: + case ENCODER_ID_INTERNAL_KLDSCP_LVTMA: dig = amdgpu_encoder->enc_priv; switch (dig->dig_encoder) { case 0: @@ -1446,7 +1471,7 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder) break; } break; - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: + case ENCODER_ID_INTERNAL_KLDSCP_DAC1: if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) args.v3.ucEncoderID = ASIC_INT_TV_ENCODER_ID; else if (amdgpu_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) @@ -1454,7 +1479,7 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder) else args.v3.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; break; - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: + case ENCODER_ID_INTERNAL_KLDSCP_DAC2: if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) args.v3.ucEncoderID = ASIC_INT_TV_ENCODER_ID; else if (amdgpu_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) @@ -1462,6 +1487,8 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder) else args.v3.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; break; + default: + break; } break; } @@ -1484,15 +1511,17 @@ amdgpu_atombios_encoder_init_dig(struct amdgpu_device *adev) list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct drm_encoder *ext_encoder = amdgpu_get_external_encoder(encoder); - - switch (amdgpu_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: + enum encoder_id enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id); + switch (enc_id) { + case ENCODER_ID_INTERNAL_UNIPHY: + case ENCODER_ID_INTERNAL_UNIPHY1: + case ENCODER_ID_INTERNAL_UNIPHY2: + case ENCODER_ID_INTERNAL_UNIPHY3: amdgpu_atombios_encoder_setup_dig_transmitter(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); break; + default: + return; }
if (ext_encoder) @@ -1509,6 +1538,7 @@ amdgpu_atombios_encoder_dac_load_detect(struct drm_encoder *encoder, struct amdgpu_device *adev = dev->dev_private; struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + enum encoder_id enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id);
if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT | @@ -1524,8 +1554,8 @@ amdgpu_atombios_encoder_dac_load_detect(struct drm_encoder *encoder,
args.sDacload.ucMisc = 0;
- if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || - (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) + if ((enc_id == ENCODER_ID_INTERNAL_DAC1) || + (enc_id == ENCODER_ID_INTERNAL_KLDSCP_DAC1)) args.sDacload.ucDacType = ATOM_DAC_A; else args.sDacload.ucDacType = ATOM_DAC_B; @@ -1811,7 +1841,7 @@ amdgpu_atombios_encoder_get_lcd_info(struct amdgpu_encoder *encoder) union lvds_info *lvds_info; uint8_t frev, crev; struct amdgpu_encoder_atom_dig *lvds = NULL; - int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; + enum object_enum_id encoder_enum = encoder->encoder_object_id.enum_id;
if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset)) { @@ -1867,7 +1897,7 @@ amdgpu_atombios_encoder_get_lcd_info(struct amdgpu_encoder *encoder)
encoder->native_mode = lvds->native_mode;
- if (encoder_enum == 2) + if (encoder_enum == ENUM_ID_2) lvds->linkb = true; else lvds->linkb = false; @@ -1943,7 +1973,7 @@ amdgpu_atombios_encoder_get_lcd_info(struct amdgpu_encoder *encoder) struct amdgpu_encoder_atom_dig * amdgpu_atombios_encoder_get_dig_info(struct amdgpu_encoder *amdgpu_encoder) { - int encoder_enum = (amdgpu_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; + enum object_enum_id encoder_enum = amdgpu_encoder->encoder_object_id.enum_id; struct amdgpu_encoder_atom_dig *dig = kzalloc(sizeof(struct amdgpu_encoder_atom_dig), GFP_KERNEL);
if (!dig) @@ -1953,7 +1983,7 @@ amdgpu_atombios_encoder_get_dig_info(struct amdgpu_encoder *amdgpu_encoder) dig->coherent_mode = true; dig->dig_encoder = -1;
- if (encoder_enum == 2) + if (encoder_enum == ENUM_ID_2) dig->linkb = true; else dig->linkb = false; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 90dc73b..993de0f 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -716,6 +716,7 @@ static void dce_v10_0_program_fmt(struct drm_encoder *encoder) int bpc = 0; u32 tmp = 0; enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE; + enum encoder_id enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id);
if (connector) { struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); @@ -728,8 +729,8 @@ static void dce_v10_0_program_fmt(struct drm_encoder *encoder) return;
/* not needed for analog */ - if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || - (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) + if ((enc_id == ENCODER_ID_INTERNAL_KLDSCP_DAC1) || + (enc_id == ENCODER_ID_INTERNAL_KLDSCP_DAC2)) return;
if (bpc == 0) @@ -1973,7 +1974,7 @@ static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable) dig->afmt->enabled = enable;
DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n", - enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); + enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_object_id.id); }
static int dce_v10_0_afmt_init(struct amdgpu_device *adev) @@ -2387,31 +2388,31 @@ static int dce_v10_0_pick_dig_encoder(struct drm_encoder *encoder) { struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + enum encoder_id enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id);
- switch (amdgpu_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: + switch (enc_id) { + case ENCODER_ID_INTERNAL_UNIPHY: if (dig->linkb) return 1; else return 0; break; - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: + case ENCODER_ID_INTERNAL_UNIPHY1: if (dig->linkb) return 3; else - return 2; - break; - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: + return 2; break; + case ENCODER_ID_INTERNAL_UNIPHY2: if (dig->linkb) return 5; else return 4; break; - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: + case ENCODER_ID_INTERNAL_UNIPHY3: return 6; break; default: - DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); + DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_object_id.id); return 0; } } @@ -2791,7 +2792,7 @@ static void dce_v10_0_crtc_disable(struct drm_crtc *crtc) case ATOM_PPLL2: /* disable the ppll */ amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, - 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); + 0, DISPLAY_NO_OBJECT, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); break; default: break; @@ -3547,7 +3548,7 @@ static void dce_v10_0_encoder_prepare(struct drm_encoder *encoder) if ((amdgpu_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != - ENCODER_OBJECT_ID_NONE)) { + ENCODER_ID_UNKNOWN)) { struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; if (dig) { dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder); @@ -3676,9 +3677,9 @@ static const struct drm_encoder_funcs dce_v10_0_encoder_funcs = { };
static void dce_v10_0_encoder_add(struct amdgpu_device *adev, - uint32_t encoder_enum, - uint32_t supported_device, - u16 caps) + struct graphics_object_id encoder_object_id, + uint32_t supported_device, + u16 caps) { struct drm_device *dev = adev->ddev; struct drm_encoder *encoder; @@ -3687,7 +3688,8 @@ static void dce_v10_0_encoder_add(struct amdgpu_device *adev, /* see if we already added it */ list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { amdgpu_encoder = to_amdgpu_encoder(encoder); - if (amdgpu_encoder->encoder_enum == encoder_enum) { + if (display_graphics_object_id_is_equal_unchecked(amdgpu_encoder->encoder_object_id, + encoder_object_id)) { amdgpu_encoder->devices |= supported_device; return; } @@ -3718,25 +3720,24 @@ static void dce_v10_0_encoder_add(struct amdgpu_device *adev,
amdgpu_encoder->enc_priv = NULL;
- amdgpu_encoder->encoder_enum = encoder_enum; - amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; + amdgpu_encoder->encoder_object_id = encoder_object_id; amdgpu_encoder->devices = supported_device; amdgpu_encoder->rmx_type = RMX_OFF; amdgpu_encoder->underscan_type = UNDERSCAN_OFF; amdgpu_encoder->is_ext_encoder = false; amdgpu_encoder->caps = caps;
- switch (amdgpu_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: + switch (encoder_object_id.id) { + case ENCODER_ID_INTERNAL_KLDSCP_DAC1: + case ENCODER_ID_INTERNAL_KLDSCP_DAC2: drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, DRM_MODE_ENCODER_DAC, NULL); drm_encoder_helper_add(encoder, &dce_v10_0_dac_helper_funcs); break; - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: + case ENCODER_ID_INTERNAL_UNIPHY: + case ENCODER_ID_INTERNAL_UNIPHY1: + case ENCODER_ID_INTERNAL_UNIPHY2: + case ENCODER_ID_INTERNAL_UNIPHY3: if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { amdgpu_encoder->rmx_type = RMX_FULL; drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, @@ -3753,8 +3754,8 @@ static void dce_v10_0_encoder_add(struct amdgpu_device *adev, } drm_encoder_helper_add(encoder, &dce_v10_0_dig_helper_funcs); break; - case ENCODER_OBJECT_ID_TRAVIS: - case ENCODER_OBJECT_ID_NUTMEG: + case ENCODER_ID_EXTERNAL_TRAVIS: + case ENCODER_ID_EXTERNAL_NUTMEG: /* these are handled by the primary encoders */ amdgpu_encoder->is_ext_encoder = true; if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index d3c9fb7..b7edba9 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -651,6 +651,7 @@ static void dce_v11_0_program_fmt(struct drm_encoder *encoder) int bpc = 0; u32 tmp = 0; enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE; + enum encoder_id enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id);
if (connector) { struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); @@ -663,8 +664,8 @@ static void dce_v11_0_program_fmt(struct drm_encoder *encoder) return;
/* not needed for analog */ - if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || - (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) + if ((enc_id == ENCODER_ID_INTERNAL_KLDSCP_DAC1) || + (enc_id == ENCODER_ID_INTERNAL_KLDSCP_DAC2)) return;
if (bpc == 0) @@ -1908,7 +1909,7 @@ static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable) dig->afmt->enabled = enable;
DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n", - enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); + enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_object_id.id); }
static int dce_v11_0_afmt_init(struct amdgpu_device *adev) @@ -2313,31 +2314,32 @@ static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder) { struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; + enum encoder_id enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id);
- switch (amdgpu_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: + switch (enc_id) { + case ENCODER_ID_INTERNAL_UNIPHY: if (dig->linkb) return 1; else return 0; break; - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: + case ENCODER_ID_INTERNAL_UNIPHY1: if (dig->linkb) return 3; else return 2; break; - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: + case ENCODER_ID_INTERNAL_UNIPHY2: if (dig->linkb) return 5; else return 4; break; - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: + case ENCODER_ID_INTERNAL_UNIPHY3: return 6; break; default: - DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); + DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_object_id.id); return 0; } } @@ -2727,7 +2729,7 @@ static void dce_v11_0_crtc_disable(struct drm_crtc *crtc) case ATOM_PPLL2: /* disable the ppll */ amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, - 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); + 0, DISPLAY_NO_OBJECT, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); break; default: break; @@ -3488,7 +3490,7 @@ static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder) if ((amdgpu_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != - ENCODER_OBJECT_ID_NONE)) { + ENCODER_ID_UNKNOWN)) { struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; if (dig) { dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder); @@ -3617,9 +3619,9 @@ static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = { };
static void dce_v11_0_encoder_add(struct amdgpu_device *adev, - uint32_t encoder_enum, - uint32_t supported_device, - u16 caps) + struct graphics_object_id encoder_object_id, + uint32_t supported_device, + u16 caps) { struct drm_device *dev = adev->ddev; struct drm_encoder *encoder; @@ -3628,7 +3630,8 @@ static void dce_v11_0_encoder_add(struct amdgpu_device *adev, /* see if we already added it */ list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { amdgpu_encoder = to_amdgpu_encoder(encoder); - if (amdgpu_encoder->encoder_enum == encoder_enum) { + if (display_graphics_object_id_is_equal_unchecked(amdgpu_encoder->encoder_object_id, + encoder_object_id)) { amdgpu_encoder->devices |= supported_device; return; } @@ -3659,25 +3662,24 @@ static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
amdgpu_encoder->enc_priv = NULL;
- amdgpu_encoder->encoder_enum = encoder_enum; - amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; + amdgpu_encoder->encoder_object_id = encoder_object_id; amdgpu_encoder->devices = supported_device; amdgpu_encoder->rmx_type = RMX_OFF; amdgpu_encoder->underscan_type = UNDERSCAN_OFF; amdgpu_encoder->is_ext_encoder = false; amdgpu_encoder->caps = caps;
- switch (amdgpu_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: + switch (encoder_object_id.id) { + case ENCODER_ID_INTERNAL_KLDSCP_DAC1: + case ENCODER_ID_INTERNAL_KLDSCP_DAC2: drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, DRM_MODE_ENCODER_DAC, NULL); drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs); break; - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: + case ENCODER_ID_INTERNAL_UNIPHY: + case ENCODER_ID_INTERNAL_UNIPHY1: + case ENCODER_ID_INTERNAL_UNIPHY2: + case ENCODER_ID_INTERNAL_UNIPHY3: if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { amdgpu_encoder->rmx_type = RMX_FULL; drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, @@ -3694,8 +3696,8 @@ static void dce_v11_0_encoder_add(struct amdgpu_device *adev, } drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs); break; - case ENCODER_OBJECT_ID_TRAVIS: - case ENCODER_OBJECT_ID_NUTMEG: + case ENCODER_ID_EXTERNAL_TRAVIS: + case ENCODER_ID_EXTERNAL_NUTMEG: /* these are handled by the primary encoders */ amdgpu_encoder->is_ext_encoder = true; if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index ddb8eba..f46991b 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -664,6 +664,7 @@ static void dce_v8_0_program_fmt(struct drm_encoder *encoder) int bpc = 0; u32 tmp = 0; enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE; + enum encoder_id enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id);
if (connector) { struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); @@ -676,8 +677,8 @@ static void dce_v8_0_program_fmt(struct drm_encoder *encoder) return;
/* not needed for analog */ - if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || - (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) + if ((enc_id == ENCODER_ID_INTERNAL_KLDSCP_DAC1) || + (enc_id == ENCODER_ID_INTERNAL_KLDSCP_DAC2)) return;
if (bpc == 0) @@ -1910,7 +1911,7 @@ static void dce_v8_0_afmt_enable(struct drm_encoder *encoder, bool enable) dig->afmt->enabled = enable;
DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n", - enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); + enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_object_id.id); }
static int dce_v8_0_afmt_init(struct amdgpu_device *adev) @@ -2288,31 +2289,31 @@ static int dce_v8_0_pick_dig_encoder(struct drm_encoder *encoder) { struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; - - switch (amdgpu_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: + enum encoder_id enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id); + switch (enc_id) { + case ENCODER_ID_INTERNAL_UNIPHY: if (dig->linkb) return 1; else return 0; break; - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: + case ENCODER_ID_INTERNAL_UNIPHY1: if (dig->linkb) return 3; else return 2; break; - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: + case ENCODER_ID_INTERNAL_UNIPHY2: if (dig->linkb) return 5; else return 4; break; - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: + case ENCODER_ID_INTERNAL_UNIPHY3: return 6; break; default: - DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); + DRM_ERROR("invalid encoder_id: 0x%x\n", enc_id); return 0; } } @@ -2702,7 +2703,7 @@ static void dce_v8_0_crtc_disable(struct drm_crtc *crtc) case ATOM_PPLL2: /* disable the ppll */ amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, - 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); + 0, DISPLAY_NO_OBJECT, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); break; case ATOM_PPLL0: /* disable the ppll */ @@ -2710,7 +2711,7 @@ static void dce_v8_0_crtc_disable(struct drm_crtc *crtc) (adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII)) amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, - 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); + 0, DISPLAY_NO_OBJECT, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); break; default: break; @@ -3477,7 +3478,7 @@ static void dce_v8_0_encoder_prepare(struct drm_encoder *encoder) if ((amdgpu_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != - ENCODER_OBJECT_ID_NONE)) { + ENCODER_ID_UNKNOWN)) { struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; if (dig) { dig->dig_encoder = dce_v8_0_pick_dig_encoder(encoder); @@ -3606,7 +3607,7 @@ static const struct drm_encoder_funcs dce_v8_0_encoder_funcs = { };
static void dce_v8_0_encoder_add(struct amdgpu_device *adev, - uint32_t encoder_enum, + struct graphics_object_id encoder_object_id, uint32_t supported_device, u16 caps) { @@ -3617,11 +3618,11 @@ static void dce_v8_0_encoder_add(struct amdgpu_device *adev, /* see if we already added it */ list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { amdgpu_encoder = to_amdgpu_encoder(encoder); - if (amdgpu_encoder->encoder_enum == encoder_enum) { + if (display_graphics_object_id_is_equal_unchecked(amdgpu_encoder->encoder_object_id, + encoder_object_id)) { amdgpu_encoder->devices |= supported_device; return; } - }
/* add a new one */ @@ -3648,25 +3649,24 @@ static void dce_v8_0_encoder_add(struct amdgpu_device *adev,
amdgpu_encoder->enc_priv = NULL;
- amdgpu_encoder->encoder_enum = encoder_enum; - amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; + amdgpu_encoder->encoder_object_id = encoder_object_id; amdgpu_encoder->devices = supported_device; amdgpu_encoder->rmx_type = RMX_OFF; amdgpu_encoder->underscan_type = UNDERSCAN_OFF; amdgpu_encoder->is_ext_encoder = false; amdgpu_encoder->caps = caps;
- switch (amdgpu_encoder->encoder_id) { - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: - case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: + switch (encoder_object_id.id) { + case ENCODER_ID_INTERNAL_KLDSCP_DAC1: + case ENCODER_ID_INTERNAL_KLDSCP_DAC2: drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs, DRM_MODE_ENCODER_DAC, NULL); drm_encoder_helper_add(encoder, &dce_v8_0_dac_helper_funcs); break; - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: - case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: + case ENCODER_ID_INTERNAL_UNIPHY: + case ENCODER_ID_INTERNAL_UNIPHY1: + case ENCODER_ID_INTERNAL_UNIPHY2: + case ENCODER_ID_INTERNAL_UNIPHY3: if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { amdgpu_encoder->rmx_type = RMX_FULL; drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs, @@ -3683,8 +3683,8 @@ static void dce_v8_0_encoder_add(struct amdgpu_device *adev, } drm_encoder_helper_add(encoder, &dce_v8_0_dig_helper_funcs); break; - case ENCODER_OBJECT_ID_TRAVIS: - case ENCODER_OBJECT_ID_NUTMEG: + case ENCODER_ID_EXTERNAL_TRAVIS: + case ENCODER_ID_EXTERNAL_NUTMEG: /* these are handled by the primary encoders */ amdgpu_encoder->is_ext_encoder = true; if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) diff --git a/drivers/gpu/drm/amd/include/display_grph_object_id.h b/drivers/gpu/drm/amd/include/display_grph_object_id.h index 2bb8642..9fbf7fb 100644 --- a/drivers/gpu/drm/amd/include/display_grph_object_id.h +++ b/drivers/gpu/drm/amd/include/display_grph_object_id.h @@ -315,4 +315,5 @@ static inline uint32_t display_graphics_object_id_to_uint(struct graphics_object return object_id; }
+#define DISPLAY_NO_OBJECT (struct graphics_object_id){0} #endif
From: Dave Airlie airlied@redhat.com
As before, convert the crtc_id to a graphics object id.
Signed-off-by: Dave Airlie airlied@redhat.com --- drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 10 ++--- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 2 +- drivers/gpu/drm/amd/amdgpu/atombios_crtc.c | 55 ++++++++++++++------------ drivers/gpu/drm/amd/amdgpu/atombios_crtc.h | 2 +- drivers/gpu/drm/amd/amdgpu/atombios_encoders.c | 8 ++-- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 31 ++++++++------- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 31 ++++++++------- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 33 ++++++++-------- 11 files changed, 93 insertions(+), 85 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c index 8b653f2..11aa704 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c @@ -828,7 +828,7 @@ static int amdgpu_cgs_get_active_displays_info(struct cgs_device *cgs_device, &ddev->mode_config.crtc_list, head) { amdgpu_crtc = to_amdgpu_crtc(crtc); if (crtc->enabled) { - info->active_display_mask |= (1 << amdgpu_crtc->crtc_id); + info->active_display_mask |= (1 << amdgpu_crtc->crtc_object_id.id); info->display_count++; } if (mode_info != NULL && diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 448b211..d80d2dd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -140,7 +140,7 @@ static void amdgpu_flip_work_func(struct work_struct *__work)
DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n", - amdgpuCrtc->crtc_id, amdgpuCrtc, work); + amdgpuCrtc->crtc_object_id.id, amdgpuCrtc, work);
}
@@ -196,7 +196,7 @@ int amdgpu_crtc_page_flip(struct drm_crtc *crtc,
work->event = event; work->adev = adev; - work->crtc_id = amdgpu_crtc->crtc_id; + work->crtc_id = amdgpu_crtc->crtc_object_id.id;
/* schedule unpin of the old buffer */ old_amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); @@ -239,7 +239,7 @@ int amdgpu_crtc_page_flip(struct drm_crtc *crtc,
work->base = base;
- r = drm_vblank_get(crtc->dev, amdgpu_crtc->crtc_id); + r = drm_vblank_get(crtc->dev, amdgpu_crtc->crtc_object_id.id); if (r) { DRM_ERROR("failed to get vblank before flip\n"); goto pflip_cleanup; @@ -259,7 +259,7 @@ int amdgpu_crtc_page_flip(struct drm_crtc *crtc,
DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n", - amdgpu_crtc->crtc_id, amdgpu_crtc, work); + amdgpu_crtc->crtc_object_id.id, amdgpu_crtc, work); /* update crtc fb */ crtc->primary->fb = fb; spin_unlock_irqrestore(&crtc->dev->event_lock, flags); @@ -267,7 +267,7 @@ int amdgpu_crtc_page_flip(struct drm_crtc *crtc, return 0;
vblank_cleanup: - drm_vblank_put(crtc->dev, amdgpu_crtc->crtc_id); + drm_vblank_put(crtc->dev, amdgpu_crtc->crtc_object_id.id);
pflip_cleanup: if (unlikely(amdgpu_bo_reserve(new_rbo, false) != 0)) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 1f9d318..8449f45 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -181,7 +181,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file crtc = (struct drm_crtc *)minfo->crtcs[i]; if (crtc && crtc->base.id == info->mode_crtc.id) { struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); - ui32 = amdgpu_crtc->crtc_id; + ui32 = display_graphics_object_id_get_controller_id(amdgpu_crtc->crtc_object_id); found = 1; break; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 96e1de8..5624c81 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -368,7 +368,7 @@ struct amdgpu_atom_ss {
struct amdgpu_crtc { struct drm_crtc base; - int crtc_id; + struct graphics_object_id crtc_object_id; u16 lut_r[256], lut_g[256], lut_b[256]; bool enabled; bool can_tile; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c index 6d44d4a..8bb3ced 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c @@ -1162,7 +1162,7 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev) &ddev->mode_config.crtc_list, head) { amdgpu_crtc = to_amdgpu_crtc(crtc); if (crtc->enabled) { - adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id); + adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_object_id.id); adev->pm.dpm.new_active_crtc_count++; } } diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c index 5b8d3c6..8731773 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c @@ -45,10 +45,10 @@ void amdgpu_atombios_crtc_overscan_setup(struct drm_crtc *crtc, SET_CRTC_OVERSCAN_PS_ALLOCATION args; int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan); int a1, a2; - + enum controller_id controller_id = display_graphics_object_id_get_controller_id(amdgpu_crtc->crtc_object_id); memset(&args, 0, sizeof(args));
- args.ucCRTC = amdgpu_crtc->crtc_id; + args.ucCRTC = controller_id;
switch (amdgpu_crtc->rmx_type) { case RMX_CENTER: @@ -87,10 +87,10 @@ void amdgpu_atombios_crtc_scaler_setup(struct drm_crtc *crtc) struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); ENABLE_SCALER_PS_ALLOCATION args; int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); - + enum controller_id controller_id = display_graphics_object_id_get_controller_id(amdgpu_crtc->crtc_object_id); memset(&args, 0, sizeof(args));
- args.ucScaler = amdgpu_crtc->crtc_id; + args.ucScaler = controller_id;
switch (amdgpu_crtc->rmx_type) { case RMX_FULL: @@ -117,10 +117,10 @@ void amdgpu_atombios_crtc_lock(struct drm_crtc *crtc, int lock) int index = GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters); ENABLE_CRTC_PS_ALLOCATION args; - + enum controller_id controller_id = display_graphics_object_id_get_controller_id(amdgpu_crtc->crtc_object_id); memset(&args, 0, sizeof(args));
- args.ucCRTC = amdgpu_crtc->crtc_id; + args.ucCRTC = controller_id; args.ucEnable = lock;
amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); @@ -133,10 +133,10 @@ void amdgpu_atombios_crtc_enable(struct drm_crtc *crtc, int state) struct amdgpu_device *adev = dev->dev_private; int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC); ENABLE_CRTC_PS_ALLOCATION args; - + enum controller_id controller_id = display_graphics_object_id_get_controller_id(amdgpu_crtc->crtc_object_id); memset(&args, 0, sizeof(args));
- args.ucCRTC = amdgpu_crtc->crtc_id; + args.ucCRTC = controller_id; args.ucEnable = state;
amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); @@ -149,10 +149,11 @@ void amdgpu_atombios_crtc_blank(struct drm_crtc *crtc, int state) struct amdgpu_device *adev = dev->dev_private; int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC); BLANK_CRTC_PS_ALLOCATION args; + enum controller_id controller_id = display_graphics_object_id_get_controller_id(amdgpu_crtc->crtc_object_id);
memset(&args, 0, sizeof(args));
- args.ucCRTC = amdgpu_crtc->crtc_id; + args.ucCRTC = controller_id; args.ucBlanking = state;
amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); @@ -165,10 +166,11 @@ void amdgpu_atombios_crtc_powergate(struct drm_crtc *crtc, int state) struct amdgpu_device *adev = dev->dev_private; int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating); ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args; + enum controller_id controller_id = display_graphics_object_id_get_controller_id(amdgpu_crtc->crtc_object_id);
memset(&args, 0, sizeof(args));
- args.ucDispPipeId = amdgpu_crtc->crtc_id; + args.ucDispPipeId = controller_id; args.ucEnable = state;
amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); @@ -195,6 +197,7 @@ void amdgpu_atombios_crtc_set_dtd_timing(struct drm_crtc *crtc, SET_CRTC_USING_DTD_TIMING_PARAMETERS args; int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming); u16 misc = 0; + enum controller_id controller_id = display_graphics_object_id_get_controller_id(amdgpu_crtc->crtc_object_id);
memset(&args, 0, sizeof(args)); args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (amdgpu_crtc->h_border * 2)); @@ -226,7 +229,7 @@ void amdgpu_atombios_crtc_set_dtd_timing(struct drm_crtc *crtc, misc |= ATOM_DOUBLE_CLOCK_MODE;
args.susModeMiscInfo.usAccess = cpu_to_le16(misc); - args.ucCRTC = amdgpu_crtc->crtc_id; + args.ucCRTC = controller_id;
amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); } @@ -238,14 +241,15 @@ union atom_enable_ss { };
static void amdgpu_atombios_crtc_program_ss(struct amdgpu_device *adev, - int enable, - int pll_id, - int crtc_id, - struct amdgpu_atom_ss *ss) + int enable, + int pll_id, + struct graphics_object_id crtc_object_id, + struct amdgpu_atom_ss *ss) { unsigned i; int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL); union atom_enable_ss args; + enum controller_id controller_id = display_graphics_object_id_get_controller_id(crtc_object_id);
if (enable) { /* Don't mess with SS if percentage is 0 or external ss. @@ -261,7 +265,7 @@ static void amdgpu_atombios_crtc_program_ss(struct amdgpu_device *adev, for (i = 0; i < adev->mode_info.num_crtc; i++) { if (adev->mode_info.crtcs[i] && adev->mode_info.crtcs[i]->enabled && - i != crtc_id && + i != controller_id && pll_id == adev->mode_info.crtcs[i]->pll_id) { /* one other crtc is using this pll don't turn * off spread spectrum as it might turn off @@ -521,7 +525,7 @@ static bool is_pixel_clock_source_from_pll(u32 encoder_mode, int pll_id) }
void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc, - u32 crtc_id, + struct graphics_object_id crtc_object_id, int pll_id, u32 encoder_mode, struct graphics_object_id encoder_object_id, @@ -540,6 +544,7 @@ void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc, int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); union set_pixel_clock args; uint8_t atom_enc_id = amdgpu_encoder_object_to_atom(encoder_object_id); + enum controller_id controller_id = display_graphics_object_id_get_controller_id(crtc_object_id);
memset(&args, 0, sizeof(args));
@@ -559,7 +564,7 @@ void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc, args.v1.ucFracFbDiv = frac_fb_div; args.v1.ucPostDiv = post_div; args.v1.ucPpll = pll_id; - args.v1.ucCRTC = crtc_id; + args.v1.ucCRTC = controller_id; args.v1.ucRefDivSrc = 1; break; case 2: @@ -569,7 +574,7 @@ void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc, args.v2.ucFracFbDiv = frac_fb_div; args.v2.ucPostDiv = post_div; args.v2.ucPpll = pll_id; - args.v2.ucCRTC = crtc_id; + args.v2.ucCRTC = controller_id; args.v2.ucRefDivSrc = 1; break; case 3: @@ -579,7 +584,7 @@ void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc, args.v3.ucFracFbDiv = frac_fb_div; args.v3.ucPostDiv = post_div; args.v3.ucPpll = pll_id; - if (crtc_id == ATOM_CRTC2) + if (controller_id == ATOM_CRTC2) args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2; else args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1; @@ -589,7 +594,7 @@ void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc, args.v3.ucEncoderMode = encoder_mode; break; case 5: - args.v5.ucCRTC = crtc_id; + args.v5.ucCRTC = controller_id; args.v5.usPixelClock = cpu_to_le16(clock / 10); args.v5.ucRefDiv = ref_div; args.v5.usFbDiv = cpu_to_le16(fb_div); @@ -620,7 +625,7 @@ void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc, args.v5.ucPpll = pll_id; break; case 6: - args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10); + args.v6.ulDispEngClkFreq = cpu_to_le32(controller_id << 24 | clock / 10); args.v6.ucRefDiv = ref_div; args.v6.usFbDiv = cpu_to_le16(fb_div); args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); @@ -775,9 +780,9 @@ void amdgpu_atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode &fb_div, &frac_fb_div, &ref_div, &post_div);
amdgpu_atombios_crtc_program_ss(adev, ATOM_DISABLE, amdgpu_crtc->pll_id, - amdgpu_crtc->crtc_id, &amdgpu_crtc->ss); + amdgpu_crtc->crtc_object_id, &amdgpu_crtc->ss);
- amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, + amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_object_id, amdgpu_crtc->pll_id, encoder_mode, amdgpu_encoder->encoder_object_id, clock, ref_div, fb_div, frac_fb_div, post_div, amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss); @@ -800,7 +805,7 @@ void amdgpu_atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode amdgpu_crtc->ss.step = step_size;
amdgpu_atombios_crtc_program_ss(adev, ATOM_ENABLE, amdgpu_crtc->pll_id, - amdgpu_crtc->crtc_id, &amdgpu_crtc->ss); + amdgpu_crtc->crtc_object_id, &amdgpu_crtc->ss); } }
diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_crtc.h b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.h index 452245f..c10a570 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_crtc.h +++ b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.h @@ -38,7 +38,7 @@ void amdgpu_atombios_crtc_set_dtd_timing(struct drm_crtc *crtc, void amdgpu_atombios_crtc_set_disp_eng_pll(struct amdgpu_device *adev, u32 dispclk); void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc, - u32 crtc_id, + struct graphics_object_id crtc_object_id, int pll_id, u32 encoder_mode, struct graphics_object_id encoder_object_id, diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c index 28d306a..9f7f3fc 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c @@ -1307,7 +1307,7 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder) uint8_t frev, crev; struct amdgpu_encoder_atom_dig *dig; enum encoder_id enc_id = display_graphics_object_id_get_encoder_id(amdgpu_encoder->encoder_object_id); - + enum controller_id controller_id = display_graphics_object_id_get_controller_id(amdgpu_crtc->crtc_object_id); memset(&args, 0, sizeof(args));
if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) @@ -1318,7 +1318,7 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder) switch (crev) { case 1: default: - args.v1.ucCRTC = amdgpu_crtc->crtc_id; + args.v1.ucCRTC = controller_id; switch (enc_id) { case ENCODER_ID_INTERNAL_TMDS1: case ENCODER_ID_INTERNAL_KLDSCP_TMDS1: @@ -1357,7 +1357,7 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder) } break; case 2: - args.v2.ucCRTC = amdgpu_crtc->crtc_id; + args.v2.ucCRTC = controller_id; if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_ID_UNKNOWN) { struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
@@ -1424,7 +1424,7 @@ amdgpu_atombios_encoder_set_crtc_source(struct drm_encoder *encoder) } break; case 3: - args.v3.ucCRTC = amdgpu_crtc->crtc_id; + args.v3.ucCRTC = controller_id; if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_ID_UNKNOWN) { struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 993de0f..e2b22bf 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -802,7 +802,7 @@ static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev, struct drm_display_mode *mode) { u32 tmp, buffer_alloc, i, mem_cfg; - u32 pipe_offset = amdgpu_crtc->crtc_id; + u32 pipe_offset = amdgpu_crtc->crtc_object_id.id; /* * Line Buffer Setup * There are 6 line buffers, one for each display controllers. @@ -1760,7 +1760,7 @@ static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) */ tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, - amdgpu_crtc->crtc_id); + amdgpu_crtc->crtc_object_id.id); WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase); WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo); @@ -2028,12 +2028,13 @@ static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable) struct drm_device *dev = crtc->dev; struct amdgpu_device *adev = dev->dev_private; u32 vga_control; + enum controller_id controller_id = display_graphics_object_id_get_controller_id(amdgpu_crtc->crtc_object_id);
- vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; + vga_control = RREG32(vga_control_regs[controller_id]) & ~1; if (enable) - WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); + WREG32(vga_control_regs[controller_id], vga_control | 1); else - WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); + WREG32(vga_control_regs[controller_id], vga_control); }
static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable) @@ -2312,7 +2313,7 @@ static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc) int i; u32 tmp;
- DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); + DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_object_id.id);
tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0); @@ -2590,7 +2591,7 @@ static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc,
obj = drm_gem_object_lookup(crtc->dev, file_priv, handle); if (!obj) { - DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); + DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_object_id.id); return -ENOENT; }
@@ -2708,16 +2709,16 @@ static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode) amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); dce_v10_0_vga_enable(crtc, false); /* Make sure VBLANK and PFLIP interrupts are still enabled */ - type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id); + type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_object_id.id); amdgpu_irq_update(adev, &adev->crtc_irq, type); amdgpu_irq_update(adev, &adev->pageflip_irq, type); - drm_vblank_on(dev, amdgpu_crtc->crtc_id); + drm_vblank_on(dev, amdgpu_crtc->crtc_object_id.id); dce_v10_0_crtc_load_lut(crtc); break; case DRM_MODE_DPMS_STANDBY: case DRM_MODE_DPMS_SUSPEND: case DRM_MODE_DPMS_OFF: - drm_vblank_off(dev, amdgpu_crtc->crtc_id); + drm_vblank_off(dev, amdgpu_crtc->crtc_object_id.id); if (amdgpu_crtc->enabled) { dce_v10_0_vga_enable(crtc, true); amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); @@ -2777,7 +2778,7 @@ static void dce_v10_0_crtc_disable(struct drm_crtc *crtc) for (i = 0; i < adev->mode_info.num_crtc; i++) { if (adev->mode_info.crtcs[i] && adev->mode_info.crtcs[i]->enabled && - i != amdgpu_crtc->crtc_id && + i != amdgpu_crtc->crtc_object_id.id && amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { /* one other crtc is using this pll don't turn * off the pll @@ -2791,7 +2792,7 @@ static void dce_v10_0_crtc_disable(struct drm_crtc *crtc) case ATOM_PPLL1: case ATOM_PPLL2: /* disable the ppll */ - amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, + amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_object_id, amdgpu_crtc->pll_id, 0, DISPLAY_NO_OBJECT, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); break; default: @@ -2899,7 +2900,7 @@ static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index) drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v10_0_crtc_funcs);
drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); - amdgpu_crtc->crtc_id = index; + amdgpu_crtc->crtc_object_id = display_graphics_object_id_init(index, ENUM_ID_UNKNOWN, OBJECT_TYPE_CONTROLLER); adev->mode_info.crtcs[index] = amdgpu_crtc;
amdgpu_crtc->max_cursor_width = 128; @@ -2913,7 +2914,7 @@ static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index) amdgpu_crtc->lut_b[i] = i << 2; }
- switch (amdgpu_crtc->crtc_id) { + switch (index) { case 0: default: amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET; @@ -3375,7 +3376,7 @@ static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev,
spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
- drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id); + drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_object_id.id); schedule_work(&works->unpin_work);
return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index b7edba9..a231679 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -737,7 +737,7 @@ static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev, struct drm_display_mode *mode) { u32 tmp, buffer_alloc, i, mem_cfg; - u32 pipe_offset = amdgpu_crtc->crtc_id; + u32 pipe_offset = amdgpu_crtc->crtc_object_id.id; /* * Line Buffer Setup * There are 6 line buffers, one for each display controllers. @@ -1695,7 +1695,7 @@ static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) */ tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, - amdgpu_crtc->crtc_id); + amdgpu_crtc->crtc_object_id.id); WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase); WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo); @@ -1963,12 +1963,13 @@ static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable) struct drm_device *dev = crtc->dev; struct amdgpu_device *adev = dev->dev_private; u32 vga_control; + enum controller_id controller_id = display_graphics_object_id_get_controller_id(amdgpu_crtc->crtc_object_id);
- vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; + vga_control = RREG32(vga_control_regs[controller_id]) & ~1; if (enable) - WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); + WREG32(vga_control_regs[controller_id], vga_control | 1); else - WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); + WREG32(vga_control_regs[controller_id], vga_control); }
static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable) @@ -2247,7 +2248,7 @@ static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc) int i; u32 tmp;
- DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); + DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_object_id.id);
tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0); @@ -2527,7 +2528,7 @@ static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
obj = drm_gem_object_lookup(crtc->dev, file_priv, handle); if (!obj) { - DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); + DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_object_id.id); return -ENOENT; }
@@ -2645,16 +2646,16 @@ static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode) amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); dce_v11_0_vga_enable(crtc, false); /* Make sure VBLANK and PFLIP interrupts are still enabled */ - type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id); + type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_object_id.id); amdgpu_irq_update(adev, &adev->crtc_irq, type); amdgpu_irq_update(adev, &adev->pageflip_irq, type); - drm_vblank_on(dev, amdgpu_crtc->crtc_id); + drm_vblank_on(dev, amdgpu_crtc->crtc_object_id.id); dce_v11_0_crtc_load_lut(crtc); break; case DRM_MODE_DPMS_STANDBY: case DRM_MODE_DPMS_SUSPEND: case DRM_MODE_DPMS_OFF: - drm_vblank_off(dev, amdgpu_crtc->crtc_id); + drm_vblank_off(dev, amdgpu_crtc->crtc_object_id.id); if (amdgpu_crtc->enabled) { dce_v11_0_vga_enable(crtc, true); amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); @@ -2714,7 +2715,7 @@ static void dce_v11_0_crtc_disable(struct drm_crtc *crtc) for (i = 0; i < adev->mode_info.num_crtc; i++) { if (adev->mode_info.crtcs[i] && adev->mode_info.crtcs[i]->enabled && - i != amdgpu_crtc->crtc_id && + i != amdgpu_crtc->crtc_object_id.id && amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { /* one other crtc is using this pll don't turn * off the pll @@ -2728,7 +2729,7 @@ static void dce_v11_0_crtc_disable(struct drm_crtc *crtc) case ATOM_PPLL1: case ATOM_PPLL2: /* disable the ppll */ - amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, + amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_object_id, amdgpu_crtc->pll_id, 0, DISPLAY_NO_OBJECT, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); break; default: @@ -2836,7 +2837,7 @@ static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index) drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs);
drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); - amdgpu_crtc->crtc_id = index; + amdgpu_crtc->crtc_object_id = display_graphics_object_id_init(index, ENUM_ID_UNKNOWN, OBJECT_TYPE_CONTROLLER); adev->mode_info.crtcs[index] = amdgpu_crtc;
amdgpu_crtc->max_cursor_width = 128; @@ -2850,7 +2851,7 @@ static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index) amdgpu_crtc->lut_b[i] = i << 2; }
- switch (amdgpu_crtc->crtc_id) { + switch (index) { case 0: default: amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET; @@ -3317,7 +3318,7 @@ static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
- drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id); + drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_object_id.id); schedule_work(&works->unpin_work);
return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index f46991b..6a53cde 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -747,7 +747,7 @@ static u32 dce_v8_0_line_buffer_adjust(struct amdgpu_device *adev, struct drm_display_mode *mode) { u32 tmp, buffer_alloc, i; - u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8; + u32 pipe_offset = amdgpu_crtc->crtc_object_id.id * 0x8; /* * Line Buffer Setup * There are 6 line buffers, one for each display controllers. @@ -1716,7 +1716,7 @@ static void dce_v8_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator */ - WREG32(mmDCCG_AUDIO_DTO_SOURCE, (amdgpu_crtc->crtc_id << DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT)); + WREG32(mmDCCG_AUDIO_DTO_SOURCE, (amdgpu_crtc->crtc_object_id.id << DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT)); WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase); WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo); } @@ -1965,12 +1965,13 @@ static void dce_v8_0_vga_enable(struct drm_crtc *crtc, bool enable) struct drm_device *dev = crtc->dev; struct amdgpu_device *adev = dev->dev_private; u32 vga_control; + enum controller_id controller_id = display_graphics_object_id_get_controller_id(amdgpu_crtc->crtc_object_id);
- vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; + vga_control = RREG32(vga_control_regs[controller_id]) & ~1; if (enable) - WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); + WREG32(vga_control_regs[controller_id], vga_control | 1); else - WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); + WREG32(vga_control_regs[controller_id], vga_control); }
static void dce_v8_0_grph_enable(struct drm_crtc *crtc, bool enable) @@ -2229,7 +2230,7 @@ static void dce_v8_0_crtc_load_lut(struct drm_crtc *crtc) struct amdgpu_device *adev = dev->dev_private; int i;
- DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); + DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_object_id.id);
WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, ((INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) | @@ -2502,7 +2503,7 @@ static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc,
obj = drm_gem_object_lookup(crtc->dev, file_priv, handle); if (!obj) { - DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); + DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_object_id.id); return -ENOENT; }
@@ -2620,16 +2621,16 @@ static void dce_v8_0_crtc_dpms(struct drm_crtc *crtc, int mode) amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); dce_v8_0_vga_enable(crtc, false); /* Make sure VBLANK and PFLIP interrupts are still enabled */ - type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id); + type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_object_id.id); amdgpu_irq_update(adev, &adev->crtc_irq, type); amdgpu_irq_update(adev, &adev->pageflip_irq, type); - drm_vblank_on(dev, amdgpu_crtc->crtc_id); + drm_vblank_on(dev, amdgpu_crtc->crtc_object_id.id); dce_v8_0_crtc_load_lut(crtc); break; case DRM_MODE_DPMS_STANDBY: case DRM_MODE_DPMS_SUSPEND: case DRM_MODE_DPMS_OFF: - drm_vblank_off(dev, amdgpu_crtc->crtc_id); + drm_vblank_off(dev, amdgpu_crtc->crtc_object_id.id); if (amdgpu_crtc->enabled) { dce_v8_0_vga_enable(crtc, true); amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); @@ -2689,7 +2690,7 @@ static void dce_v8_0_crtc_disable(struct drm_crtc *crtc) for (i = 0; i < adev->mode_info.num_crtc; i++) { if (adev->mode_info.crtcs[i] && adev->mode_info.crtcs[i]->enabled && - i != amdgpu_crtc->crtc_id && + i != amdgpu_crtc->crtc_object_id.id && amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { /* one other crtc is using this pll don't turn * off the pll @@ -2702,7 +2703,7 @@ static void dce_v8_0_crtc_disable(struct drm_crtc *crtc) case ATOM_PPLL1: case ATOM_PPLL2: /* disable the ppll */ - amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, + amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_object_id, amdgpu_crtc->pll_id, 0, DISPLAY_NO_OBJECT, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); break; case ATOM_PPLL0: @@ -2710,7 +2711,7 @@ static void dce_v8_0_crtc_disable(struct drm_crtc *crtc) if ((adev->asic_type == CHIP_KAVERI) || (adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII)) - amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, + amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_object_id, amdgpu_crtc->pll_id, 0, DISPLAY_NO_OBJECT, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); break; default: @@ -2818,7 +2819,7 @@ static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index) drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v8_0_crtc_funcs);
drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); - amdgpu_crtc->crtc_id = index; + amdgpu_crtc->crtc_object_id = display_graphics_object_id_init(index, ENUM_ID_UNKNOWN, OBJECT_TYPE_CONTROLLER); adev->mode_info.crtcs[index] = amdgpu_crtc;
amdgpu_crtc->max_cursor_width = CIK_CURSOR_WIDTH; @@ -2832,7 +2833,7 @@ static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index) amdgpu_crtc->lut_b[i] = i << 2; }
- amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id]; + amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_object_id.id];
amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; amdgpu_crtc->adjusted_clock = 0; @@ -3384,7 +3385,7 @@ static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev,
spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
- drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id); + drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_object_id.id); schedule_work(&works->unpin_work);
return 0;
Am 14.04.2016 um 04:56 schrieb Dave Airlie:
DAL has a concept of storing the graphics object ids in a special small struct, and adding type safety to them.
I'm starting to contemplate bringing some pieces of DAL into the mainline modesetting code (like the bios parser for a start), and I think this is the best first step in that direction.
This series converts connectors, encoders and crtcs id to the DAL objects. I haven't done PLLs yet they are a bit messier and I probably need to think about them a bit more.
Also DAL doesn't support any of the DVO/external encoders, I've no idea if they even exist on DCE8 or newer GPUs, so I've done a separate patch to drop them.
I'm not so deep into the display engine stuff or DAL, but this looks like a good start to me to better integrate some of the DAL code into the existing code base.
So the patches are Acked-by: Christian König christian.koenig@amd.com.
I will ask around about the DVO stuff. Let me know if you need anything else while Alex is still asleep.
Regards, Christian.
Dave.
dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Makes sense to me.
Reviewed-by: Harry Wentland harry.wentland@amd.com
Harry
On 2016-04-14 04:25 AM, Christian König wrote:
Am 14.04.2016 um 04:56 schrieb Dave Airlie:
DAL has a concept of storing the graphics object ids in a special small struct, and adding type safety to them.
I'm starting to contemplate bringing some pieces of DAL into the mainline modesetting code (like the bios parser for a start), and I think this is the best first step in that direction.
This series converts connectors, encoders and crtcs id to the DAL objects. I haven't done PLLs yet they are a bit messier and I probably need to think about them a bit more.
Also DAL doesn't support any of the DVO/external encoders, I've no idea if they even exist on DCE8 or newer GPUs, so I've done a separate patch to drop them.
I'm not so deep into the display engine stuff or DAL, but this looks like a good start to me to better integrate some of the DAL code into the existing code base.
So the patches are Acked-by: Christian König christian.koenig@amd.com.
I will ask around about the DVO stuff. Let me know if you need anything else while Alex is still asleep.
Regards, Christian.
Dave.
dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
dri-devel@lists.freedesktop.org
-
Christian König -
Dave Airlie -
Emil Velikov -
Harry Wentland