The rk3228/rk3229 and rk3328 socs started using a new type of hdmi-phy from Innosilicon that resides completely separate from the dw-hdmi block and gets accessed via mmio.
Additionally the rk3328 dw-hdmi does not report the vendor-phy type but a different one instead, so add the possibility to override the phy type when the glue driver knows better than the ip block itself.
changes in v4: - rebased onto 4.19-rc2 - no actual changes - added Rob's Ack on the dw-hdmi compatible
changes in v3: - split off phy driver into a separate series - only allow forcing vendor phy type - wording fixes and other nits
changes in v2: - phy: prevent overflow in tmdsclk calculation as reported by Martin Cerveny - phy: use unsigned long for all tmdsclk rate uses - phy: simplify tmds rate calculation - dropped patch exporting some dw-hdmi phy functions as a similar patch entered drm-misc already
Heiko Stuebner (6): drm/bridge: dw-hdmi: allow forcing vendor phy-type drm/rockchip: dw_hdmi: Allow outputs that don't need output switching dt-bindings: allow optional phys in Rockchip dw_hdmi binding drm/rockchip: dw_hdmi: allow including external phys drm/rockchip: dw_hdmi: store rockchip_hdmi reference in phy_data object drm/rockchip: dw_hdmi: add dw-hdmi support for the rk3328
.../display/rockchip/dw_hdmi-rockchip.txt | 3 + drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 4 +- drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 130 +++++++++++++++++- include/drm/bridge/dw_hdmi.h | 1 + 4 files changed, 134 insertions(+), 4 deletions(-)
In some IP implementations the reading of the phy-type may be broken. One example are the Rockchip rk3228 and rk3328 socs that use a separate vendor-type phy from Innosilicon but still report the HDMI20_TX type.
So allow the glue driver to force the vendor-phy for these cases. In the future it may be necessary to allow forcing other types, but for now we'll keep it simply to the case actually seen in the wild.
changes in v3: - only allow forcing vendor type, as suggested by Laurent
Signed-off-by: Heiko Stuebner heiko@sntech.de Tested-by: Robin Murphy robin.murphy@arm.com --- drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 4 +++- include/drm/bridge/dw_hdmi.h | 1 + 2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index 5971976284bf..ac37c50d6c4b 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c @@ -2205,7 +2205,9 @@ static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi) unsigned int i; u8 phy_type;
- phy_type = hdmi_readb(hdmi, HDMI_CONFIG2_ID); + phy_type = hdmi->plat_data->phy_force_vendor ? + DW_HDMI_PHY_VENDOR_PHY : + hdmi_readb(hdmi, HDMI_CONFIG2_ID);
if (phy_type == DW_HDMI_PHY_VENDOR_PHY) { /* Vendor PHYs require support from the glue layer. */ diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h index ccb5aa8468e0..6ef3236bb6dd 100644 --- a/include/drm/bridge/dw_hdmi.h +++ b/include/drm/bridge/dw_hdmi.h @@ -133,6 +133,7 @@ struct dw_hdmi_plat_data { const struct dw_hdmi_phy_ops *phy_ops; const char *phy_name; void *phy_data; + bool phy_force_vendor;
/* Synopsys PHY support */ const struct dw_hdmi_mpll_config *mpll_cfg;
So far we always encountered socs with 2 output crtcs needing the driver to tell the hdmi block which output to connect to. But there also exist socs with only one crtc like the rk3228, rk3328 and rk3368.
So adapt the register field to simply carry a negative value to signal that no output-switching is necessary.
Signed-off-by: Heiko Stuebner heiko@sntech.de Tested-by: Robin Murphy robin.murphy@arm.com
changes in v3: - fixed wording issue found by Robin Murphy --- drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index 11309a2a4e43..b09c3531305b 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -36,7 +36,7 @@ * @lcdsel_lit: reg value of selecting vop little for HDMI */ struct rockchip_hdmi_chip_data { - u32 lcdsel_grf_reg; + int lcdsel_grf_reg; u32 lcdsel_big; u32 lcdsel_lit; }; @@ -245,6 +245,9 @@ static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder) u32 val; int ret;
+ if (hdmi->chip_data->lcdsel_grf_reg < 0) + return; + ret = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder); if (ret) val = hdmi->chip_data->lcdsel_lit;
Some newer Rockchip SoCs use an Innosilicon hdmiphy accessed via general mmio, so allow these to be referenced via the regular phy interfaces and therefore add optional phy-related properties to the binding.
Signed-off-by: Heiko Stuebner heiko@sntech.de Reviewed-by: Rob Herring robh@kernel.org --- .../devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt index adc94fc3c9f8..937bfb472e1d 100644 --- a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt +++ b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt @@ -34,6 +34,8 @@ Optional properties - clock-names: May contain "cec" as defined in dw_hdmi.txt. - clock-names: May contain "grf", power for grf io. - clock-names: May contain "vpll", external clock for some hdmi phy. +- phys: from general PHY binding: the phandle for the PHY device. +- phy-names: Should be "hdmi" if phys references an external phy.
Example:
Some variants of the dw-hdmi on Rockchip socs use a separate phy block accessed via the generic phy framework, so allow them to be included if such a phy reference is found.
Signed-off-by: Heiko Stuebner heiko@sntech.de Tested-by: Robin Murphy robin.murphy@arm.com --- drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index b09c3531305b..57e76dfd5f6d 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -11,6 +11,7 @@ #include <linux/mfd/syscon.h> #include <linux/module.h> #include <linux/platform_device.h> +#include <linux/phy/phy.h> #include <linux/regmap.h>
#include <drm/drm_of.h> @@ -49,6 +50,7 @@ struct rockchip_hdmi { struct clk *vpll_clk; struct clk *grf_clk; struct dw_hdmi *hdmi; + struct phy *phy; };
#define to_rockchip_hdmi(x) container_of(x, struct rockchip_hdmi, x) @@ -376,6 +378,14 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, return ret; }
+ hdmi->phy = devm_phy_optional_get(dev, "hdmi"); + if (IS_ERR(hdmi->phy)) { + ret = PTR_ERR(hdmi->phy); + if (ret != -EPROBE_DEFER) + DRM_DEV_ERROR(hdmi->dev, "failed to get phy\n"); + return ret; + } + drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs); drm_encoder_init(drm, encoder, &dw_hdmi_rockchip_encoder_funcs, DRM_MODE_ENCODER_TMDS, NULL);
When using special phy handling operations we'll often need access to the rockchip_hdmi struct.
As the chip-data that occupies the phy_data pointer initially gets assigned to the rockchip_hdmi struct, we can now re-use this phy_data pointer to hold the reference to the rockchip_hdmi struct and use this reference later on.
Inspiration for this comes from meson and sunxi dw-hdmi, which are using the same method.
Signed-off-by: Heiko Stuebner heiko@sntech.de Tested-by: Robin Murphy robin.murphy@arm.com
changes in v3: - reword commit message --- drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index 57e76dfd5f6d..19f002fa0a09 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -335,7 +335,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, void *data) { struct platform_device *pdev = to_platform_device(dev); - const struct dw_hdmi_plat_data *plat_data; + struct dw_hdmi_plat_data *plat_data; const struct of_device_id *match; struct drm_device *drm = data; struct drm_encoder *encoder; @@ -350,9 +350,14 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master, return -ENOMEM;
match = of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node); - plat_data = match->data; + plat_data = devm_kmemdup(&pdev->dev, match->data, + sizeof(*plat_data), GFP_KERNEL); + if (!plat_data) + return -ENOMEM; + hdmi->dev = &pdev->dev; hdmi->chip_data = plat_data->phy_data; + plat_data->phy_data = hdmi; encoder = &hdmi->encoder;
encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
The rk3328 uses a dw-hdmi controller with an external hdmi phy from Innosilicon which uses the generic phy framework for access. Add the necessary data and the compatible for the rk3328 to the rockchip dw-hdmi driver.
Signed-off-by: Heiko Stuebner heiko@sntech.de Tested-by: Robin Murphy robin.murphy@arm.com Acked-by: Rob Herring robh@kernel.org
changes in v3: - reword as suggested by Rob to show that it's a dw-hdmi + Inno phy --- .../display/rockchip/dw_hdmi-rockchip.txt | 1 + drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 106 ++++++++++++++++++ 2 files changed, 107 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt index 937bfb472e1d..39143424a474 100644 --- a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt +++ b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt @@ -13,6 +13,7 @@ Required properties:
- compatible: should be one of the following: "rockchip,rk3288-dw-hdmi" + "rockchip,rk3328-dw-hdmi" "rockchip,rk3399-dw-hdmi" - reg: See dw_hdmi.txt. - reg-io-width: See dw_hdmi.txt. Shall be 4. diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index 19f002fa0a09..237f31fd8403 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -25,6 +25,24 @@
#define RK3288_GRF_SOC_CON6 0x025C #define RK3288_HDMI_LCDC_SEL BIT(4) +#define RK3328_GRF_SOC_CON2 0x0408 + +#define RK3328_HDMI_SDAIN_MSK BIT(11) +#define RK3328_HDMI_SCLIN_MSK BIT(10) +#define RK3328_HDMI_HPD_IOE BIT(2) +#define RK3328_GRF_SOC_CON3 0x040c +/* need to be unset if hdmi or i2c should control voltage */ +#define RK3328_HDMI_SDA5V_GRF BIT(15) +#define RK3328_HDMI_SCL5V_GRF BIT(14) +#define RK3328_HDMI_HPD5V_GRF BIT(13) +#define RK3328_HDMI_CEC5V_GRF BIT(12) +#define RK3328_GRF_SOC_CON4 0x0410 +#define RK3328_HDMI_HPD_SARADC BIT(13) +#define RK3328_HDMI_CEC_5V BIT(11) +#define RK3328_HDMI_SDA_5V BIT(10) +#define RK3328_HDMI_SCL_5V BIT(9) +#define RK3328_HDMI_HPD_5V BIT(8) + #define RK3399_GRF_SOC_CON20 0x6250 #define RK3399_HDMI_LCDC_SEL BIT(6)
@@ -292,6 +310,68 @@ static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_fun .atomic_check = dw_hdmi_rockchip_encoder_atomic_check, };
+static int dw_hdmi_rockchip_genphy_init(struct dw_hdmi *dw_hdmi, void *data, + struct drm_display_mode *mode) +{ + struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; + + return phy_power_on(hdmi->phy); +} + +static void dw_hdmi_rockchip_genphy_disable(struct dw_hdmi *dw_hdmi, void *data) +{ + struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; + + phy_power_off(hdmi->phy); +} + +static enum drm_connector_status +dw_hdmi_rk3328_read_hpd(struct dw_hdmi *dw_hdmi, void *data) +{ + struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; + enum drm_connector_status status; + + status = dw_hdmi_phy_read_hpd(dw_hdmi, data); + + if (status == connector_status_connected) + regmap_write(hdmi->regmap, + RK3328_GRF_SOC_CON4, + HIWORD_UPDATE(RK3328_HDMI_CEC_5V | RK3328_HDMI_SDA_5V | + RK3328_HDMI_SCL_5V, + RK3328_HDMI_CEC_5V | RK3328_HDMI_SDA_5V | + RK3328_HDMI_SCL_5V)); + else + regmap_write(hdmi->regmap, + RK3328_GRF_SOC_CON4, + HIWORD_UPDATE(0, + RK3328_HDMI_CEC_5V | RK3328_HDMI_SDA_5V | + RK3328_HDMI_SCL_5V)); + return status; +} + +static void dw_hdmi_rk3328_setup_hpd(struct dw_hdmi *dw_hdmi, void *data) +{ + struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data; + + dw_hdmi_phy_setup_hpd(dw_hdmi, data); + + /* Enable and map pins to 3V grf-controlled io-voltage */ + regmap_write(hdmi->regmap, + RK3328_GRF_SOC_CON4, + HIWORD_UPDATE(0, RK3328_HDMI_HPD_SARADC | RK3328_HDMI_CEC_5V | + RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V | + RK3328_HDMI_HPD_5V)); + regmap_write(hdmi->regmap, + RK3328_GRF_SOC_CON3, + HIWORD_UPDATE(0, RK3328_HDMI_SDA5V_GRF | RK3328_HDMI_SCL5V_GRF | + RK3328_HDMI_HPD5V_GRF | RK3328_HDMI_CEC5V_GRF)); + regmap_write(hdmi->regmap, + RK3328_GRF_SOC_CON2, + HIWORD_UPDATE(RK3328_HDMI_SDAIN_MSK | RK3328_HDMI_SCLIN_MSK, + RK3328_HDMI_SDAIN_MSK | RK3328_HDMI_SCLIN_MSK | + RK3328_HDMI_HPD_IOE)); +} + static struct rockchip_hdmi_chip_data rk3288_chip_data = { .lcdsel_grf_reg = RK3288_GRF_SOC_CON6, .lcdsel_big = HIWORD_UPDATE(0, RK3288_HDMI_LCDC_SEL), @@ -306,6 +386,29 @@ static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = { .phy_data = &rk3288_chip_data, };
+static const struct dw_hdmi_phy_ops rk3328_hdmi_phy_ops = { + .init = dw_hdmi_rockchip_genphy_init, + .disable = dw_hdmi_rockchip_genphy_disable, + .read_hpd = dw_hdmi_rk3328_read_hpd, + .update_hpd = dw_hdmi_phy_update_hpd, + .setup_hpd = dw_hdmi_rk3328_setup_hpd, +}; + +static struct rockchip_hdmi_chip_data rk3328_chip_data = { + .lcdsel_grf_reg = -1, +}; + +static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = { + .mode_valid = dw_hdmi_rockchip_mode_valid, + .mpll_cfg = rockchip_mpll_cfg, + .cur_ctr = rockchip_cur_ctr, + .phy_config = rockchip_phy_config, + .phy_data = &rk3328_chip_data, + .phy_ops = &rk3328_hdmi_phy_ops, + .phy_name = "inno_dw_hdmi_phy2", + .phy_force_vendor = true, +}; + static struct rockchip_hdmi_chip_data rk3399_chip_data = { .lcdsel_grf_reg = RK3399_GRF_SOC_CON20, .lcdsel_big = HIWORD_UPDATE(0, RK3399_HDMI_LCDC_SEL), @@ -324,6 +427,9 @@ static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = { { .compatible = "rockchip,rk3288-dw-hdmi", .data = &rk3288_hdmi_drv_data }, + { .compatible = "rockchip,rk3328-dw-hdmi", + .data = &rk3328_hdmi_drv_data + }, { .compatible = "rockchip,rk3399-dw-hdmi", .data = &rk3399_hdmi_drv_data },
Hi Heiko,
CEC is not working when CEC 5V is enabled
On 2018-09-10 11:22, Heiko Stuebner wrote:
The rk3328 uses a dw-hdmi controller with an external hdmi phy from Innosilicon which uses the generic phy framework for access. Add the necessary data and the compatible for the rk3328 to the rockchip dw-hdmi driver.
Signed-off-by: Heiko Stuebner heiko@sntech.de Tested-by: Robin Murphy robin.murphy@arm.com Acked-by: Rob Herring robh@kernel.org
changes in v3:
- reword as suggested by Rob to show that it's a dw-hdmi + Inno phy
.../display/rockchip/dw_hdmi-rockchip.txt | 1 + drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 106 ++++++++++++++++++ 2 files changed, 107 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt index 937bfb472e1d..39143424a474 100644 --- a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt +++ b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt @@ -13,6 +13,7 @@ Required properties:
- compatible: should be one of the following: "rockchip,rk3288-dw-hdmi"
"rockchip,rk3328-dw-hdmi"
- reg: See dw_hdmi.txt.
- reg-io-width: See dw_hdmi.txt. Shall be 4.
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index 19f002fa0a09..237f31fd8403 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -25,6 +25,24 @@
#define RK3288_GRF_SOC_CON6 0x025C #define RK3288_HDMI_LCDC_SEL BIT(4) +#define RK3328_GRF_SOC_CON2 0x0408
+#define RK3328_HDMI_SDAIN_MSK BIT(11) +#define RK3328_HDMI_SCLIN_MSK BIT(10) +#define RK3328_HDMI_HPD_IOE BIT(2) +#define RK3328_GRF_SOC_CON3 0x040c +/* need to be unset if hdmi or i2c should control voltage */ +#define RK3328_HDMI_SDA5V_GRF BIT(15) +#define RK3328_HDMI_SCL5V_GRF BIT(14) +#define RK3328_HDMI_HPD5V_GRF BIT(13) +#define RK3328_HDMI_CEC5V_GRF BIT(12) +#define RK3328_GRF_SOC_CON4 0x0410 +#define RK3328_HDMI_HPD_SARADC BIT(13) +#define RK3328_HDMI_CEC_5V BIT(11) +#define RK3328_HDMI_SDA_5V BIT(10) +#define RK3328_HDMI_SCL_5V BIT(9) +#define RK3328_HDMI_HPD_5V BIT(8)
#define RK3399_GRF_SOC_CON20 0x6250 #define RK3399_HDMI_LCDC_SEL BIT(6)
@@ -292,6 +310,68 @@ static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_fun .atomic_check = dw_hdmi_rockchip_encoder_atomic_check, };
+static int dw_hdmi_rockchip_genphy_init(struct dw_hdmi *dw_hdmi, void *data,
struct drm_display_mode *mode)+{
- struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
- return phy_power_on(hdmi->phy);
+}
+static void dw_hdmi_rockchip_genphy_disable(struct dw_hdmi *dw_hdmi, void *data) +{
- struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
- phy_power_off(hdmi->phy);
+}
+static enum drm_connector_status +dw_hdmi_rk3328_read_hpd(struct dw_hdmi *dw_hdmi, void *data) +{
- struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
- enum drm_connector_status status;
- status = dw_hdmi_phy_read_hpd(dw_hdmi, data);
- if (status == connector_status_connected)
regmap_write(hdmi->regmap,RK3328_GRF_SOC_CON4,HIWORD_UPDATE(RK3328_HDMI_CEC_5V | RK3328_HDMI_SDA_5V |RK3328_HDMI_SCL_5V,RK3328_HDMI_CEC_5V | RK3328_HDMI_SDA_5V |RK3328_HDMI_SCL_5V));
This differs from BSP kernel and enable of CEC 5V stops CEC from working. BSP kernel do not set write enable bit for CEC 5V:
RK3328_IO_5V_DOMAIN ((7 << 9) | (3 << (9 + 16)))
https://github.com/Kwiboo/linux-rockchip/commit/e74ac6a3a581bcb7b2ac9f4d70cf... makes CEC work on v3 of this patch.
- else
regmap_write(hdmi->regmap,RK3328_GRF_SOC_CON4,HIWORD_UPDATE(0,RK3328_HDMI_CEC_5V | RK3328_HDMI_SDA_5V |RK3328_HDMI_SCL_5V));- return status;
+}
+static void dw_hdmi_rk3328_setup_hpd(struct dw_hdmi *dw_hdmi, void *data) +{
- struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
- dw_hdmi_phy_setup_hpd(dw_hdmi, data);
- /* Enable and map pins to 3V grf-controlled io-voltage */
- regmap_write(hdmi->regmap,
RK3328_GRF_SOC_CON4,HIWORD_UPDATE(0, RK3328_HDMI_HPD_SARADC | RK3328_HDMI_CEC_5V |RK3328_HDMI_SDA_5V | RK3328_HDMI_SCL_5V |RK3328_HDMI_HPD_5V));- regmap_write(hdmi->regmap,
RK3328_GRF_SOC_CON3,HIWORD_UPDATE(0, RK3328_HDMI_SDA5V_GRF | RK3328_HDMI_SCL5V_GRF |RK3328_HDMI_HPD5V_GRF | RK3328_HDMI_CEC5V_GRF));- regmap_write(hdmi->regmap,
RK3328_GRF_SOC_CON2,HIWORD_UPDATE(RK3328_HDMI_SDAIN_MSK | RK3328_HDMI_SCLIN_MSK,RK3328_HDMI_SDAIN_MSK | RK3328_HDMI_SCLIN_MSK |RK3328_HDMI_HPD_IOE));+}
static struct rockchip_hdmi_chip_data rk3288_chip_data = { .lcdsel_grf_reg = RK3288_GRF_SOC_CON6, .lcdsel_big = HIWORD_UPDATE(0, RK3288_HDMI_LCDC_SEL), @@ -306,6 +386,29 @@ static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = { .phy_data = &rk3288_chip_data, };
+static const struct dw_hdmi_phy_ops rk3328_hdmi_phy_ops = {
- .init = dw_hdmi_rockchip_genphy_init,
- .disable = dw_hdmi_rockchip_genphy_disable,
- .read_hpd = dw_hdmi_rk3328_read_hpd,
- .update_hpd = dw_hdmi_phy_update_hpd,
- .setup_hpd = dw_hdmi_rk3328_setup_hpd,
+};
+static struct rockchip_hdmi_chip_data rk3328_chip_data = {
- .lcdsel_grf_reg = -1,
+};
+static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = {
- .mode_valid = dw_hdmi_rockchip_mode_valid,
- .mpll_cfg = rockchip_mpll_cfg,
- .cur_ctr = rockchip_cur_ctr,
- .phy_config = rockchip_phy_config,
- .phy_data = &rk3328_chip_data,
- .phy_ops = &rk3328_hdmi_phy_ops,
- .phy_name = "inno_dw_hdmi_phy2",
- .phy_force_vendor = true,
+};
static struct rockchip_hdmi_chip_data rk3399_chip_data = { .lcdsel_grf_reg = RK3399_GRF_SOC_CON20, .lcdsel_big = HIWORD_UPDATE(0, RK3399_HDMI_LCDC_SEL), @@ -324,6 +427,9 @@ static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = { { .compatible = "rockchip,rk3288-dw-hdmi", .data = &rk3288_hdmi_drv_data },
- { .compatible = "rockchip,rk3328-dw-hdmi",
.data = &rk3328_hdmi_drv_data- }, { .compatible = "rockchip,rk3399-dw-hdmi", .data = &rk3399_hdmi_drv_data },
Am Montag, 10. September 2018, 17:15:46 CEST schrieb Jonas Karlman:
Hi Heiko,
CEC is not working when CEC 5V is enabled
On 2018-09-10 11:22, Heiko Stuebner wrote:
The rk3328 uses a dw-hdmi controller with an external hdmi phy from Innosilicon which uses the generic phy framework for access. Add the necessary data and the compatible for the rk3328 to the rockchip dw-hdmi driver.
Signed-off-by: Heiko Stuebner heiko@sntech.de Tested-by: Robin Murphy robin.murphy@arm.com Acked-by: Rob Herring robh@kernel.org
changes in v3:
- reword as suggested by Rob to show that it's a dw-hdmi + Inno phy
.../display/rockchip/dw_hdmi-rockchip.txt | 1 + drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 106 ++++++++++++++++++ 2 files changed, 107 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt index 937bfb472e1d..39143424a474 100644 --- a/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt +++ b/Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt @@ -13,6 +13,7 @@ Required properties:
- compatible: should be one of the following: "rockchip,rk3288-dw-hdmi"
"rockchip,rk3328-dw-hdmi"
- reg: See dw_hdmi.txt.
- reg-io-width: See dw_hdmi.txt. Shall be 4.
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index 19f002fa0a09..237f31fd8403 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -25,6 +25,24 @@
#define RK3288_GRF_SOC_CON6 0x025C #define RK3288_HDMI_LCDC_SEL BIT(4) +#define RK3328_GRF_SOC_CON2 0x0408
+#define RK3328_HDMI_SDAIN_MSK BIT(11) +#define RK3328_HDMI_SCLIN_MSK BIT(10) +#define RK3328_HDMI_HPD_IOE BIT(2) +#define RK3328_GRF_SOC_CON3 0x040c +/* need to be unset if hdmi or i2c should control voltage */ +#define RK3328_HDMI_SDA5V_GRF BIT(15) +#define RK3328_HDMI_SCL5V_GRF BIT(14) +#define RK3328_HDMI_HPD5V_GRF BIT(13) +#define RK3328_HDMI_CEC5V_GRF BIT(12) +#define RK3328_GRF_SOC_CON4 0x0410 +#define RK3328_HDMI_HPD_SARADC BIT(13) +#define RK3328_HDMI_CEC_5V BIT(11) +#define RK3328_HDMI_SDA_5V BIT(10) +#define RK3328_HDMI_SCL_5V BIT(9) +#define RK3328_HDMI_HPD_5V BIT(8)
#define RK3399_GRF_SOC_CON20 0x6250 #define RK3399_HDMI_LCDC_SEL BIT(6)
@@ -292,6 +310,68 @@ static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_fun .atomic_check = dw_hdmi_rockchip_encoder_atomic_check, };
+static int dw_hdmi_rockchip_genphy_init(struct dw_hdmi *dw_hdmi, void *data,
struct drm_display_mode *mode)+{
- struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
- return phy_power_on(hdmi->phy);
+}
+static void dw_hdmi_rockchip_genphy_disable(struct dw_hdmi *dw_hdmi, void *data) +{
- struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
- phy_power_off(hdmi->phy);
+}
+static enum drm_connector_status +dw_hdmi_rk3328_read_hpd(struct dw_hdmi *dw_hdmi, void *data) +{
- struct rockchip_hdmi *hdmi = (struct rockchip_hdmi *)data;
- enum drm_connector_status status;
- status = dw_hdmi_phy_read_hpd(dw_hdmi, data);
- if (status == connector_status_connected)
regmap_write(hdmi->regmap,RK3328_GRF_SOC_CON4,HIWORD_UPDATE(RK3328_HDMI_CEC_5V | RK3328_HDMI_SDA_5V |RK3328_HDMI_SCL_5V,RK3328_HDMI_CEC_5V | RK3328_HDMI_SDA_5V |RK3328_HDMI_SCL_5V));This differs from BSP kernel and enable of CEC 5V stops CEC from working. BSP kernel do not set write enable bit for CEC 5V:
RK3328_IO_5V_DOMAIN ((7 << 9) | (3 << (9 + 16)))
https://github.com/Kwiboo/linux-rockchip/commit/e74ac6a3a581bcb7b2ac9f4d70cf... makes CEC work on v3 of this patch.
thanks for checking the cec functionality. I've incorporated your change and sent off v6. Maybe you can take another look and possible provide some Tested-by (or even Reviewed-by/Acked-by) tags? :-)
Thanks Heiko
dri-devel@lists.freedesktop.org
-
Heiko Stuebner -
Jonas Karlman