dither 6 setting is missed in a6b7c98afdca bit 1 is lfsr_en( "Enables LFSR-type dithering"), need enable bit 2 is rdither_en(Enables running order dithering), need disable

Fixes: a6b7c98afdca(drm/mediatek: add mtk_dither_set_common()) Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Change-Id: I30258dd4129d17fb7d94b1714d78bc133e88338e --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 3 +++ 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 99cbf44463e4..33e8789fde8a 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -26,6 +26,8 @@ #define DISP_OD_CFG 0x0020 #define DISP_OD_SIZE 0x0030 #define DISP_DITHER_5 0x0114 +#define DISP_DITHER_6 0x0118 +#define LFSR_EN BIT(1) #define DISP_DITHER_7 0x011c #define DISP_DITHER_15 0x013c #define DISP_DITHER_16 0x0140 @@ -135,6 +137,7 @@ void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,

if (bpc >= MTK_MIN_BPC) { mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_5); + mtk_ddp_write_mask(cmdq_pkt, LFSR_EN, cmdq_reg, regs, DISP_DITHER_6, LFSR_EN); mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_7); mtk_ddp_write(cmdq_pkt, DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |