The vsync length should be 10 lines, as specified in the data sheet. This gets the actual refresh rate closer to nominal 60 Hz given the 9 MHz pixel clock.
Signed-off-by: Philipp Zabel p.zabel@pengutronix.de --- drivers/gpu/drm/panel/panel-simple.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index 474fa759e06ec..fd21ca799be8d 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -1017,8 +1017,8 @@ static const struct drm_display_mode innolux_at043tn24_mode = { .htotal = 480 + 2 + 41 + 2, .vdisplay = 272, .vsync_start = 272 + 2, - .vsync_end = 272 + 2 + 11, - .vtotal = 272 + 2 + 11 + 2, + .vsync_end = 272 + 2 + 10, + .vtotal = 272 + 2 + 10 + 2, .vrefresh = 60, .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, };
For LCD interface controllers that support configuring polarity of pixel clock and data enable signal, specify bus flags in the panel descriptor.
Signed-off-by: Philipp Zabel p.zabel@pengutronix.de --- drivers/gpu/drm/panel/panel-simple.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index fd21ca799be8d..30944d006bf1c 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -1032,6 +1032,7 @@ static const struct panel_desc innolux_at043tn24 = { .height = 54, }, .bus_format = MEDIA_BUS_FMT_RGB888_1X24, + .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_POSEDGE, };
static const struct drm_display_mode innolux_at070tn92_mode = {
On Qua, 2017-10-11 at 14:59 +0200, Philipp Zabel wrote:
For LCD interface controllers that support configuring polarity of pixel clock and data enable signal, specify bus flags in the panel descriptor.
Signed-off-by: Philipp Zabel p.zabel@pengutronix.de
Tested-by: Marco Franchi marco.franchi@nxp.com
The delays between video data and backlight enable and between backlight disable and end of video data are given as >= 160 ms in the datasheet.
Signed-off-by: Philipp Zabel p.zabel@pengutronix.de --- drivers/gpu/drm/panel/panel-simple.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index 30944d006bf1c..0d0769874e382 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -1007,6 +1007,10 @@ static const struct panel_desc hitachi_tx23d38vm0caa = { .width = 195, .height = 117, }, + .delay = { + .enable = 160, + .disable = 160, + }, };
static const struct drm_display_mode innolux_at043tn24_mode = {
On Qua, 2017-10-11 at 14:59 +0200, Philipp Zabel wrote:
The delays between video data and backlight enable and between backlight disable and end of video data are given as >= 160 ms in the datasheet.
Signed-off-by: Philipp Zabel p.zabel@pengutronix.de
Tested-by: Marco Franchi marco.franchi@nxp.com
Hi Philipp,
On Qua, 2017-10-11 at 14:59 +0200, Philipp Zabel wrote:
The vsync length should be 10 lines, as specified in the data sheet. This gets the actual refresh rate closer to nominal 60 Hz given the 9 MHz pixel clock.
Signed-off-by: Philipp Zabel p.zabel@pengutronix.de
Thank you for all these fixes.
Tested-by: Marco Franchi marco.franchi@nxp.com
dri-devel@lists.freedesktop.org
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Marco Franchi -
Philipp Zabel