These patches enable packed format YUV422-Y210, Y212 and Y216 for 10, 12 and 16 bit respectively for ICL.
For user space component IGT:WIP
v2: addressed review comments of mahesh and alexandru hdr handling of these 64 bit pixel format not inscope of this series
Vidya Srinivas (4): drm: Add Y210, Y212, Y216 format definitions and fourcc drm/i915/icl: Add Y210, Y212, Y216 plane control definitions drm/i915/icl: Preparations for enabling Y210, Y212, Y216 formats drm/i915/icl: Enable Y210, Y212, Y216 format for primary and sprite planes
drivers/gpu/drm/drm_fourcc.c | 3 +++ drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_display.c | 40 ++++++++++++++++++++++++++++++++++-- drivers/gpu/drm/i915/intel_sprite.c | 25 ++++++++++++++++++++-- include/uapi/drm/drm_fourcc.h | 8 ++++++++ 5 files changed, 75 insertions(+), 4 deletions(-)
From: Vidya Srinivas vidya.srinivas@intel.com
The following pixel formats are packed format that follows 4:2:2 chroma sampling. For memory represenation each component is allocated 16 bits each. Thus each pixel occupies a DWORD.
Y210:Valid data occupies MSB 10 bits. LSB 6 bits are filled with zeroes. Y212:Valid data occupies MSB 12 bits. LSB 4 bits are filled with zeroes. Y216:Valid data occupies 16 bits, doesn't require any padding bits.
First 16 bits stores the Y value and the next 16 bits stores one of the chroma samples alternatively. The first luma sample will be accompanied by first U sample and second luma sample is accompanied by the first V sample.
v2: is_yuv setted to true (mahesh) different order of yuv samples (mahesh): still update from hardware team pending change in comment (alexandru)
Signed-off-by: Swati Sharma swati2.sharma@intel.com Signed-off-by: Vidya Srinivas vidya.srinivas@intel.com --- drivers/gpu/drm/drm_fourcc.c | 3 +++ include/uapi/drm/drm_fourcc.h | 8 ++++++++ 2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c index be1d6aa..143c26a 100644 --- a/drivers/gpu/drm/drm_fourcc.c +++ b/drivers/gpu/drm/drm_fourcc.c @@ -190,6 +190,9 @@ const struct drm_format_info *__drm_format_info(u32 format) { .format = DRM_FORMAT_UYVY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true }, { .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true }, { .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true, .is_yuv = true }, + { .format = DRM_FORMAT_Y210, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true }, + { .format = DRM_FORMAT_Y212, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true }, + { .format = DRM_FORMAT_Y216, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true }, };
unsigned int i; diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 139632b..95118cc 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -153,6 +153,14 @@ #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
/* + * Y2xx indicate for each component, xx valid data occupy msb + * 16-xx padding occupy lsb + */ +#define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Y0:Cb0:Y1:Cr1 10:10:10:10 little endian */ +#define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Y0:Cb0:Y1:Cr1 12:12:12:12 little endian */ +#define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Y0:Cb0:Y1:Cr1 16:16:16:16 little endian */ + +/* * 2 plane RGB + A * index 0 = RGB plane, same format as the corresponding non _A8 format has * index 1 = A plane, [7:0] A
On 12.09.2018 13:32, Swati Sharma wrote:
From: Vidya Srinivas vidya.srinivas@intel.com
The following pixel formats are packed format that follows 4:2:2 chroma sampling. For memory represenation each component is allocated 16 bits each. Thus each pixel occupies a DWORD.
Just to be clear I wouldn't use 'DWORD' here but if it's 64 bits bits call it so. Not a big issue as its just in the patch comment but still.
Y210:Valid data occupies MSB 10 bits. LSB 6 bits are filled with zeroes. Y212:Valid data occupies MSB 12 bits. LSB 4 bits are filled with zeroes. Y216:Valid data occupies 16 bits, doesn't require any padding bits.
First 16 bits stores the Y value and the next 16 bits stores one of the chroma samples alternatively. The first luma sample will be accompanied by first U sample and second luma sample is accompanied by the first V sample.
v2: is_yuv setted to true (mahesh) different order of yuv samples (mahesh): still update from hardware team pending change in comment (alexandru)
Signed-off-by: Swati Sharma swati2.sharma@intel.com Signed-off-by: Vidya Srinivas vidya.srinivas@intel.com
drivers/gpu/drm/drm_fourcc.c | 3 +++ include/uapi/drm/drm_fourcc.h | 8 ++++++++ 2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c index be1d6aa..143c26a 100644 --- a/drivers/gpu/drm/drm_fourcc.c +++ b/drivers/gpu/drm/drm_fourcc.c @@ -190,6 +190,9 @@ const struct drm_format_info *__drm_format_info(u32 format) { .format = DRM_FORMAT_UYVY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true }, { .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true }, { .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true, .is_yuv = true },
{ .format = DRM_FORMAT_Y210, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },{ .format = DRM_FORMAT_Y212, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },{ .format = DRM_FORMAT_Y216, .depth = 0, .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },};
unsigned int i;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 139632b..95118cc 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -153,6 +153,14 @@ #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
/*
- Y2xx indicate for each component, xx valid data occupy msb
- 16-xx padding occupy lsb
- */
+#define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Y0:Cb0:Y1:Cr1 10:10:10:10 little endian */ +#define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Y0:Cb0:Y1:Cr1 12:12:12:12 little endian */ +#define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Y0:Cb0:Y1:Cr1 16:16:16:16 little endian */
I think what Alexandru-Cosmin Gheorghe meant with earlier review comment is these defines should be better explained here in part which will be visible in header file. Looking how other formats have been commented this would probably be something along the lines of
#define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Y0:x:Cb0:x:Y1:x:Cr1:x 10:6:10:6:10:6:10:6 little endian */
or something.
/Juha-Pekka
+/*
- 2 plane RGB + A
- index 0 = RGB plane, same format as the corresponding non _A8 format has
- index 1 = A plane, [7:0] A
From: Vidya Srinivas vidya.srinivas@intel.com
Added needed plane control flag definitions for Y210, Y212 and Y216 formats.
Signed-off-by: Swati Sharma swati2.sharma@intel.com Signed-off-by: Vidya Srinivas vidya.srinivas@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c80e569..d90d51c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6506,6 +6506,9 @@ enum { #define PLANE_CTL_FORMAT_RGB_565 (14 << 24) #define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23) #define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) /* Pre-GLK */ +#define PLANE_CTL_FORMAT_Y210 (1 << 23) +#define PLANE_CTL_FORMAT_Y212 (3 << 23) +#define PLANE_CTL_FORMAT_Y216 (5 << 23) #define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21) #define PLANE_CTL_KEY_ENABLE_SOURCE (1 << 21) #define PLANE_CTL_KEY_ENABLE_DESTINATION (2 << 21)
On 12.09.2018 13:32, Swati Sharma wrote:
From: Vidya Srinivas vidya.srinivas@intel.com
Added needed plane control flag definitions for Y210, Y212 and Y216 formats.
Signed-off-by: Swati Sharma swati2.sharma@intel.com Signed-off-by: Vidya Srinivas vidya.srinivas@intel.com
drivers/gpu/drm/i915/i915_reg.h | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c80e569..d90d51c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6506,6 +6506,9 @@ enum { #define PLANE_CTL_FORMAT_RGB_565 (14 << 24) #define ICL_PLANE_CTL_FORMAT_MASK (0x1f << 23) #define PLANE_CTL_PIPE_CSC_ENABLE (1 << 23) /* Pre-GLK */ +#define PLANE_CTL_FORMAT_Y210 (1 << 23) +#define PLANE_CTL_FORMAT_Y212 (3 << 23) +#define PLANE_CTL_FORMAT_Y216 (5 << 23) #define PLANE_CTL_KEY_ENABLE_MASK (0x3 << 21) #define PLANE_CTL_KEY_ENABLE_SOURCE (1 << 21) #define PLANE_CTL_KEY_ENABLE_DESTINATION (2 << 21)
Reviewed-by: Juha-Pekka Heikkila juhapekka.heikkila@gmail.com
From: Vidya Srinivas vidya.srinivas@intel.com
Signed-off-by: Swati Sharma swati2.sharma@intel.com Signed-off-by: Vidya Srinivas vidya.srinivas@intel.com --- drivers/gpu/drm/i915/intel_display.c | 15 +++++++++++++++ drivers/gpu/drm/i915/intel_sprite.c | 3 +++ 2 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 2b77d93..7c68a0d 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3512,6 +3512,12 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format) return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; case DRM_FORMAT_NV12: return PLANE_CTL_FORMAT_NV12; + case DRM_FORMAT_Y210: + return PLANE_CTL_FORMAT_Y210; + case DRM_FORMAT_Y212: + return PLANE_CTL_FORMAT_Y212; + case DRM_FORMAT_Y216: + return PLANE_CTL_FORMAT_Y216; default: MISSING_CASE(pixel_format); } @@ -4960,6 +4966,9 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, case DRM_FORMAT_UYVY: case DRM_FORMAT_VYUY: case DRM_FORMAT_NV12: + case DRM_FORMAT_Y210: + case DRM_FORMAT_Y212: + case DRM_FORMAT_Y216: break; default: DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n", @@ -13422,6 +13431,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane, case DRM_FORMAT_YVYU: case DRM_FORMAT_UYVY: case DRM_FORMAT_VYUY: + case DRM_FORMAT_Y210: + case DRM_FORMAT_Y212: + case DRM_FORMAT_Y216: case DRM_FORMAT_NV12: if (modifier == I915_FORMAT_MOD_Yf_TILED) return true; @@ -14551,6 +14563,9 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, case DRM_FORMAT_UYVY: case DRM_FORMAT_YVYU: case DRM_FORMAT_VYUY: + case DRM_FORMAT_Y210: + case DRM_FORMAT_Y212: + case DRM_FORMAT_Y216: if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) { DRM_DEBUG_KMS("unsupported pixel format: %s\n", drm_get_format_name(mode_cmd->pixel_format, &format_name)); diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 9600ccf..f7e2768 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -1419,6 +1419,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane, case DRM_FORMAT_YVYU: case DRM_FORMAT_UYVY: case DRM_FORMAT_VYUY: + case DRM_FORMAT_Y210: + case DRM_FORMAT_Y212: + case DRM_FORMAT_Y216: case DRM_FORMAT_NV12: if (modifier == I915_FORMAT_MOD_Yf_TILED) return true;
Swati Sharma kirjoitti 12.9.2018 klo 13.32:
From: Vidya Srinivas vidya.srinivas@intel.com
Signed-off-by: Swati Sharma swati2.sharma@intel.com Signed-off-by: Vidya Srinivas vidya.srinivas@intel.com
drivers/gpu/drm/i915/intel_display.c | 15 +++++++++++++++ drivers/gpu/drm/i915/intel_sprite.c | 3 +++ 2 files changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 2b77d93..7c68a0d 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3512,6 +3512,12 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format) return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; case DRM_FORMAT_NV12: return PLANE_CTL_FORMAT_NV12;
- case DRM_FORMAT_Y210:
return PLANE_CTL_FORMAT_Y210;- case DRM_FORMAT_Y212:
return PLANE_CTL_FORMAT_Y212;- case DRM_FORMAT_Y216:
return PLANE_CTL_FORMAT_Y216;@@ -4960,6 +4966,9 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, case DRM_FORMAT_UYVY: case DRM_FORMAT_VYUY: case DRM_FORMAT_NV12:
- case DRM_FORMAT_Y210:
- case DRM_FORMAT_Y212:
- case DRM_FORMAT_Y216: break; default: DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
@@ -13422,6 +13431,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane, case DRM_FORMAT_YVYU: case DRM_FORMAT_UYVY: case DRM_FORMAT_VYUY:
- case DRM_FORMAT_Y210:
- case DRM_FORMAT_Y212:
- case DRM_FORMAT_Y216: case DRM_FORMAT_NV12: if (modifier == I915_FORMAT_MOD_Yf_TILED) return true;
@@ -14551,6 +14563,9 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, case DRM_FORMAT_UYVY: case DRM_FORMAT_YVYU: case DRM_FORMAT_VYUY:
- case DRM_FORMAT_Y210:
- case DRM_FORMAT_Y212:
- case DRM_FORMAT_Y216: if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) { DRM_DEBUG_KMS("unsupported pixel format: %s\n", drm_get_format_name(mode_cmd->pixel_format, &format_name));
This is wrong place for these cases. These three new YUV formats are available on ICL+. You'll need case handling which checks if INTEL_GEN(dev_priv) < 11.
/Juha-Pekka
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 9600ccf..f7e2768 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -1419,6 +1419,9 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane, case DRM_FORMAT_YVYU: case DRM_FORMAT_UYVY: case DRM_FORMAT_VYUY:
- case DRM_FORMAT_Y210:
- case DRM_FORMAT_Y212:
- case DRM_FORMAT_Y216: case DRM_FORMAT_NV12: if (modifier == I915_FORMAT_MOD_Yf_TILED) return true;
From: Vidya Srinivas vidya.srinivas@intel.com
In this patch, a list for icl specific pixel formats is created in which Y210, Y212 and Y216 pixel formats are added along with legacy pixel formats for primary and sprite plane.
Signed-off-by: Swati Sharma swati2.sharma@intel.com Signed-off-by: Vidya Srinivas vidya.srinivas@intel.com --- drivers/gpu/drm/i915/intel_display.c | 25 +++++++++++++++++++++++-- drivers/gpu/drm/i915/intel_sprite.c | 22 ++++++++++++++++++++-- 2 files changed, 43 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 7c68a0d..f341cbd 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -105,6 +105,24 @@ DRM_FORMAT_NV12, };
+static const uint32_t icl_primary_formats[] = { + DRM_FORMAT_C8, + DRM_FORMAT_RGB565, + DRM_FORMAT_XRGB8888, + DRM_FORMAT_XBGR8888, + DRM_FORMAT_ARGB8888, + DRM_FORMAT_ABGR8888, + DRM_FORMAT_XRGB2101010, + DRM_FORMAT_XBGR2101010, + DRM_FORMAT_YUYV, + DRM_FORMAT_YVYU, + DRM_FORMAT_UYVY, + DRM_FORMAT_VYUY, + DRM_FORMAT_Y210, + DRM_FORMAT_Y212, + DRM_FORMAT_Y216, +}; + static const uint64_t skl_format_modifiers_noccs[] = { I915_FORMAT_MOD_Yf_TILED, I915_FORMAT_MOD_Y_TILED, @@ -13725,8 +13743,11 @@ bool skl_plane_has_planar(struct drm_i915_private *dev_priv, if (INTEL_GEN(dev_priv) >= 9) { primary->has_ccs = skl_plane_has_ccs(dev_priv, pipe, PLANE_PRIMARY); - - if (skl_plane_has_planar(dev_priv, pipe, PLANE_PRIMARY)) { + if (INTEL_GEN(dev_priv) >= 11) { + intel_primary_formats = icl_primary_formats; + num_formats = ARRAY_SIZE(icl_primary_formats); + } else if (skl_plane_has_planar(dev_priv, pipe, + PLANE_PRIMARY)) { intel_primary_formats = skl_pri_planar_formats; num_formats = ARRAY_SIZE(skl_pri_planar_formats); } else { diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index f7e2768..2e61fe19 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -1281,6 +1281,21 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data, DRM_FORMAT_NV12, };
+static uint32_t icl_plane_formats[] = { + DRM_FORMAT_RGB565, + DRM_FORMAT_ABGR8888, + DRM_FORMAT_ARGB8888, + DRM_FORMAT_XBGR8888, + DRM_FORMAT_XRGB8888, + DRM_FORMAT_YUYV, + DRM_FORMAT_YVYU, + DRM_FORMAT_UYVY, + DRM_FORMAT_VYUY, + DRM_FORMAT_Y210, + DRM_FORMAT_Y212, + DRM_FORMAT_Y216, +}; + static const uint64_t skl_plane_format_modifiers_noccs[] = { I915_FORMAT_MOD_Yf_TILED, I915_FORMAT_MOD_Y_TILED, @@ -1536,8 +1551,11 @@ struct intel_plane * intel_plane->disable_plane = skl_disable_plane; intel_plane->get_hw_state = skl_plane_get_hw_state;
- if (skl_plane_has_planar(dev_priv, pipe, - PLANE_SPRITE0 + plane)) { + if (INTEL_GEN(dev_priv) >= 11) { + plane_formats = icl_plane_formats; + num_plane_formats = ARRAY_SIZE(icl_plane_formats); + } else if (skl_plane_has_planar(dev_priv, pipe, + PLANE_SPRITE0 + plane)) { plane_formats = skl_planar_formats; num_plane_formats = ARRAY_SIZE(skl_planar_formats); } else {
On 12.09.2018 13:32, Swati Sharma wrote:
From: Vidya Srinivas vidya.srinivas@intel.com
In this patch, a list for icl specific pixel formats is created in which Y210, Y212 and Y216 pixel formats are added along with legacy pixel formats for primary and sprite plane.
Signed-off-by: Swati Sharma swati2.sharma@intel.com Signed-off-by: Vidya Srinivas vidya.srinivas@intel.com
drivers/gpu/drm/i915/intel_display.c | 25 +++++++++++++++++++++++-- drivers/gpu/drm/i915/intel_sprite.c | 22 ++++++++++++++++++++-- 2 files changed, 43 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 7c68a0d..f341cbd 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -105,6 +105,24 @@ DRM_FORMAT_NV12, };
+static const uint32_t icl_primary_formats[] = {
- DRM_FORMAT_C8,
- DRM_FORMAT_RGB565,
- DRM_FORMAT_XRGB8888,
- DRM_FORMAT_XBGR8888,
- DRM_FORMAT_ARGB8888,
- DRM_FORMAT_ABGR8888,
- DRM_FORMAT_XRGB2101010,
- DRM_FORMAT_XBGR2101010,
- DRM_FORMAT_YUYV,
- DRM_FORMAT_YVYU,
- DRM_FORMAT_UYVY,
- DRM_FORMAT_VYUY,
- DRM_FORMAT_Y210,
- DRM_FORMAT_Y212,
- DRM_FORMAT_Y216,
+};
- static const uint64_t skl_format_modifiers_noccs[] = { I915_FORMAT_MOD_Yf_TILED, I915_FORMAT_MOD_Y_TILED,
@@ -13725,8 +13743,11 @@ bool skl_plane_has_planar(struct drm_i915_private *dev_priv, if (INTEL_GEN(dev_priv) >= 9) { primary->has_ccs = skl_plane_has_ccs(dev_priv, pipe, PLANE_PRIMARY);
if (skl_plane_has_planar(dev_priv, pipe, PLANE_PRIMARY)) {
if (INTEL_GEN(dev_priv) >= 11) {intel_primary_formats = icl_primary_formats;num_formats = ARRAY_SIZE(icl_primary_formats);} else if (skl_plane_has_planar(dev_priv, pipe,PLANE_PRIMARY)) {
Above doesn't look right. I think it could be written "if(gen>=11) {...} else if(gen>=9){...". Now it looks support for planar formats on ICL is totally skipped. As is inside skl_plane_has_planar(..) there's check if running on ICL no planar support is available but it is only until planar support for ICL is patched in. I suspect you are going to need icl_primary_formats[] as well as icl_pri_planar_formats[] in similar way as on SKL. It is similar issue below with changes for intel_sprite.c
/Juha-Pekka
intel_primary_formats = skl_pri_planar_formats; num_formats = ARRAY_SIZE(skl_pri_planar_formats); } else {diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index f7e2768..2e61fe19 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -1281,6 +1281,21 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data, DRM_FORMAT_NV12, };
+static uint32_t icl_plane_formats[] = {
- DRM_FORMAT_RGB565,
- DRM_FORMAT_ABGR8888,
- DRM_FORMAT_ARGB8888,
- DRM_FORMAT_XBGR8888,
- DRM_FORMAT_XRGB8888,
- DRM_FORMAT_YUYV,
- DRM_FORMAT_YVYU,
- DRM_FORMAT_UYVY,
- DRM_FORMAT_VYUY,
- DRM_FORMAT_Y210,
- DRM_FORMAT_Y212,
- DRM_FORMAT_Y216,
+};
- static const uint64_t skl_plane_format_modifiers_noccs[] = { I915_FORMAT_MOD_Yf_TILED, I915_FORMAT_MOD_Y_TILED,
@@ -1536,8 +1551,11 @@ struct intel_plane * intel_plane->disable_plane = skl_disable_plane; intel_plane->get_hw_state = skl_plane_get_hw_state;
if (skl_plane_has_planar(dev_priv, pipe,PLANE_SPRITE0 + plane)) {
if (INTEL_GEN(dev_priv) >= 11) {plane_formats = icl_plane_formats;num_plane_formats = ARRAY_SIZE(icl_plane_formats);} else if (skl_plane_has_planar(dev_priv, pipe,PLANE_SPRITE0 + plane)) { plane_formats = skl_planar_formats; num_plane_formats = ARRAY_SIZE(skl_planar_formats);
dri-devel@lists.freedesktop.org
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Juha-Pekka Heikkila -
Juha-Pekka Heikkilä
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Swati Sharma