Hi all,

On 02-11-18 12:44, Hans de Goede wrote:

The GOP sometimes initializes the DSI pclk at a (slightly) different freq then the pclk which we pick. intel_pipe_config_compare() allows for this by doing a fuzzy compare on the port_clock.

But the pclk difference not only results in the port_clock and base.adjusted_mode.crtc_clock clocks being a bit different, but also in us picking different dsi_pll register values matching the different pclk.

This commit makes us only do the dsi_pll register compare when the adjust parameter is false, so only from verify_crtc_state(), so that we correctly do a fast modeset at boot avoiding the screen going black for about 1 sec.

Signed-off-by: Hans de Goede hdegoede@redhat.com

Self-nack to this patch. This avoids the modeset on boot when booting with fastboot=1 but then on the first commit afterwards we get errors like these:

[ 6.330864] [drm:pipe_config_err [i915]] *ERROR* mismatch in dsi_pll.ctrl (expected 0x80040100, found 0x80080100) [ 6.330967] [drm:pipe_config_err [i915]] *ERROR* mismatch in dsi_pll.div (expected 0x000001aa, found 0x0000011a)

Followed by a backtrace caused by the I915_STATE_WARN at the end of verify_crtc_state triggering.

So I will brush of my previous patch to fix this, which reads the pclk picked by the GOP back and uses overrides the VBT one with that if it is close.

I believe I've a solution for not doing hw readback in intel_dsi_vbt.c, which was the largest objection last time I posted that series.

Regards,

Hans

---

drivers/gpu/drm/i915/intel_display.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index b219d5858160..82fa85df0fba 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -11759,8 +11759,10 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv, PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias); PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);

• PIPE_CONF_CHECK_X(dsi_pll.ctrl);
• PIPE_CONF_CHECK_X(dsi_pll.div);

• if (!adjust) {

• PIPE_CONF_CHECK_X(dsi_pll.ctrl);
  

• PIPE_CONF_CHECK_X(dsi_pll.div);
  

• }

  if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) PIPE_CONF_CHECK_I(pipe_bpp);