This patch add support for the Mediatek MT2712 DISP subsystem. MT2712 is base on MT8173, there are some difference as following: MT2712 support three disp output(two ovl and one rdma)
Change in v6: - Update commit message for the patch "drm/mediatek: Update the definition of connection from RDMA1 to DPI0"
Stu Hsieh (29): drm/mediatek: update dt-bindings for mt2712 drm/mediatek: support maximum 64 mutex mod drm/mediatek: add ddp component AAL1 drm/mediatek: add ddp component OD1 drm/mediatek: add ddp component PWM1 drm/mediatek: add ddp component PWM2 drm/mediatek: add component DPI1 drm/mediatek: add component DSI2 drm/mediatek: add component DSI3 drm/mediatek: add the DSI1 for component init condition drm/mediatek: add connection from OD1 to RDMA1 drm/mediatek: Update the definition of connection from RDMA1 to DPI0 drm/mediatek: add connection from RDMA0 to DPI0 drm/mediatek: add connection from RDMA0 to DSI2 drm/mediatek: add connection from RDMA0 to DSI3 drm/mediatek: add connection from RDMA1 to DPI1 drm/mediatek: add connection from RDMA1 to DSI1 drm/mediatek: add connection from RDMA1 to DSI2 drm/mediatek: add connection from RDMA1 to DSI3 drm/mediatek: add connection from RDMA2 to DPI0 drm/mediatek: add connection from RDMA2 to DPI1 drm/mediatek: add connection from RDMA2 to DSI1 drm/mediatek: add connection from RDMA2 to DSI2 drm/mediatek: add connection from RDMA2 to DSI3 drm/mediatek: add DPI1 support for mutex drm/mediatek: add DSI2 support for mutex drm/mediatek: add DSI3 support for mutex drm/mediatek: add third ddp path drm/mediatek: Add support for mediatek SOC MT2712
.../bindings/display/mediatek/mediatek,disp.txt | 2 +- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 3 + drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 235 ++++++++++++++++++--- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 +- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 10 +- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 47 ++++- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 5 +- 7 files changed, 274 insertions(+), 43 deletions(-)
Update device tree binding documentation for the display subsystem for Mediatek MT2712 SoCs.
Signed-off-by: Stu Hsieh stu.hsieh@mediatek.com Acked-by: CK Hu ck.hu@mediatek.com Acked-by: Rob Herring robh@kernel.org --- Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt index 383183a89164..8469de510001 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt @@ -40,7 +40,7 @@ Required properties (all function blocks): "mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt "mediatek,<chip>-disp-mutex" - display mutex "mediatek,<chip>-disp-od" - overdrive - the supported chips are mt2701 and mt8173. + the supported chips are mt2701, mt2712 and mt8173. - reg: Physical base address and length of the function block register space - interrupts: The interrupt signal from the function block (required, except for merge and split function blocks).
This patch support that if modules more than 32, add index more than 31 when using DISP_REG_MUTEX_MOD2 bit
Signed-off-by: Stu Hsieh stu.hsieh@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 75 +++++++++++++++++++++------------- 1 file changed, 47 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index 8130f3dab661..47ffa240bd25 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -41,31 +41,32 @@ #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n)) #define DISP_REG_MUTEX_MOD(n) (0x2c + 0x20 * (n)) #define DISP_REG_MUTEX_SOF(n) (0x30 + 0x20 * (n)) +#define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n))
#define INT_MUTEX BIT(1)
-#define MT8173_MUTEX_MOD_DISP_OVL0 BIT(11) -#define MT8173_MUTEX_MOD_DISP_OVL1 BIT(12) -#define MT8173_MUTEX_MOD_DISP_RDMA0 BIT(13) -#define MT8173_MUTEX_MOD_DISP_RDMA1 BIT(14) -#define MT8173_MUTEX_MOD_DISP_RDMA2 BIT(15) -#define MT8173_MUTEX_MOD_DISP_WDMA0 BIT(16) -#define MT8173_MUTEX_MOD_DISP_WDMA1 BIT(17) -#define MT8173_MUTEX_MOD_DISP_COLOR0 BIT(18) -#define MT8173_MUTEX_MOD_DISP_COLOR1 BIT(19) -#define MT8173_MUTEX_MOD_DISP_AAL BIT(20) -#define MT8173_MUTEX_MOD_DISP_GAMMA BIT(21) -#define MT8173_MUTEX_MOD_DISP_UFOE BIT(22) -#define MT8173_MUTEX_MOD_DISP_PWM0 BIT(23) -#define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24) -#define MT8173_MUTEX_MOD_DISP_OD BIT(25) - -#define MT2701_MUTEX_MOD_DISP_OVL BIT(3) -#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6) -#define MT2701_MUTEX_MOD_DISP_COLOR BIT(7) -#define MT2701_MUTEX_MOD_DISP_BLS BIT(9) -#define MT2701_MUTEX_MOD_DISP_RDMA0 BIT(10) -#define MT2701_MUTEX_MOD_DISP_RDMA1 BIT(12) +#define MT8173_MUTEX_MOD_DISP_OVL0 11 +#define MT8173_MUTEX_MOD_DISP_OVL1 12 +#define MT8173_MUTEX_MOD_DISP_RDMA0 13 +#define MT8173_MUTEX_MOD_DISP_RDMA1 14 +#define MT8173_MUTEX_MOD_DISP_RDMA2 15 +#define MT8173_MUTEX_MOD_DISP_WDMA0 16 +#define MT8173_MUTEX_MOD_DISP_WDMA1 17 +#define MT8173_MUTEX_MOD_DISP_COLOR0 18 +#define MT8173_MUTEX_MOD_DISP_COLOR1 19 +#define MT8173_MUTEX_MOD_DISP_AAL 20 +#define MT8173_MUTEX_MOD_DISP_GAMMA 21 +#define MT8173_MUTEX_MOD_DISP_UFOE 22 +#define MT8173_MUTEX_MOD_DISP_PWM0 23 +#define MT8173_MUTEX_MOD_DISP_PWM1 24 +#define MT8173_MUTEX_MOD_DISP_OD 25 + +#define MT2701_MUTEX_MOD_DISP_OVL 3 +#define MT2701_MUTEX_MOD_DISP_WDMA 6 +#define MT2701_MUTEX_MOD_DISP_COLOR 7 +#define MT2701_MUTEX_MOD_DISP_BLS 9 +#define MT2701_MUTEX_MOD_DISP_RDMA0 10 +#define MT2701_MUTEX_MOD_DISP_RDMA1 12
#define MUTEX_SOF_SINGLE_MODE 0 #define MUTEX_SOF_DSI0 1 @@ -278,6 +279,7 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex, struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, mutex[mutex->id]); unsigned int reg; + unsigned int offset;
WARN_ON(&ddp->mutex[mutex->id] != mutex);
@@ -292,9 +294,17 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex, reg = MUTEX_SOF_DPI0; break; default: - reg = readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(mutex->id)); - reg |= ddp->mutex_mod[id]; - writel_relaxed(reg, ddp->regs + DISP_REG_MUTEX_MOD(mutex->id)); + if (ddp->mutex_mod[id] < 32) { + offset = DISP_REG_MUTEX_MOD(mutex->id); + reg = readl_relaxed(ddp->regs + offset); + reg |= 1 << ddp->mutex_mod[id]; + writel_relaxed(reg, ddp->regs + offset); + } else { + offset = DISP_REG_MUTEX_MOD2(mutex->id); + reg = readl_relaxed(ddp->regs + offset); + reg |= 1 << (ddp->mutex_mod[id] - 32); + writel_relaxed(reg, ddp->regs + offset); + } return; }
@@ -307,6 +317,7 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex, struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, mutex[mutex->id]); unsigned int reg; + unsigned int offset;
WARN_ON(&ddp->mutex[mutex->id] != mutex);
@@ -318,9 +329,17 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex, ddp->regs + DISP_REG_MUTEX_SOF(mutex->id)); break; default: - reg = readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(mutex->id)); - reg &= ~(ddp->mutex_mod[id]); - writel_relaxed(reg, ddp->regs + DISP_REG_MUTEX_MOD(mutex->id)); + if (ddp->mutex_mod[id] < 32) { + offset = DISP_REG_MUTEX_MOD(mutex->id); + reg = readl_relaxed(ddp->regs + offset); + reg &= ~(1 << ddp->mutex_mod[id]); + writel_relaxed(reg, ddp->regs + offset); + } else { + offset = DISP_REG_MUTEX_MOD2(mutex->id); + reg = readl_relaxed(ddp->regs + offset); + reg &= ~(1 << (ddp->mutex_mod[id] - 32)); + writel_relaxed(reg, ddp->regs + offset); + } break; } }
This patch add component AAL1 and rename AAL to AAL0
Signed-off-by: Stu Hsieh stu.hsieh@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 2 +- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 3 ++- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 3 ++- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 +- 4 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index 47ffa240bd25..7217665f4b5d 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -110,7 +110,7 @@ static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = { };
static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { - [DDP_COMPONENT_AAL] = MT8173_MUTEX_MOD_DISP_AAL, + [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL, [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0, [DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1, [DDP_COMPONENT_GAMMA] = MT8173_MUTEX_MOD_DISP_GAMMA, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 4672317e3ad1..0919039805aa 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -218,7 +218,8 @@ struct mtk_ddp_comp_match { };
static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { - [DDP_COMPONENT_AAL] = { MTK_DISP_AAL, 0, &ddp_aal }, + [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal }, + [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal }, [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL }, [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, NULL }, [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, NULL }, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index 0828cf8bf85c..eee3c0cc2632 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -41,7 +41,8 @@ enum mtk_ddp_comp_type { };
enum mtk_ddp_comp_id { - DDP_COMPONENT_AAL, + DDP_COMPONENT_AAL0, + DDP_COMPONENT_AAL1, DDP_COMPONENT_BLS, DDP_COMPONENT_COLOR0, DDP_COMPONENT_COLOR1, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index a2ca90fc403c..a415260f3d5f 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -149,7 +149,7 @@ static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = { static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = { DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0, - DDP_COMPONENT_AAL, + DDP_COMPONENT_AAL0, DDP_COMPONENT_OD, DDP_COMPONENT_RDMA0, DDP_COMPONENT_UFOE,
This patch add the component OD1 and rename the OD to OD0
Signed-off-by: Stu Hsieh stu.hsieh@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 4 ++-- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 3 ++- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 3 ++- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 +- 4 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index 7217665f4b5d..58e44349e315 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -114,7 +114,7 @@ static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0, [DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1, [DDP_COMPONENT_GAMMA] = MT8173_MUTEX_MOD_DISP_GAMMA, - [DDP_COMPONENT_OD] = MT8173_MUTEX_MOD_DISP_OD, + [DDP_COMPONENT_OD0] = MT8173_MUTEX_MOD_DISP_OD, [DDP_COMPONENT_OVL0] = MT8173_MUTEX_MOD_DISP_OVL0, [DDP_COMPONENT_OVL1] = MT8173_MUTEX_MOD_DISP_OVL1, [DDP_COMPONENT_PWM0] = MT8173_MUTEX_MOD_DISP_PWM0, @@ -139,7 +139,7 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN; value = OVL_MOUT_EN_RDMA; - } else if (cur == DDP_COMPONENT_OD && next == DDP_COMPONENT_RDMA0) { + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) { *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; value = OD_MOUT_EN_RDMA0; } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) { diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 0919039805aa..87acf6be87f6 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -227,7 +227,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, NULL }, [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, NULL }, [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, - [DDP_COMPONENT_OD] = { MTK_DISP_OD, 0, &ddp_od }, + [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, + [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, NULL }, [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, NULL }, [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index eee3c0cc2632..9b19fc4423f1 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -50,7 +50,8 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_DSI0, DDP_COMPONENT_DSI1, DDP_COMPONENT_GAMMA, - DDP_COMPONENT_OD, + DDP_COMPONENT_OD0, + DDP_COMPONENT_OD1, DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL1, DDP_COMPONENT_PWM0, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index a415260f3d5f..08d5d0b47bfe 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -150,7 +150,7 @@ static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = { DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0, DDP_COMPONENT_AAL0, - DDP_COMPONENT_OD, + DDP_COMPONENT_OD0, DDP_COMPONENT_RDMA0, DDP_COMPONENT_UFOE, DDP_COMPONENT_DSI0,
This patch add component PWM1 in mtk_ddp_matches
Signed-off-by: Stu Hsieh stu.hsieh@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 87acf6be87f6..a5c7ac2d162d 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -232,6 +232,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, NULL }, [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, NULL }, [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, + [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, NULL }, [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, NULL }, [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, NULL },
This patch add component PWM2
Signed-off-by: Stu Hsieh stu.hsieh@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + 2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index a5c7ac2d162d..86e8c9e5df41 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -233,6 +233,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, NULL }, [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, + [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, NULL }, [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, NULL }, [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, NULL }, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index 9b19fc4423f1..e00c2e798abd 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -56,6 +56,7 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_OVL1, DDP_COMPONENT_PWM0, DDP_COMPONENT_PWM1, + DDP_COMPONENT_PWM2, DDP_COMPONENT_RDMA0, DDP_COMPONENT_RDMA1, DDP_COMPONENT_RDMA2,
This patch add the component DPI1
Signed-off-by: Stu Hsieh stu.hsieh@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 ++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + 2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 86e8c9e5df41..cc74b1a7278c 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -224,6 +224,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, NULL }, [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, NULL }, [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, NULL }, + [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, NULL }, [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, NULL }, [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, NULL }, [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, @@ -275,6 +276,7 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *node,
if (comp_id == DDP_COMPONENT_BLS || comp_id == DDP_COMPONENT_DPI0 || + comp_id == DDP_COMPONENT_DPI1 || comp_id == DDP_COMPONENT_DSI0 || comp_id == DDP_COMPONENT_PWM0) { comp->regs = NULL; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index e00c2e798abd..54c99c169093 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -47,6 +47,7 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_COLOR0, DDP_COMPONENT_COLOR1, DDP_COMPONENT_DPI0, + DDP_COMPONENT_DPI1, DDP_COMPONENT_DSI0, DDP_COMPONENT_DSI1, DDP_COMPONENT_GAMMA,
This patch add the component DSI2
Signed-off-by: Stu Hsieh stu.hsieh@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 ++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + 2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index cc74b1a7278c..071f9f5aefea 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -227,6 +227,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, NULL }, [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, NULL }, [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, NULL }, + [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, NULL }, [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, @@ -278,6 +279,7 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *node, comp_id == DDP_COMPONENT_DPI0 || comp_id == DDP_COMPONENT_DPI1 || comp_id == DDP_COMPONENT_DSI0 || + comp_id == DDP_COMPONENT_DSI2 || comp_id == DDP_COMPONENT_PWM0) { comp->regs = NULL; comp->clk = NULL; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index 54c99c169093..8d152b337f15 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -50,6 +50,7 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_DPI1, DDP_COMPONENT_DSI0, DDP_COMPONENT_DSI1, + DDP_COMPONENT_DSI2, DDP_COMPONENT_GAMMA, DDP_COMPONENT_OD0, DDP_COMPONENT_OD1,
This patch add the component DSI3
Signed-off-by: Stu Hsieh stu.hsieh@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 ++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + 2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 071f9f5aefea..17b681686471 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -228,6 +228,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, NULL }, [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, NULL }, [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, NULL }, + [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, NULL }, [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma }, [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od }, [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od }, @@ -280,6 +281,7 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *node, comp_id == DDP_COMPONENT_DPI1 || comp_id == DDP_COMPONENT_DSI0 || comp_id == DDP_COMPONENT_DSI2 || + comp_id == DDP_COMPONENT_DSI3 || comp_id == DDP_COMPONENT_PWM0) { comp->regs = NULL; comp->clk = NULL; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index 8d152b337f15..7413ffeb3c9d 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -51,6 +51,7 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_DSI0, DDP_COMPONENT_DSI1, DDP_COMPONENT_DSI2, + DDP_COMPONENT_DSI3, DDP_COMPONENT_GAMMA, DDP_COMPONENT_OD0, DDP_COMPONENT_OD1,
This patch add the DSI1 for component init condition
Signed-off-by: Stu Hsieh stu.hsieh@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 17b681686471..ff974d82a4a6 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -280,6 +280,7 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *node, comp_id == DDP_COMPONENT_DPI0 || comp_id == DDP_COMPONENT_DPI1 || comp_id == DDP_COMPONENT_DSI0 || + comp_id == DDP_COMPONENT_DSI1 || comp_id == DDP_COMPONENT_DSI2 || comp_id == DDP_COMPONENT_DSI3 || comp_id == DDP_COMPONENT_PWM0) {
This patch add the connection from OD1 to RDMA1 for ext path.
Signed-off-by: Stu Hsieh stu.hsieh@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index 58e44349e315..8bfc0debd2c2 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -75,6 +75,7 @@
#define OVL0_MOUT_EN_COLOR0 0x1 #define OD_MOUT_EN_RDMA0 0x1 +#define OD1_MOUT_EN_RDMA1 BIT(16) #define UFOE_MOUT_EN_DSI0 0x1 #define COLOR0_SEL_IN_OVL0 0x1 #define OVL1_MOUT_EN_COLOR1 0x1 @@ -151,6 +152,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) { *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN; value = GAMMA_MOUT_EN_RDMA1; + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; + value = OD1_MOUT_EN_RDMA1; } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { *addr = DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN; value = RDMA1_MOUT_DPI0;
This patch update the definition of connection from RDMA1 to DPI0. Change the term MOUT to SOUT.
Because our HW datasheet use the term SOUT to match its function for RDMA. For consistency, changing the name from MOUT to SOUT is better.
Signed-off-by: Stu Hsieh stu.hsieh@mediatek.com --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index 8bfc0debd2c2..977df8facb79 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -29,7 +29,7 @@ #define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 #define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 #define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac -#define DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN 0x0c8 +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 #define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 @@ -80,7 +80,7 @@ #define COLOR0_SEL_IN_OVL0 0x1 #define OVL1_MOUT_EN_COLOR1 0x1 #define GAMMA_MOUT_EN_RDMA1 0x1 -#define RDMA1_MOUT_DPI0 0x2 +#define RDMA1_SOUT_DPI0 0x2 #define DPI0_SEL_IN_RDMA1 0x1 #define COLOR1_SEL_IN_OVL1 0x1
@@ -156,8 +156,8 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; value = OD1_MOUT_EN_RDMA1; } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { - *addr = DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN; - value = RDMA1_MOUT_DPI0; + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DPI0; } else { value = 0; }
On Wed, 2018-06-20 at 16:19 +0800, Stu Hsieh wrote:
This patch update the definition of connection from RDMA1 to DPI0. Change the term MOUT to SOUT.
Because our HW datasheet use the term SOUT to match its function for RDMA. For consistency, changing the name from MOUT to SOUT is better.
Reviewed-by: CK Hu ck.hu@mediatek.com
Signed-off-by: Stu Hsieh stu.hsieh@mediatek.com
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index 8bfc0debd2c2..977df8facb79 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -29,7 +29,7 @@ #define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 #define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 #define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac -#define DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN 0x0c8 +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 #define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 @@ -80,7 +80,7 @@ #define COLOR0_SEL_IN_OVL0 0x1 #define OVL1_MOUT_EN_COLOR1 0x1 #define GAMMA_MOUT_EN_RDMA1 0x1 -#define RDMA1_MOUT_DPI0 0x2 +#define RDMA1_SOUT_DPI0 0x2 #define DPI0_SEL_IN_RDMA1 0x1 #define COLOR1_SEL_IN_OVL1 0x1
@@ -156,8 +156,8 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; value = OD1_MOUT_EN_RDMA1; } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
*addr = DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN;value = RDMA1_MOUT_DPI0;
*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;value = RDMA1_SOUT_DPI0;
This patch add the connection from RDMA0 to DPI0
Signed-off-by: Stu Hsieh stu.hsieh@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index 977df8facb79..3a3f37f523f2 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -29,6 +29,7 @@ #define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 #define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 #define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 #define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 #define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
@@ -80,6 +81,7 @@ #define COLOR0_SEL_IN_OVL0 0x1 #define OVL1_MOUT_EN_COLOR1 0x1 #define GAMMA_MOUT_EN_RDMA1 0x1 +#define RDMA0_SOUT_DPI0 0x2 #define RDMA1_SOUT_DPI0 0x2 #define DPI0_SEL_IN_RDMA1 0x1 #define COLOR1_SEL_IN_OVL1 0x1 @@ -155,6 +157,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) { *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN; value = OD1_MOUT_EN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DPI0; } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; value = RDMA1_SOUT_DPI0;
This patch add the connection from RDMA0 to DSI2
Signed-off-by: Stu Hsieh stu.hsieh@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index 3a3f37f523f2..f985bad61d83 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -82,6 +82,7 @@ #define OVL1_MOUT_EN_COLOR1 0x1 #define GAMMA_MOUT_EN_RDMA1 0x1 #define RDMA0_SOUT_DPI0 0x2 +#define RDMA0_SOUT_DSI2 0x4 #define RDMA1_SOUT_DPI0 0x2 #define DPI0_SEL_IN_RDMA1 0x1 #define COLOR1_SEL_IN_OVL1 0x1 @@ -160,6 +161,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) { *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; value = RDMA0_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DSI2; } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; value = RDMA1_SOUT_DPI0;
This patch add the connection from RDMA0 to DSI3
Signed-off-by: Stu Hsieh stu.hsieh@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index f985bad61d83..463ed7830d17 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -83,6 +83,7 @@ #define GAMMA_MOUT_EN_RDMA1 0x1 #define RDMA0_SOUT_DPI0 0x2 #define RDMA0_SOUT_DSI2 0x4 +#define RDMA0_SOUT_DSI3 0x5 #define RDMA1_SOUT_DPI0 0x2 #define DPI0_SEL_IN_RDMA1 0x1 #define COLOR1_SEL_IN_OVL1 0x1 @@ -164,6 +165,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) { *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; value = RDMA0_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; + value = RDMA0_SOUT_DSI3; } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; value = RDMA1_SOUT_DPI0;
This patch add the connection from RDMA1 to DPI1
Signed-off-by: Stu Hsieh stu.hsieh@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index 463ed7830d17..13e91903f493 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -85,7 +85,9 @@ #define RDMA0_SOUT_DSI2 0x4 #define RDMA0_SOUT_DSI3 0x5 #define RDMA1_SOUT_DPI0 0x2 +#define RDMA1_SOUT_DPI1 0x3 #define DPI0_SEL_IN_RDMA1 0x1 +#define DPI1_SEL_IN_RDMA1 (0x1 << 8) #define COLOR1_SEL_IN_OVL1 0x1
#define OVL_MOUT_EN_RDMA 0x1 @@ -171,6 +173,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; value = RDMA1_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DPI1; } else { value = 0; } @@ -190,6 +195,9 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur, } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { *addr = DISP_REG_CONFIG_DPI_SEL_IN; value = DPI0_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI1_SEL_IN_RDMA1; } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; value = COLOR1_SEL_IN_OVL1;
This patch add the connection from RDMA1 to DSI1
Signed-off-by: Stu Hsieh stu.hsieh@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index 13e91903f493..90228cad051a 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -28,6 +28,7 @@ #define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 #define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 #define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 +#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 #define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac #define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 #define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 @@ -86,8 +87,10 @@ #define RDMA0_SOUT_DSI3 0x5 #define RDMA1_SOUT_DPI0 0x2 #define RDMA1_SOUT_DPI1 0x3 +#define RDMA1_SOUT_DSI1 0x1 #define DPI0_SEL_IN_RDMA1 0x1 #define DPI1_SEL_IN_RDMA1 (0x1 << 8) +#define DSI1_SEL_IN_RDMA1 0x1 #define COLOR1_SEL_IN_OVL1 0x1
#define OVL_MOUT_EN_RDMA 0x1 @@ -170,6 +173,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) { *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN; value = RDMA0_SOUT_DSI3; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI1; } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; value = RDMA1_SOUT_DPI0; @@ -198,6 +204,9 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur, } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { *addr = DISP_REG_CONFIG_DPI_SEL_IN; value = DPI1_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; + value = DSI1_SEL_IN_RDMA1; } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; value = COLOR1_SEL_IN_OVL1;
This patch add the connection from RDMA1 to DSI2
Signed-off-by: Stu Hsieh stu.hsieh@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index 90228cad051a..9cf2fcb4932a 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -28,6 +28,7 @@ #define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 #define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 #define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 +#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 #define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 #define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac #define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 @@ -88,9 +89,11 @@ #define RDMA1_SOUT_DPI0 0x2 #define RDMA1_SOUT_DPI1 0x3 #define RDMA1_SOUT_DSI1 0x1 +#define RDMA1_SOUT_DSI2 0x4 #define DPI0_SEL_IN_RDMA1 0x1 #define DPI1_SEL_IN_RDMA1 (0x1 << 8) #define DSI1_SEL_IN_RDMA1 0x1 +#define DSI2_SEL_IN_RDMA1 (0x1 << 16) #define COLOR1_SEL_IN_OVL1 0x1
#define OVL_MOUT_EN_RDMA 0x1 @@ -176,6 +179,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; value = RDMA1_SOUT_DSI1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI2; } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; value = RDMA1_SOUT_DPI0; @@ -207,6 +213,9 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur, } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { *addr = DISP_REG_CONFIG_DSIO_SEL_IN; value = DSI1_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI2_SEL_IN_RDMA1; } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; value = COLOR1_SEL_IN_OVL1;
This patch add the connection from RDMA1 to DSI3
Signed-off-by: Stu Hsieh stu.hsieh@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index 9cf2fcb4932a..d0d5f337ce14 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -90,10 +90,12 @@ #define RDMA1_SOUT_DPI1 0x3 #define RDMA1_SOUT_DSI1 0x1 #define RDMA1_SOUT_DSI2 0x4 +#define RDMA1_SOUT_DSI3 0x5 #define DPI0_SEL_IN_RDMA1 0x1 #define DPI1_SEL_IN_RDMA1 (0x1 << 8) #define DSI1_SEL_IN_RDMA1 0x1 #define DSI2_SEL_IN_RDMA1 (0x1 << 16) +#define DSI3_SEL_IN_RDMA1 (0x1 << 16) #define COLOR1_SEL_IN_OVL1 0x1
#define OVL_MOUT_EN_RDMA 0x1 @@ -182,6 +184,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; value = RDMA1_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; + value = RDMA1_SOUT_DSI3; } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) { *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; value = RDMA1_SOUT_DPI0; @@ -216,6 +221,9 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur, } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) { *addr = DISP_REG_CONFIG_DSIE_SEL_IN; value = DSI2_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DSIO_SEL_IN; + value = DSI3_SEL_IN_RDMA1; } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; value = COLOR1_SEL_IN_OVL1;
This patch add the connection from RDMA2 to DPI0
Signed-off-by: Stu Hsieh stu.hsieh@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index d0d5f337ce14..c88742a6c2b9 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -31,6 +31,7 @@ #define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4 #define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8 #define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8 #define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 #define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 #define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 @@ -91,7 +92,9 @@ #define RDMA1_SOUT_DSI1 0x1 #define RDMA1_SOUT_DSI2 0x4 #define RDMA1_SOUT_DSI3 0x5 +#define RDMA2_SOUT_DPI0 0x2 #define DPI0_SEL_IN_RDMA1 0x1 +#define DPI0_SEL_IN_RDMA2 0x3 #define DPI1_SEL_IN_RDMA1 (0x1 << 8) #define DSI1_SEL_IN_RDMA1 0x1 #define DSI2_SEL_IN_RDMA1 (0x1 << 16) @@ -193,6 +196,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) { *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN; value = RDMA1_SOUT_DPI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DPI0; } else { value = 0; } @@ -224,6 +230,9 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur, } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) { *addr = DISP_REG_CONFIG_DSIO_SEL_IN; value = DSI3_SEL_IN_RDMA1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI0_SEL_IN_RDMA2; } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; value = COLOR1_SEL_IN_OVL1;
This patch add the connection from RDMA2 to DPI1
Signed-off-by: Stu Hsieh stu.hsieh@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index c88742a6c2b9..a4b418302f32 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -93,9 +93,11 @@ #define RDMA1_SOUT_DSI2 0x4 #define RDMA1_SOUT_DSI3 0x5 #define RDMA2_SOUT_DPI0 0x2 +#define RDMA2_SOUT_DPI1 0x3 #define DPI0_SEL_IN_RDMA1 0x1 #define DPI0_SEL_IN_RDMA2 0x3 #define DPI1_SEL_IN_RDMA1 (0x1 << 8) +#define DPI1_SEL_IN_RDMA2 (0x3 << 8) #define DSI1_SEL_IN_RDMA1 0x1 #define DSI2_SEL_IN_RDMA1 (0x1 << 16) #define DSI3_SEL_IN_RDMA1 (0x1 << 16) @@ -199,6 +201,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; value = RDMA2_SOUT_DPI0; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DPI1; } else { value = 0; } @@ -233,6 +238,9 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur, } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) { *addr = DISP_REG_CONFIG_DPI_SEL_IN; value = DPI0_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { + *addr = DISP_REG_CONFIG_DPI_SEL_IN; + value = DPI1_SEL_IN_RDMA2; } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; value = COLOR1_SEL_IN_OVL1;
This patch add the connection from RDMA2 to DSI1
Signed-off-by: Stu Hsieh stu.hsieh@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index a4b418302f32..db78fad785e3 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -94,11 +94,13 @@ #define RDMA1_SOUT_DSI3 0x5 #define RDMA2_SOUT_DPI0 0x2 #define RDMA2_SOUT_DPI1 0x3 +#define RDMA2_SOUT_DSI1 0x1 #define DPI0_SEL_IN_RDMA1 0x1 #define DPI0_SEL_IN_RDMA2 0x3 #define DPI1_SEL_IN_RDMA1 (0x1 << 8) #define DPI1_SEL_IN_RDMA2 (0x3 << 8) #define DSI1_SEL_IN_RDMA1 0x1 +#define DSI1_SEL_IN_RDMA2 0x4 #define DSI2_SEL_IN_RDMA1 (0x1 << 16) #define DSI3_SEL_IN_RDMA1 (0x1 << 16) #define COLOR1_SEL_IN_OVL1 0x1 @@ -204,6 +206,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; value = RDMA2_SOUT_DPI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI1; } else { value = 0; } @@ -241,6 +246,9 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur, } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) { *addr = DISP_REG_CONFIG_DPI_SEL_IN; value = DPI1_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI1_SEL_IN_RDMA2; } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; value = COLOR1_SEL_IN_OVL1;
This patch add the connection from RDMA2 to DSI2
Signed-off-by: Stu Hsieh stu.hsieh@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index db78fad785e3..e5db1ab51c9b 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -95,6 +95,7 @@ #define RDMA2_SOUT_DPI0 0x2 #define RDMA2_SOUT_DPI1 0x3 #define RDMA2_SOUT_DSI1 0x1 +#define RDMA2_SOUT_DSI2 0x4 #define DPI0_SEL_IN_RDMA1 0x1 #define DPI0_SEL_IN_RDMA2 0x3 #define DPI1_SEL_IN_RDMA1 (0x1 << 8) @@ -102,6 +103,7 @@ #define DSI1_SEL_IN_RDMA1 0x1 #define DSI1_SEL_IN_RDMA2 0x4 #define DSI2_SEL_IN_RDMA1 (0x1 << 16) +#define DSI2_SEL_IN_RDMA2 (0x4 << 16) #define DSI3_SEL_IN_RDMA1 (0x1 << 16) #define COLOR1_SEL_IN_OVL1 0x1
@@ -209,6 +211,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; value = RDMA2_SOUT_DSI1; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI2; } else { value = 0; } @@ -249,6 +254,9 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur, } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) { *addr = DISP_REG_CONFIG_DSIE_SEL_IN; value = DSI1_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI2_SEL_IN_RDMA2; } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; value = COLOR1_SEL_IN_OVL1;
This patch add the connection from RDMA2 to DSI3
Signed-off-by: Stu Hsieh stu.hsieh@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index e5db1ab51c9b..0a1b967cab1b 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -96,6 +96,7 @@ #define RDMA2_SOUT_DPI1 0x3 #define RDMA2_SOUT_DSI1 0x1 #define RDMA2_SOUT_DSI2 0x4 +#define RDMA2_SOUT_DSI3 0x5 #define DPI0_SEL_IN_RDMA1 0x1 #define DPI0_SEL_IN_RDMA2 0x3 #define DPI1_SEL_IN_RDMA1 (0x1 << 8) @@ -105,6 +106,7 @@ #define DSI2_SEL_IN_RDMA1 (0x1 << 16) #define DSI2_SEL_IN_RDMA2 (0x4 << 16) #define DSI3_SEL_IN_RDMA1 (0x1 << 16) +#define DSI3_SEL_IN_RDMA2 (0x4 << 16) #define COLOR1_SEL_IN_OVL1 0x1
#define OVL_MOUT_EN_RDMA 0x1 @@ -214,6 +216,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; value = RDMA2_SOUT_DSI2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT; + value = RDMA2_SOUT_DSI3; } else { value = 0; } @@ -257,6 +262,9 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur, } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) { *addr = DISP_REG_CONFIG_DSIE_SEL_IN; value = DSI2_SEL_IN_RDMA2; + } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) { + *addr = DISP_REG_CONFIG_DSIE_SEL_IN; + value = DSI3_SEL_IN_RDMA2; } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) { *addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN; value = COLOR1_SEL_IN_OVL1;
This patch add the DPI1 support for mutex
Signed-off-by: Stu Hsieh stu.hsieh@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index 0a1b967cab1b..4c203d013d7c 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -76,6 +76,7 @@ #define MUTEX_SOF_DSI0 1 #define MUTEX_SOF_DSI1 2 #define MUTEX_SOF_DPI0 3 +#define MUTEX_SOF_DPI1 4
#define OVL0_MOUT_EN_COLOR0 0x1 #define OD_MOUT_EN_RDMA0 0x1 @@ -385,6 +386,9 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex, case DDP_COMPONENT_DPI0: reg = MUTEX_SOF_DPI0; break; + case DDP_COMPONENT_DPI1: + reg = MUTEX_SOF_DPI1; + break; default: if (ddp->mutex_mod[id] < 32) { offset = DISP_REG_MUTEX_MOD(mutex->id); @@ -417,6 +421,7 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex, case DDP_COMPONENT_DSI0: case DDP_COMPONENT_DSI1: case DDP_COMPONENT_DPI0: + case DDP_COMPONENT_DPI1: writel_relaxed(MUTEX_SOF_SINGLE_MODE, ddp->regs + DISP_REG_MUTEX_SOF(mutex->id)); break;
This patch add the DSI2 support for mutex
Signed-off-by: Stu Hsieh stu.hsieh@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index 4c203d013d7c..a0b526b16da1 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -77,6 +77,7 @@ #define MUTEX_SOF_DSI1 2 #define MUTEX_SOF_DPI0 3 #define MUTEX_SOF_DPI1 4 +#define MUTEX_SOF_DSI2 5
#define OVL0_MOUT_EN_COLOR0 0x1 #define OD_MOUT_EN_RDMA0 0x1 @@ -383,6 +384,9 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex, case DDP_COMPONENT_DSI1: reg = MUTEX_SOF_DSI0; break; + case DDP_COMPONENT_DSI2: + reg = MUTEX_SOF_DSI2; + break; case DDP_COMPONENT_DPI0: reg = MUTEX_SOF_DPI0; break; @@ -420,6 +424,7 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex, switch (id) { case DDP_COMPONENT_DSI0: case DDP_COMPONENT_DSI1: + case DDP_COMPONENT_DSI2: case DDP_COMPONENT_DPI0: case DDP_COMPONENT_DPI1: writel_relaxed(MUTEX_SOF_SINGLE_MODE,
This patch add the DSI3 support for mutex
Signed-off-by: Stu Hsieh stu.hsieh@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index a0b526b16da1..15e436d4e8a0 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -78,6 +78,7 @@ #define MUTEX_SOF_DPI0 3 #define MUTEX_SOF_DPI1 4 #define MUTEX_SOF_DSI2 5 +#define MUTEX_SOF_DSI3 6
#define OVL0_MOUT_EN_COLOR0 0x1 #define OD_MOUT_EN_RDMA0 0x1 @@ -387,6 +388,9 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex, case DDP_COMPONENT_DSI2: reg = MUTEX_SOF_DSI2; break; + case DDP_COMPONENT_DSI3: + reg = MUTEX_SOF_DSI3; + break; case DDP_COMPONENT_DPI0: reg = MUTEX_SOF_DPI0; break; @@ -425,6 +429,7 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex, case DDP_COMPONENT_DSI0: case DDP_COMPONENT_DSI1: case DDP_COMPONENT_DSI2: + case DDP_COMPONENT_DSI3: case DDP_COMPONENT_DPI0: case DDP_COMPONENT_DPI1: writel_relaxed(MUTEX_SOF_SINGLE_MODE,
This patch create third crtc by third ddp path
Signed-off-by: Stu Hsieh stu.hsieh@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 3 +++ drivers/gpu/drm/mediatek/mtk_drm_drv.c | 5 +++++ drivers/gpu/drm/mediatek/mtk_drm_drv.h | 5 ++++- 3 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c index 658b8dd45b83..2d6aa150a9ff 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -539,6 +539,9 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, int ret; int i;
+ if (!path) + return 0; + for (i = 0; i < path_len; i++) { enum mtk_ddp_comp_id comp_id = path[i]; struct device_node *node; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 08d5d0b47bfe..3d279a299383 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -232,6 +232,11 @@ static int mtk_drm_kms_init(struct drm_device *drm) if (ret < 0) goto err_component_unbind;
+ ret = mtk_drm_crtc_create(drm, private->data->third_path, + private->data->third_len); + if (ret < 0) + goto err_component_unbind; + /* Use OVL device for all DMA memory allocations */ np = private->comp_node[private->data->main_path[0]] ?: private->comp_node[private->data->ext_path[0]]; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h index c3378c452c0a..ecc00ca3221d 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -17,7 +17,7 @@ #include <linux/io.h> #include "mtk_drm_ddp_comp.h"
-#define MAX_CRTC 2 +#define MAX_CRTC 3 #define MAX_CONNECTOR 2
struct device; @@ -33,6 +33,9 @@ struct mtk_mmsys_driver_data { unsigned int main_len; const enum mtk_ddp_comp_id *ext_path; unsigned int ext_len; + const enum mtk_ddp_comp_id *third_path; + unsigned int third_len; + bool shadow_register; };
This patch add support for the Mediatek MT2712 DISP subsystem. There are two OVL engine and three disp output in MT2712.
Signed-off-by: Stu Hsieh stu.hsieh@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 39 ++++++++++++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_drv.c | 38 +++++++++++++++++++++++++++++++++ 2 files changed, 77 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index 15e436d4e8a0..87e4191c250e 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -65,6 +65,24 @@ #define MT8173_MUTEX_MOD_DISP_PWM1 24 #define MT8173_MUTEX_MOD_DISP_OD 25
+#define MT2712_MUTEX_MOD_DISP_PWM2 10 +#define MT2712_MUTEX_MOD_DISP_OVL0 11 +#define MT2712_MUTEX_MOD_DISP_OVL1 12 +#define MT2712_MUTEX_MOD_DISP_RDMA0 13 +#define MT2712_MUTEX_MOD_DISP_RDMA1 14 +#define MT2712_MUTEX_MOD_DISP_RDMA2 15 +#define MT2712_MUTEX_MOD_DISP_WDMA0 16 +#define MT2712_MUTEX_MOD_DISP_WDMA1 17 +#define MT2712_MUTEX_MOD_DISP_COLOR0 18 +#define MT2712_MUTEX_MOD_DISP_COLOR1 19 +#define MT2712_MUTEX_MOD_DISP_AAL0 20 +#define MT2712_MUTEX_MOD_DISP_UFOE 22 +#define MT2712_MUTEX_MOD_DISP_PWM0 23 +#define MT2712_MUTEX_MOD_DISP_PWM1 24 +#define MT2712_MUTEX_MOD_DISP_OD0 25 +#define MT2712_MUTEX_MOD2_DISP_AAL1 33 +#define MT2712_MUTEX_MOD2_DISP_OD1 34 + #define MT2701_MUTEX_MOD_DISP_OVL 3 #define MT2701_MUTEX_MOD_DISP_WDMA 6 #define MT2701_MUTEX_MOD_DISP_COLOR 7 @@ -138,6 +156,26 @@ static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA, };
+static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = { + [DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0, + [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1, + [DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0, + [DDP_COMPONENT_COLOR1] = MT2712_MUTEX_MOD_DISP_COLOR1, + [DDP_COMPONENT_OD0] = MT2712_MUTEX_MOD_DISP_OD0, + [DDP_COMPONENT_OD1] = MT2712_MUTEX_MOD2_DISP_OD1, + [DDP_COMPONENT_OVL0] = MT2712_MUTEX_MOD_DISP_OVL0, + [DDP_COMPONENT_OVL1] = MT2712_MUTEX_MOD_DISP_OVL1, + [DDP_COMPONENT_PWM0] = MT2712_MUTEX_MOD_DISP_PWM0, + [DDP_COMPONENT_PWM1] = MT2712_MUTEX_MOD_DISP_PWM1, + [DDP_COMPONENT_PWM2] = MT2712_MUTEX_MOD_DISP_PWM2, + [DDP_COMPONENT_RDMA0] = MT2712_MUTEX_MOD_DISP_RDMA0, + [DDP_COMPONENT_RDMA1] = MT2712_MUTEX_MOD_DISP_RDMA1, + [DDP_COMPONENT_RDMA2] = MT2712_MUTEX_MOD_DISP_RDMA2, + [DDP_COMPONENT_UFOE] = MT2712_MUTEX_MOD_DISP_UFOE, + [DDP_COMPONENT_WDMA0] = MT2712_MUTEX_MOD_DISP_WDMA0, + [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1, +}; + static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL, [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0, @@ -533,6 +571,7 @@ static int mtk_ddp_remove(struct platform_device *pdev)
static const struct of_device_id ddp_driver_dt_match[] = { { .compatible = "mediatek,mt2701-disp-mutex", .data = mt2701_mutex_mod}, + { .compatible = "mediatek,mt2712-disp-mutex", .data = mt2712_mutex_mod}, { .compatible = "mediatek,mt8173-disp-mutex", .data = mt8173_mutex_mod}, {}, }; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 3d279a299383..71a4b1c85cd2 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -146,6 +146,32 @@ static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = { DDP_COMPONENT_DPI0, };
+static const enum mtk_ddp_comp_id mt2712_mtk_ddp_main[] = { + DDP_COMPONENT_OVL0, + DDP_COMPONENT_COLOR0, + DDP_COMPONENT_AAL0, + DDP_COMPONENT_OD0, + DDP_COMPONENT_RDMA0, + DDP_COMPONENT_DPI0, + DDP_COMPONENT_PWM0, +}; + +static const enum mtk_ddp_comp_id mt2712_mtk_ddp_ext[] = { + DDP_COMPONENT_OVL1, + DDP_COMPONENT_COLOR1, + DDP_COMPONENT_AAL1, + DDP_COMPONENT_OD1, + DDP_COMPONENT_RDMA1, + DDP_COMPONENT_DPI1, + DDP_COMPONENT_PWM1, +}; + +static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = { + DDP_COMPONENT_RDMA2, + DDP_COMPONENT_DSI3, + DDP_COMPONENT_PWM2, +}; + static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = { DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0, @@ -173,6 +199,15 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .shadow_register = true, };
+static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { + .main_path = mt2712_mtk_ddp_main, + .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main), + .ext_path = mt2712_mtk_ddp_ext, + .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext), + .third_path = mt2712_mtk_ddp_third, + .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third), +}; + static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { .main_path = mt8173_mtk_ddp_main, .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main), @@ -379,6 +414,7 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { { .compatible = "mediatek,mt8173-dsi", .data = (void *)MTK_DSI }, { .compatible = "mediatek,mt8173-dpi", .data = (void *)MTK_DPI }, { .compatible = "mediatek,mt2701-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, + { .compatible = "mediatek,mt2712-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8173-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt2701-disp-pwm", .data = (void *)MTK_DISP_BLS }, { .compatible = "mediatek,mt8173-disp-pwm", .data = (void *)MTK_DISP_PWM }, @@ -557,6 +593,8 @@ static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend, static const struct of_device_id mtk_drm_of_ids[] = { { .compatible = "mediatek,mt2701-mmsys", .data = &mt2701_mmsys_driver_data}, + { .compatible = "mediatek,mt2712-mmsys", + .data = &mt2712_mmsys_driver_data}, { .compatible = "mediatek,mt8173-mmsys", .data = &mt8173_mmsys_driver_data}, { }
On Wed, Jun 20, 2018 at 04:19:02PM +0800, Stu Hsieh wrote:
This patch add support for the Mediatek MT2712 DISP subsystem. MT2712 is base on MT8173, there are some difference as following: MT2712 support three disp output(two ovl and one rdma)
Change in v6:
- Update commit message for the patch "drm/mediatek: Update the definition of connection from RDMA1 to DPI0"
Just a drive-by comment on the mediatek driver:
As far as I can see mtk_drm_gem.c reimplements the cma helpers as a copypaste job. Any reasons why you're not using the normal cma helpers?
Thanks, Daniel
Stu Hsieh (29): drm/mediatek: update dt-bindings for mt2712 drm/mediatek: support maximum 64 mutex mod drm/mediatek: add ddp component AAL1 drm/mediatek: add ddp component OD1 drm/mediatek: add ddp component PWM1 drm/mediatek: add ddp component PWM2 drm/mediatek: add component DPI1 drm/mediatek: add component DSI2 drm/mediatek: add component DSI3 drm/mediatek: add the DSI1 for component init condition drm/mediatek: add connection from OD1 to RDMA1 drm/mediatek: Update the definition of connection from RDMA1 to DPI0 drm/mediatek: add connection from RDMA0 to DPI0 drm/mediatek: add connection from RDMA0 to DSI2 drm/mediatek: add connection from RDMA0 to DSI3 drm/mediatek: add connection from RDMA1 to DPI1 drm/mediatek: add connection from RDMA1 to DSI1 drm/mediatek: add connection from RDMA1 to DSI2 drm/mediatek: add connection from RDMA1 to DSI3 drm/mediatek: add connection from RDMA2 to DPI0 drm/mediatek: add connection from RDMA2 to DPI1 drm/mediatek: add connection from RDMA2 to DSI1 drm/mediatek: add connection from RDMA2 to DSI2 drm/mediatek: add connection from RDMA2 to DSI3 drm/mediatek: add DPI1 support for mutex drm/mediatek: add DSI2 support for mutex drm/mediatek: add DSI3 support for mutex drm/mediatek: add third ddp path drm/mediatek: Add support for mediatek SOC MT2712
.../bindings/display/mediatek/mediatek,disp.txt | 2 +- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 3 + drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 235 ++++++++++++++++++--- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 +- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 10 +- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 47 ++++- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 5 +- 7 files changed, 274 insertions(+), 43 deletions(-)
-- 2.12.5
dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Hi, Daniel Vetter:
On Mon, 2018-06-25 at 10:47 +0200, Daniel Vetter wrote:
On Wed, Jun 20, 2018 at 04:19:02PM +0800, Stu Hsieh wrote:
This patch add support for the Mediatek MT2712 DISP subsystem. MT2712 is base on MT8173, there are some difference as following: MT2712 support three disp output(two ovl and one rdma)
Change in v6:
- Update commit message for the patch "drm/mediatek: Update the definition of connection from RDMA1 to DPI0"
Just a drive-by comment on the mediatek driver:
As far as I can see mtk_drm_gem.c reimplements the cma helpers as a copypaste job. Any reasons why you're not using the normal cma helpers?
Thanks, Daniel
In the beginning, we develop mtk_drm_gem.c by referring other platform. We will try to use the normal cma helpers according to your idea.
Thanks, Stu
Stu Hsieh (29): drm/mediatek: update dt-bindings for mt2712 drm/mediatek: support maximum 64 mutex mod drm/mediatek: add ddp component AAL1 drm/mediatek: add ddp component OD1 drm/mediatek: add ddp component PWM1 drm/mediatek: add ddp component PWM2 drm/mediatek: add component DPI1 drm/mediatek: add component DSI2 drm/mediatek: add component DSI3 drm/mediatek: add the DSI1 for component init condition drm/mediatek: add connection from OD1 to RDMA1 drm/mediatek: Update the definition of connection from RDMA1 to DPI0 drm/mediatek: add connection from RDMA0 to DPI0 drm/mediatek: add connection from RDMA0 to DSI2 drm/mediatek: add connection from RDMA0 to DSI3 drm/mediatek: add connection from RDMA1 to DPI1 drm/mediatek: add connection from RDMA1 to DSI1 drm/mediatek: add connection from RDMA1 to DSI2 drm/mediatek: add connection from RDMA1 to DSI3 drm/mediatek: add connection from RDMA2 to DPI0 drm/mediatek: add connection from RDMA2 to DPI1 drm/mediatek: add connection from RDMA2 to DSI1 drm/mediatek: add connection from RDMA2 to DSI2 drm/mediatek: add connection from RDMA2 to DSI3 drm/mediatek: add DPI1 support for mutex drm/mediatek: add DSI2 support for mutex drm/mediatek: add DSI3 support for mutex drm/mediatek: add third ddp path drm/mediatek: Add support for mediatek SOC MT2712
.../bindings/display/mediatek/mediatek,disp.txt | 2 +- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 3 + drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 235 ++++++++++++++++++--- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 +- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 10 +- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 47 ++++- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 5 +- 7 files changed, 274 insertions(+), 43 deletions(-)
-- 2.12.5
dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
On Thu, Jun 28, 2018 at 11:45:37AM +0800, Stu Hsieh wrote:
Hi, Daniel Vetter:
On Mon, 2018-06-25 at 10:47 +0200, Daniel Vetter wrote:
On Wed, Jun 20, 2018 at 04:19:02PM +0800, Stu Hsieh wrote:
This patch add support for the Mediatek MT2712 DISP subsystem. MT2712 is base on MT8173, there are some difference as following: MT2712 support three disp output(two ovl and one rdma)
Change in v6:
- Update commit message for the patch "drm/mediatek: Update the definition of connection from RDMA1 to DPI0"
Just a drive-by comment on the mediatek driver:
As far as I can see mtk_drm_gem.c reimplements the cma helpers as a copypaste job. Any reasons why you're not using the normal cma helpers?
Thanks, Daniel
In the beginning, we develop mtk_drm_gem.c by referring other platform. We will try to use the normal cma helpers according to your idea.
Sounds great if you can do this as a longer-term refactoring task!
I discussed this also a bit with Philipp on irc, and he said there's possible a need to support non-contig buffers in mtk. If that can't be done using cma helpers (usually you have an iommu in such a case, which again gives you a contig buffer in device-address space, and that can be used by cma I think), then I think it would still be useful if you use the cma helpers for the contig buffers. But then wrap them in some mtk code to switch between the two.
Cheers, Daniel
Thanks, Stu
Stu Hsieh (29): drm/mediatek: update dt-bindings for mt2712 drm/mediatek: support maximum 64 mutex mod drm/mediatek: add ddp component AAL1 drm/mediatek: add ddp component OD1 drm/mediatek: add ddp component PWM1 drm/mediatek: add ddp component PWM2 drm/mediatek: add component DPI1 drm/mediatek: add component DSI2 drm/mediatek: add component DSI3 drm/mediatek: add the DSI1 for component init condition drm/mediatek: add connection from OD1 to RDMA1 drm/mediatek: Update the definition of connection from RDMA1 to DPI0 drm/mediatek: add connection from RDMA0 to DPI0 drm/mediatek: add connection from RDMA0 to DSI2 drm/mediatek: add connection from RDMA0 to DSI3 drm/mediatek: add connection from RDMA1 to DPI1 drm/mediatek: add connection from RDMA1 to DSI1 drm/mediatek: add connection from RDMA1 to DSI2 drm/mediatek: add connection from RDMA1 to DSI3 drm/mediatek: add connection from RDMA2 to DPI0 drm/mediatek: add connection from RDMA2 to DPI1 drm/mediatek: add connection from RDMA2 to DSI1 drm/mediatek: add connection from RDMA2 to DSI2 drm/mediatek: add connection from RDMA2 to DSI3 drm/mediatek: add DPI1 support for mutex drm/mediatek: add DSI2 support for mutex drm/mediatek: add DSI3 support for mutex drm/mediatek: add third ddp path drm/mediatek: Add support for mediatek SOC MT2712
.../bindings/display/mediatek/mediatek,disp.txt | 2 +- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 3 + drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 235 ++++++++++++++++++--- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 +- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 10 +- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 47 ++++- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 5 +- 7 files changed, 274 insertions(+), 43 deletions(-)
-- 2.12.5
dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
Hi, Stu:
On Wed, 2018-06-20 at 16:19 +0800, Stu Hsieh wrote:
This patch add support for the Mediatek MT2712 DISP subsystem. MT2712 is base on MT8173, there are some difference as following: MT2712 support three disp output(two ovl and one rdma)
For the series, applied to mediatek-drm-next-4.19 [1], the patch 'drm/mediatek: Add support for mediatek SOC MT2712' has line over 80 character, so I've modified it.
[1] https://github.com/ckhu-mediatek/linux.git-tags/commits/mediatek-drm-next-4....
Regards, CK
Change in v6:
- Update commit message for the patch "drm/mediatek: Update the definition of connection from RDMA1 to DPI0"
Stu Hsieh (29): drm/mediatek: update dt-bindings for mt2712 drm/mediatek: support maximum 64 mutex mod drm/mediatek: add ddp component AAL1 drm/mediatek: add ddp component OD1 drm/mediatek: add ddp component PWM1 drm/mediatek: add ddp component PWM2 drm/mediatek: add component DPI1 drm/mediatek: add component DSI2 drm/mediatek: add component DSI3 drm/mediatek: add the DSI1 for component init condition drm/mediatek: add connection from OD1 to RDMA1 drm/mediatek: Update the definition of connection from RDMA1 to DPI0 drm/mediatek: add connection from RDMA0 to DPI0 drm/mediatek: add connection from RDMA0 to DSI2 drm/mediatek: add connection from RDMA0 to DSI3 drm/mediatek: add connection from RDMA1 to DPI1 drm/mediatek: add connection from RDMA1 to DSI1 drm/mediatek: add connection from RDMA1 to DSI2 drm/mediatek: add connection from RDMA1 to DSI3 drm/mediatek: add connection from RDMA2 to DPI0 drm/mediatek: add connection from RDMA2 to DPI1 drm/mediatek: add connection from RDMA2 to DSI1 drm/mediatek: add connection from RDMA2 to DSI2 drm/mediatek: add connection from RDMA2 to DSI3 drm/mediatek: add DPI1 support for mutex drm/mediatek: add DSI2 support for mutex drm/mediatek: add DSI3 support for mutex drm/mediatek: add third ddp path drm/mediatek: Add support for mediatek SOC MT2712
.../bindings/display/mediatek/mediatek,disp.txt | 2 +- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 3 + drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 235 ++++++++++++++++++--- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 +- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 10 +- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 47 ++++- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 5 +- 7 files changed, 274 insertions(+), 43 deletions(-)
dri-devel@lists.freedesktop.org
-
CK Hu -
Daniel Vetter -
Stu Hsieh