This patch series re-work a few i915 functions to use drm_clflush_virt_range instead of calling clflush or clflushopt directly. This will prevent errors when building for non-x86 architectures.
v2: s/PAGE_SIZE/sizeof(value) for Re-work intel_write_status_page and added more patches to convert additional clflush/clflushopt to use drm_clflush*. (Michael Cheng)
v3: Drop invalidate_csb_entries and directly invoke drm_clflush_virt_ran
v4: Remove extra memory barriers
v5: s/cache_clflush_range/drm_clflush_virt_range
v6: Fix up "Drop invalidate_csb_entries" to use correct parameters. Also added in arm64 support for drm_clflush_virt_range.
v7: Re-order patches, and use correct macro for dcache flush for arm64.
v8: Remove ifdef for asm/cacheflush.
v9: Rebased
v10: Replaced asm/cacheflush with linux/cacheflush
v11: Correctly get the sizeof certian addresses. Also rebased to the latest.
v12: Drop include of cacheflush.h and use caches_clean_inval_pou instead of dcache_clean_inval_poc, since it is not exported for other modules to use.
Michael Cheng (6): drm: Add arch arm64 for drm_clflush_virt_range drm/i915/gt: Re-work intel_write_status_page drm/i915/gt: Drop invalidate_csb_entries drm/i915/gt: Re-work reset_csb drm/i915/: Re-work clflush_write32 drm/i915/gt: replace cache_clflush_range
drivers/gpu/drm/drm_cache.c | 5 +++++ .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++----- drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 12 +++++------ drivers/gpu/drm/i915/gt/intel_engine.h | 13 ++++-------- .../drm/i915/gt/intel_execlists_submission.c | 20 +++++++------------ drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +- drivers/gpu/drm/i915/gt/intel_ppgtt.c | 2 +- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +- 8 files changed, 28 insertions(+), 36 deletions(-)
Add arm64 support for drm_clflush_virt_range. caches_clean_inval_pou performs a flush by first performing a clean, follow by an invalidation operation.
v2 (Michael Cheng): Use correct macro for cleaning and invalidation the dcache. Thanks Tvrtko for the suggestion.
v3 (Michael Cheng): Replace asm/cacheflush.h with linux/cacheflush.h
v4 (Michael Cheng): Arm64 does not export dcache_clean_inval_poc as a symbol that could be use by other modules, thus use caches_clean_inval_pou instead. Also this version removes include for cacheflush, since its already included base on architecture type.
Signed-off-by: Michael Cheng michael.cheng@intel.com Reviewed-by: Matt Roper matthew.d.roper@intel.com --- drivers/gpu/drm/drm_cache.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c index c3e6e615bf09..81c28714f930 100644 --- a/drivers/gpu/drm/drm_cache.c +++ b/drivers/gpu/drm/drm_cache.c @@ -174,6 +174,11 @@ drm_clflush_virt_range(void *addr, unsigned long length)
if (wbinvd_on_all_cpus()) pr_err("Timed out waiting for cache flush\n"); + +#elif defined(CONFIG_ARM64) + void *end = addr + length; + caches_clean_inval_pou((unsigned long)addr, (unsigned long)end); + #else WARN_ONCE(1, "Architecture has no drm_cache.c support\n"); #endif
On 25/02/2022 03:24, Michael Cheng wrote:
Add arm64 support for drm_clflush_virt_range. caches_clean_inval_pou performs a flush by first performing a clean, follow by an invalidation operation.
v2 (Michael Cheng): Use correct macro for cleaning and invalidation the dcache. Thanks Tvrtko for the suggestion.
v3 (Michael Cheng): Replace asm/cacheflush.h with linux/cacheflush.h
v4 (Michael Cheng): Arm64 does not export dcache_clean_inval_poc as a symbol that could be use by other modules, thus use caches_clean_inval_pou instead. Also this version removes include for cacheflush, since its already included base on architecture type.
What does it mean that it is included based on architecture type? Some of the other header already pulls it in?
Regards,
Tvrtko
Signed-off-by: Michael Cheng michael.cheng@intel.com Reviewed-by: Matt Roper matthew.d.roper@intel.com
drivers/gpu/drm/drm_cache.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c index c3e6e615bf09..81c28714f930 100644 --- a/drivers/gpu/drm/drm_cache.c +++ b/drivers/gpu/drm/drm_cache.c @@ -174,6 +174,11 @@ drm_clflush_virt_range(void *addr, unsigned long length)
if (wbinvd_on_all_cpus()) pr_err("Timed out waiting for cache flush\n");
+#elif defined(CONFIG_ARM64)
- void *end = addr + length;
- caches_clean_inval_pou((unsigned long)addr, (unsigned long)end);
- #else WARN_ONCE(1, "Architecture has no drm_cache.c support\n"); #endif
Hi Tvrtko,
It seems without cacheflush.h being included, when I build for arm64 or x86, it stills pulls in cacheflush.h:
./.drm_cache.o.cmd:838: include/linux/cacheflush.h \ ./.drm_cache.o.cmd:839: arch/x86/include/asm/cacheflush.h \ ./.drm_cache.o.cmd:920: include/asm-generic/cacheflush.h \ ./.drm_cache.o.cmd:830: include/linux/cacheflush.h \ ./.drm_cache.o.cmd:831: arch/arm64/include/asm/cacheflush.h \ ./.drm_cache.o.cmd:1085: include/asm-generic/cacheflush.h \ So it seems without including it, cacheflush.h stills get pulled in, I think its because its a required kernel source to build the kernel per specific architecture, but please correct if I am wrong,as I am still trying to understand how things works! Michael Cheng On 2022-02-25 8:28 a.m., Tvrtko Ursulin wrote:
On 25/02/2022 03:24, Michael Cheng wrote:
Add arm64 support for drm_clflush_virt_range. caches_clean_inval_pou performs a flush by first performing a clean, follow by an invalidation operation.
v2 (Michael Cheng): Use correct macro for cleaning and invalidation the dcache. Thanks Tvrtko for the suggestion.
v3 (Michael Cheng): Replace asm/cacheflush.h with linux/cacheflush.h
v4 (Michael Cheng): Arm64 does not export dcache_clean_inval_poc as a symbol that could be use by other modules, thus use caches_clean_inval_pou instead. Also this version removes include for cacheflush, since its already included base on architecture type.
What does it mean that it is included based on architecture type? Some of the other header already pulls it in?
Regards,
Tvrtko
Signed-off-by: Michael Cheng michael.cheng@intel.com Reviewed-by: Matt Roper matthew.d.roper@intel.com
drivers/gpu/drm/drm_cache.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c index c3e6e615bf09..81c28714f930 100644 --- a/drivers/gpu/drm/drm_cache.c +++ b/drivers/gpu/drm/drm_cache.c @@ -174,6 +174,11 @@ drm_clflush_virt_range(void *addr, unsigned long length) if (wbinvd_on_all_cpus()) pr_err("Timed out waiting for cache flush\n");
+#elif defined(CONFIG_ARM64) + void *end = addr + length; + caches_clean_inval_pou((unsigned long)addr, (unsigned long)end);
#else WARN_ONCE(1, "Architecture has no drm_cache.c support\n"); #endif
On 25/02/2022 16:52, Michael Cheng wrote:
Hi Tvrtko,
It seems without cacheflush.h being included, when I build for arm64 or x86, it stills pulls in cacheflush.h:
./.drm_cache.o.cmd:838: include/linux/cacheflush.h \ ./.drm_cache.o.cmd:839: arch/x86/include/asm/cacheflush.h \ ./.drm_cache.o.cmd:920: include/asm-generic/cacheflush.h \ ./.drm_cache.o.cmd:830: include/linux/cacheflush.h \ ./.drm_cache.o.cmd:831: arch/arm64/include/asm/cacheflush.h \ ./.drm_cache.o.cmd:1085: include/asm-generic/cacheflush.h \ So it seems without including it, cacheflush.h stills get pulled in, I think its because its a required kernel source to build the kernel per specific architecture, but please correct if I am wrong,as I am still trying to understand how things works!
Probably:
drm_cache.c:
#include <linux/highmem.h>
linux/highmem.h:
#include <linux/cacheflush.h>
But it is more correct to explicitly include what you use. So if drm_cache.c uses stuff declared in cacheflush.h, it should include it.
Regards,
Tvrtko
Michael Cheng On 2022-02-25 8:28 a.m., Tvrtko Ursulin wrote:
On 25/02/2022 03:24, Michael Cheng wrote:
Add arm64 support for drm_clflush_virt_range. caches_clean_inval_pou performs a flush by first performing a clean, follow by an invalidation operation.
v2 (Michael Cheng): Use correct macro for cleaning and invalidation the dcache. Thanks Tvrtko for the suggestion.
v3 (Michael Cheng): Replace asm/cacheflush.h with linux/cacheflush.h
v4 (Michael Cheng): Arm64 does not export dcache_clean_inval_poc as a symbol that could be use by other modules, thus use caches_clean_inval_pou instead. Also this version removes include for cacheflush, since its already included base on architecture type.
What does it mean that it is included based on architecture type? Some of the other header already pulls it in?
Regards,
Tvrtko
Signed-off-by: Michael Cheng michael.cheng@intel.com Reviewed-by: Matt Roper matthew.d.roper@intel.com
drivers/gpu/drm/drm_cache.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c index c3e6e615bf09..81c28714f930 100644 --- a/drivers/gpu/drm/drm_cache.c +++ b/drivers/gpu/drm/drm_cache.c @@ -174,6 +174,11 @@ drm_clflush_virt_range(void *addr, unsigned long length) if (wbinvd_on_all_cpus()) pr_err("Timed out waiting for cache flush\n");
+#elif defined(CONFIG_ARM64) + void *end = addr + length; + caches_clean_inval_pou((unsigned long)addr, (unsigned long)end);
#else WARN_ONCE(1, "Architecture has no drm_cache.c support\n"); #endif
Ah, thanks for pointing that out, when I do include it though, it causes a few warning other systems such as h8300 and s390.
Since it is already pulled is, would it be OK to leave it out for this case? Or we could use something like !IS_H8300 and !IS_S390
around the header file?
On 2022-02-25 9:33 a.m., Tvrtko Ursulin wrote:
On 25/02/2022 16:52, Michael Cheng wrote:
Hi Tvrtko,
It seems without cacheflush.h being included, when I build for arm64 or x86, it stills pulls in cacheflush.h:
./.drm_cache.o.cmd:838: include/linux/cacheflush.h \ ./.drm_cache.o.cmd:839: arch/x86/include/asm/cacheflush.h \ ./.drm_cache.o.cmd:920: include/asm-generic/cacheflush.h \ ./.drm_cache.o.cmd:830: include/linux/cacheflush.h \ ./.drm_cache.o.cmd:831: arch/arm64/include/asm/cacheflush.h \ ./.drm_cache.o.cmd:1085: include/asm-generic/cacheflush.h \ So it seems without including it, cacheflush.h stills get pulled in, I think its because its a required kernel source to build the kernel per specific architecture, but please correct if I am wrong,as I am still trying to understand how things works!
Probably:
drm_cache.c:
#include <linux/highmem.h>
linux/highmem.h:
#include <linux/cacheflush.h>
But it is more correct to explicitly include what you use. So if drm_cache.c uses stuff declared in cacheflush.h, it should include it.
Regards,
Tvrtko
Michael Cheng On 2022-02-25 8:28 a.m., Tvrtko Ursulin wrote:
On 25/02/2022 03:24, Michael Cheng wrote:
Add arm64 support for drm_clflush_virt_range. caches_clean_inval_pou performs a flush by first performing a clean, follow by an invalidation operation.
v2 (Michael Cheng): Use correct macro for cleaning and invalidation the dcache. Thanks Tvrtko for the suggestion.
v3 (Michael Cheng): Replace asm/cacheflush.h with linux/cacheflush.h
v4 (Michael Cheng): Arm64 does not export dcache_clean_inval_poc as a symbol that could be use by other modules, thus use caches_clean_inval_pou instead. Also this version removes include for cacheflush, since its already included base on architecture type.
What does it mean that it is included based on architecture type? Some of the other header already pulls it in?
Regards,
Tvrtko
Signed-off-by: Michael Cheng michael.cheng@intel.com Reviewed-by: Matt Roper matthew.d.roper@intel.com
drivers/gpu/drm/drm_cache.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c index c3e6e615bf09..81c28714f930 100644 --- a/drivers/gpu/drm/drm_cache.c +++ b/drivers/gpu/drm/drm_cache.c @@ -174,6 +174,11 @@ drm_clflush_virt_range(void *addr, unsigned long length) if (wbinvd_on_all_cpus()) pr_err("Timed out waiting for cache flush\n");
+#elif defined(CONFIG_ARM64) + void *end = addr + length; + caches_clean_inval_pou((unsigned long)addr, (unsigned long)end);
#else WARN_ONCE(1, "Architecture has no drm_cache.c support\n"); #endif
On 25/02/2022 17:40, Michael Cheng wrote:
Ah, thanks for pointing that out, when I do include it though, it causes a few warning other systems such as h8300 and s390.
Errors look like? I haven't heard that kernel code is not allowed to include something from linux/ on some arch yet.
Since it is already pulled is, would it be OK to leave it out for this case? Or we could use something like !IS_H8300 and !IS_S390
around the header file?
Unlikely, now you made me curious why it does not work.
Regards,
Tvrtko
On 2022-02-25 9:33 a.m., Tvrtko Ursulin wrote:
On 25/02/2022 16:52, Michael Cheng wrote:
Hi Tvrtko,
It seems without cacheflush.h being included, when I build for arm64 or x86, it stills pulls in cacheflush.h:
./.drm_cache.o.cmd:838: include/linux/cacheflush.h \ ./.drm_cache.o.cmd:839: arch/x86/include/asm/cacheflush.h \ ./.drm_cache.o.cmd:920: include/asm-generic/cacheflush.h \ ./.drm_cache.o.cmd:830: include/linux/cacheflush.h \ ./.drm_cache.o.cmd:831: arch/arm64/include/asm/cacheflush.h \ ./.drm_cache.o.cmd:1085: include/asm-generic/cacheflush.h \ So it seems without including it, cacheflush.h stills get pulled in, I think its because its a required kernel source to build the kernel per specific architecture, but please correct if I am wrong,as I am still trying to understand how things works!
Probably:
drm_cache.c:
#include <linux/highmem.h>
linux/highmem.h:
#include <linux/cacheflush.h>
But it is more correct to explicitly include what you use. So if drm_cache.c uses stuff declared in cacheflush.h, it should include it.
Regards,
Tvrtko
Michael Cheng On 2022-02-25 8:28 a.m., Tvrtko Ursulin wrote:
On 25/02/2022 03:24, Michael Cheng wrote:
Add arm64 support for drm_clflush_virt_range. caches_clean_inval_pou performs a flush by first performing a clean, follow by an invalidation operation.
v2 (Michael Cheng): Use correct macro for cleaning and invalidation the dcache. Thanks Tvrtko for the suggestion.
v3 (Michael Cheng): Replace asm/cacheflush.h with linux/cacheflush.h
v4 (Michael Cheng): Arm64 does not export dcache_clean_inval_poc as a symbol that could be use by other modules, thus use caches_clean_inval_pou instead. Also this version removes include for cacheflush, since its already included base on architecture type.
What does it mean that it is included based on architecture type? Some of the other header already pulls it in?
Regards,
Tvrtko
Signed-off-by: Michael Cheng michael.cheng@intel.com Reviewed-by: Matt Roper matthew.d.roper@intel.com
drivers/gpu/drm/drm_cache.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c index c3e6e615bf09..81c28714f930 100644 --- a/drivers/gpu/drm/drm_cache.c +++ b/drivers/gpu/drm/drm_cache.c @@ -174,6 +174,11 @@ drm_clflush_virt_range(void *addr, unsigned long length) if (wbinvd_on_all_cpus()) pr_err("Timed out waiting for cache flush\n");
+#elif defined(CONFIG_ARM64) + void *end = addr + length; + caches_clean_inval_pou((unsigned long)addr, (unsigned long)end);
#else WARN_ONCE(1, "Architecture has no drm_cache.c support\n"); #endif
These seem to be pretty old arch and are day0 warnings, please refer to [1] to see the warnings. Also I am not sure why my patch series didn't append to the old one.
[1] https://patchwork.freedesktop.org/patch/475829/?series=99450&rev=11
2022-02-25 10:19 a.m., Tvrtko Ursulin wrote:
On 25/02/2022 17:40, Michael Cheng wrote:
Ah, thanks for pointing that out, when I do include it though, it causes a few warning other systems such as h8300 and s390.
Errors look like? I haven't heard that kernel code is not allowed to include something from linux/ on some arch yet.
Since it is already pulled is, would it be OK to leave it out for this case? Or we could use something like !IS_H8300 and !IS_S390
around the header file?
Unlikely, now you made me curious why it does not work.
Regards,
Tvrtko
On 2022-02-25 9:33 a.m., Tvrtko Ursulin wrote:
On 25/02/2022 16:52, Michael Cheng wrote:
Hi Tvrtko,
It seems without cacheflush.h being included, when I build for arm64 or x86, it stills pulls in cacheflush.h:
./.drm_cache.o.cmd:838: include/linux/cacheflush.h \ ./.drm_cache.o.cmd:839: arch/x86/include/asm/cacheflush.h \ ./.drm_cache.o.cmd:920: include/asm-generic/cacheflush.h \ ./.drm_cache.o.cmd:830: include/linux/cacheflush.h \ ./.drm_cache.o.cmd:831: arch/arm64/include/asm/cacheflush.h \ ./.drm_cache.o.cmd:1085: include/asm-generic/cacheflush.h \ So it seems without including it, cacheflush.h stills get pulled in, I think its because its a required kernel source to build the kernel per specific architecture, but please correct if I am wrong,as I am still trying to understand how things works!
Probably:
drm_cache.c:
#include <linux/highmem.h>
linux/highmem.h:
#include <linux/cacheflush.h>
But it is more correct to explicitly include what you use. So if drm_cache.c uses stuff declared in cacheflush.h, it should include it.
Regards,
Tvrtko
Michael Cheng On 2022-02-25 8:28 a.m., Tvrtko Ursulin wrote:
On 25/02/2022 03:24, Michael Cheng wrote:
Add arm64 support for drm_clflush_virt_range. caches_clean_inval_pou performs a flush by first performing a clean, follow by an invalidation operation.
v2 (Michael Cheng): Use correct macro for cleaning and invalidation the dcache. Thanks Tvrtko for the suggestion.
v3 (Michael Cheng): Replace asm/cacheflush.h with linux/cacheflush.h
v4 (Michael Cheng): Arm64 does not export dcache_clean_inval_poc as a symbol that could be use by other modules, thus use caches_clean_inval_pou instead. Also this version removes include for cacheflush, since its already included base on architecture type.
What does it mean that it is included based on architecture type? Some of the other header already pulls it in?
Regards,
Tvrtko
Signed-off-by: Michael Cheng michael.cheng@intel.com Reviewed-by: Matt Roper matthew.d.roper@intel.com
drivers/gpu/drm/drm_cache.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c index c3e6e615bf09..81c28714f930 100644 --- a/drivers/gpu/drm/drm_cache.c +++ b/drivers/gpu/drm/drm_cache.c @@ -174,6 +174,11 @@ drm_clflush_virt_range(void *addr, unsigned long length) if (wbinvd_on_all_cpus()) pr_err("Timed out waiting for cache flush\n");
+#elif defined(CONFIG_ARM64) + void *end = addr + length; + caches_clean_inval_pou((unsigned long)addr, (unsigned long)end);
#else WARN_ONCE(1, "Architecture has no drm_cache.c support\n"); #endif
On 25/02/2022 18:23, Michael Cheng wrote:
These seem to be pretty old arch and are day0 warnings, please refer to [1] to see the warnings. Also I am not sure why my patch series didn't append to the old one.
[1] https://patchwork.freedesktop.org/patch/475829/?series=99450&rev=11
include/linux/cacheflush.h:12:46: warning: declaration of 'struct folio' will not be visible outside of this function [-Wvisibility]
That?
Looks like the #else path needs to forward declare struct folio or include the relevant header.
+Matthew Wilcox
Matthew, what do you think fix for this build warning on h8300 and s390 should be? Or perhaps a build environment issue with kernel test robot?
Regards,
Tvrtko
2022-02-25 10:19 a.m., Tvrtko Ursulin wrote:
On 25/02/2022 17:40, Michael Cheng wrote:
Ah, thanks for pointing that out, when I do include it though, it causes a few warning other systems such as h8300 and s390.
Errors look like? I haven't heard that kernel code is not allowed to include something from linux/ on some arch yet.
Since it is already pulled is, would it be OK to leave it out for this case? Or we could use something like !IS_H8300 and !IS_S390
around the header file?
Unlikely, now you made me curious why it does not work.
Regards,
Tvrtko
On 2022-02-25 9:33 a.m., Tvrtko Ursulin wrote:
On 25/02/2022 16:52, Michael Cheng wrote:
Hi Tvrtko,
It seems without cacheflush.h being included, when I build for arm64 or x86, it stills pulls in cacheflush.h:
./.drm_cache.o.cmd:838: include/linux/cacheflush.h \ ./.drm_cache.o.cmd:839: arch/x86/include/asm/cacheflush.h \ ./.drm_cache.o.cmd:920: include/asm-generic/cacheflush.h \ ./.drm_cache.o.cmd:830: include/linux/cacheflush.h \ ./.drm_cache.o.cmd:831: arch/arm64/include/asm/cacheflush.h \ ./.drm_cache.o.cmd:1085: include/asm-generic/cacheflush.h \ So it seems without including it, cacheflush.h stills get pulled in, I think its because its a required kernel source to build the kernel per specific architecture, but please correct if I am wrong,as I am still trying to understand how things works!
Probably:
drm_cache.c:
#include <linux/highmem.h>
linux/highmem.h:
#include <linux/cacheflush.h>
But it is more correct to explicitly include what you use. So if drm_cache.c uses stuff declared in cacheflush.h, it should include it.
Regards,
Tvrtko
Michael Cheng On 2022-02-25 8:28 a.m., Tvrtko Ursulin wrote:
On 25/02/2022 03:24, Michael Cheng wrote: > Add arm64 support for drm_clflush_virt_range. caches_clean_inval_pou > performs a flush by first performing a clean, follow by an > invalidation > operation. > > v2 (Michael Cheng): Use correct macro for cleaning and > invalidation the > dcache. Thanks Tvrtko for the suggestion. > > v3 (Michael Cheng): Replace asm/cacheflush.h with linux/cacheflush.h > > v4 (Michael Cheng): Arm64 does not export dcache_clean_inval_poc > as a > symbol that could be use by other modules, thus use > caches_clean_inval_pou instead. Also this version > removes include for cacheflush, since its already > included base on architecture type.
What does it mean that it is included based on architecture type? Some of the other header already pulls it in?
Regards,
Tvrtko
> Signed-off-by: Michael Cheng michael.cheng@intel.com > Reviewed-by: Matt Roper matthew.d.roper@intel.com > --- > drivers/gpu/drm/drm_cache.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/drm_cache.c > b/drivers/gpu/drm/drm_cache.c > index c3e6e615bf09..81c28714f930 100644 > --- a/drivers/gpu/drm/drm_cache.c > +++ b/drivers/gpu/drm/drm_cache.c > @@ -174,6 +174,11 @@ drm_clflush_virt_range(void *addr, unsigned > long length) > if (wbinvd_on_all_cpus()) > pr_err("Timed out waiting for cache flush\n"); > + > +#elif defined(CONFIG_ARM64) > + void *end = addr + length; > + caches_clean_inval_pou((unsigned long)addr, (unsigned > long)end); > + > #else > WARN_ONCE(1, "Architecture has no drm_cache.c support\n"); > #endif
On Fri, Feb 25, 2022 at 06:42:37PM +0000, Tvrtko Ursulin wrote:
Matthew, what do you think fix for this build warning on h8300 and s390 should be? Or perhaps a build environment issue with kernel test robot?
I'd suggest this should do the job:
+++ b/include/linux/cacheflush.h @@ -4,6 +4,8 @@
#include <asm/cacheflush.h>
+struct folio; + #if ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE #ifndef ARCH_IMPLEMENTS_FLUSH_DCACHE_FOLIO void flush_dcache_folio(struct folio *folio);
[ +arm64 maintainers for their awareness, which would have been a good thing to do from the start ]
On 2022-02-25 03:24, Michael Cheng wrote:
Add arm64 support for drm_clflush_virt_range. caches_clean_inval_pou performs a flush by first performing a clean, follow by an invalidation operation.
v2 (Michael Cheng): Use correct macro for cleaning and invalidation the dcache. Thanks Tvrtko for the suggestion.
v3 (Michael Cheng): Replace asm/cacheflush.h with linux/cacheflush.h
v4 (Michael Cheng): Arm64 does not export dcache_clean_inval_poc as a symbol that could be use by other modules, thus use caches_clean_inval_pou instead. Also this version removes include for cacheflush, since its already included base on architecture type.
Signed-off-by: Michael Cheng michael.cheng@intel.com Reviewed-by: Matt Roper matthew.d.roper@intel.com
drivers/gpu/drm/drm_cache.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c index c3e6e615bf09..81c28714f930 100644 --- a/drivers/gpu/drm/drm_cache.c +++ b/drivers/gpu/drm/drm_cache.c @@ -174,6 +174,11 @@ drm_clflush_virt_range(void *addr, unsigned long length)
if (wbinvd_on_all_cpus()) pr_err("Timed out waiting for cache flush\n");
+#elif defined(CONFIG_ARM64)
- void *end = addr + length;
- caches_clean_inval_pou((unsigned long)addr, (unsigned long)end);
Why does i915 need to ensure the CPU's instruction cache is coherent with its data cache? Is it a self-modifying driver?
Robin.
(Note that the above is somewhat of a loaded question, and I do actually have half an idea of what you're trying to do here and why it won't fly, but I'd like to at least assume you've read the documentation of the function you decided was OK to use)
- #else WARN_ONCE(1, "Architecture has no drm_cache.c support\n"); #endif
Hi Robin,
[ +arm64 maintainers for their awareness, which would have been a good thing to do from the start ]
* Thanks for adding the arm64 maintainer and sorry I didn't rope them in sooner.
Why does i915 need to ensure the CPU's instruction cache is coherent with its data cache? Is it a self-modifying driver?
* Also thanks for pointing this out. Initially I was using dcache_clean_inval_poc, which seem to be the equivalently to what x86 is doing for dcache flushing, but it was giving me build errors since its not on the global list of kernel symbols. And after revisiting the documentation for caches_clean_inval_pou, it won't fly for what we are trying to do. Moving forward, what would you (or someone in the ARM community) suggest we do? Could it be possible to export dcache_clean_inval_poc as a global symbol?
On 2022-02-25 10:24 a.m., Robin Murphy wrote:
[ +arm64 maintainers for their awareness, which would have been a good thing to do from the start ]
On 2022-02-25 03:24, Michael Cheng wrote:
Add arm64 support for drm_clflush_virt_range. caches_clean_inval_pou performs a flush by first performing a clean, follow by an invalidation operation.
v2 (Michael Cheng): Use correct macro for cleaning and invalidation the dcache. Thanks Tvrtko for the suggestion.
v3 (Michael Cheng): Replace asm/cacheflush.h with linux/cacheflush.h
v4 (Michael Cheng): Arm64 does not export dcache_clean_inval_poc as a symbol that could be use by other modules, thus use caches_clean_inval_pou instead. Also this version removes include for cacheflush, since its already included base on architecture type.
Signed-off-by: Michael Cheng michael.cheng@intel.com Reviewed-by: Matt Roper matthew.d.roper@intel.com
drivers/gpu/drm/drm_cache.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c index c3e6e615bf09..81c28714f930 100644 --- a/drivers/gpu/drm/drm_cache.c +++ b/drivers/gpu/drm/drm_cache.c @@ -174,6 +174,11 @@ drm_clflush_virt_range(void *addr, unsigned long length) if (wbinvd_on_all_cpus()) pr_err("Timed out waiting for cache flush\n");
+#elif defined(CONFIG_ARM64) + void *end = addr + length; + caches_clean_inval_pou((unsigned long)addr, (unsigned long)end);
Why does i915 need to ensure the CPU's instruction cache is coherent with its data cache? Is it a self-modifying driver?
Robin.
(Note that the above is somewhat of a loaded question, and I do actually have half an idea of what you're trying to do here and why it won't fly, but I'd like to at least assume you've read the documentation of the function you decided was OK to use)
#else WARN_ONCE(1, "Architecture has no drm_cache.c support\n"); #endif
On 2022-02-25 19:27, Michael Cheng wrote:
Hi Robin,
[ +arm64 maintainers for their awareness, which would have been a good thing to do from the start ]
* Thanks for adding the arm64 maintainer and sorry I didn't rope them in sooner.
Why does i915 need to ensure the CPU's instruction cache is coherent with its data cache? Is it a self-modifying driver?
* Also thanks for pointing this out. Initially I was using dcache_clean_inval_poc, which seem to be the equivalently to what x86 is doing for dcache flushing, but it was giving me build errors since its not on the global list of kernel symbols. And after revisiting the documentation for caches_clean_inval_pou, it won't fly for what we are trying to do. Moving forward, what would you (or someone in the ARM community) suggest we do? Could it be possible to export dcache_clean_inval_poc as a global symbol?
Unlikely, unless something with a legitimate need for CPU-centric cache maintenance like kexec or CPU hotplug ever becomes modular.
In the case of a device driver, it's not even the basic issues of assuming to find direct equivalents to x86 semantics in other CPU architectures, or effectively reinventing parts of the DMA API, it's even bigger than that. Once you move from being integrated in a single vendor's system architecture to being on a discrete card, you fundamentally *no longer have any control over cache coherency*. Whether the host CPU architecture happens to be AArch64, RISC-V, or whatever doesn't really matter, you're at the mercy of 3rd-party PCIe and interconnect IP vendors, and SoC integrators. You'll find yourself in systems where PCIe simply cannot snoop any caches, where you'd better have the correct DMA API calls in place to have any hope of even the most basic functionality working properly; you'll find yourself in systems where even if the PCIe root complex claims to support No Snoop, your uncached traffic will still end up snooping stale data that got prefetched back into caches you thought you'd invalidated; you'll find yourself in systems where your memory attributes may or may not get forcibly rewritten by an IOMMU depending on the kernel config and/or command line.
It's not about simply finding a substitute for clflush, it's that the reasons you have for using clflush in the first place can no longer be assumed to be valid.
Robin.
On 2022-02-25 10:24 a.m., Robin Murphy wrote:
[ +arm64 maintainers for their awareness, which would have been a good thing to do from the start ]
On 2022-02-25 03:24, Michael Cheng wrote:
Add arm64 support for drm_clflush_virt_range. caches_clean_inval_pou performs a flush by first performing a clean, follow by an invalidation operation.
v2 (Michael Cheng): Use correct macro for cleaning and invalidation the dcache. Thanks Tvrtko for the suggestion.
v3 (Michael Cheng): Replace asm/cacheflush.h with linux/cacheflush.h
v4 (Michael Cheng): Arm64 does not export dcache_clean_inval_poc as a symbol that could be use by other modules, thus use caches_clean_inval_pou instead. Also this version removes include for cacheflush, since its already included base on architecture type.
Signed-off-by: Michael Cheng michael.cheng@intel.com Reviewed-by: Matt Roper matthew.d.roper@intel.com
drivers/gpu/drm/drm_cache.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c index c3e6e615bf09..81c28714f930 100644 --- a/drivers/gpu/drm/drm_cache.c +++ b/drivers/gpu/drm/drm_cache.c @@ -174,6 +174,11 @@ drm_clflush_virt_range(void *addr, unsigned long length) if (wbinvd_on_all_cpus()) pr_err("Timed out waiting for cache flush\n");
+#elif defined(CONFIG_ARM64) + void *end = addr + length; + caches_clean_inval_pou((unsigned long)addr, (unsigned long)end);
Why does i915 need to ensure the CPU's instruction cache is coherent with its data cache? Is it a self-modifying driver?
Robin.
(Note that the above is somewhat of a loaded question, and I do actually have half an idea of what you're trying to do here and why it won't fly, but I'd like to at least assume you've read the documentation of the function you decided was OK to use)
#else WARN_ONCE(1, "Architecture has no drm_cache.c support\n"); #endif
Thanks for the feedback Robin!
Sorry my choices of word weren't that great, but what I meant is to understand how ARM flushes a range of dcache for device drivers, and not an equal to x86 clflush.
I believe the concern is if the CPU writes an update, that update might only be sitting in the CPU cache and never make it to device memory where the device can see it; there are specific places that we are supposed to flush the CPU caches to make sure our updates are visible to the hardware.
+Matt Roper
Matt, Lucas, any feed back here?
On 2022-03-02 4:49 a.m., Robin Murphy wrote:
On 2022-02-25 19:27, Michael Cheng wrote:
Hi Robin,
[ +arm64 maintainers for their awareness, which would have been a good thing to do from the start ]
* Thanks for adding the arm64 maintainer and sorry I didn't rope them in sooner.
Why does i915 need to ensure the CPU's instruction cache is coherent with its data cache? Is it a self-modifying driver?
* Also thanks for pointing this out. Initially I was using dcache_clean_inval_poc, which seem to be the equivalently to what x86 is doing for dcache flushing, but it was giving me build errors since its not on the global list of kernel symbols. And after revisiting the documentation for caches_clean_inval_pou, it won't fly for what we are trying to do. Moving forward, what would you (or someone in the ARM community) suggest we do? Could it be possible to export dcache_clean_inval_poc as a global symbol?
Unlikely, unless something with a legitimate need for CPU-centric cache maintenance like kexec or CPU hotplug ever becomes modular.
In the case of a device driver, it's not even the basic issues of assuming to find direct equivalents to x86 semantics in other CPU architectures, or effectively reinventing parts of the DMA API, it's even bigger than that. Once you move from being integrated in a single vendor's system architecture to being on a discrete card, you fundamentally *no longer have any control over cache coherency*. Whether the host CPU architecture happens to be AArch64, RISC-V, or whatever doesn't really matter, you're at the mercy of 3rd-party PCIe and interconnect IP vendors, and SoC integrators. You'll find yourself in systems where PCIe simply cannot snoop any caches, where you'd better have the correct DMA API calls in place to have any hope of even the most basic functionality working properly; you'll find yourself in systems where even if the PCIe root complex claims to support No Snoop, your uncached traffic will still end up snooping stale data that got prefetched back into caches you thought you'd invalidated; you'll find yourself in systems where your memory attributes may or may not get forcibly rewritten by an IOMMU depending on the kernel config and/or command line.
It's not about simply finding a substitute for clflush, it's that the reasons you have for using clflush in the first place can no longer be assumed to be valid.
Robin.
On 2022-02-25 10:24 a.m., Robin Murphy wrote:
[ +arm64 maintainers for their awareness, which would have been a good thing to do from the start ]
On 2022-02-25 03:24, Michael Cheng wrote:
Add arm64 support for drm_clflush_virt_range. caches_clean_inval_pou performs a flush by first performing a clean, follow by an invalidation operation.
v2 (Michael Cheng): Use correct macro for cleaning and invalidation the dcache. Thanks Tvrtko for the suggestion.
v3 (Michael Cheng): Replace asm/cacheflush.h with linux/cacheflush.h
v4 (Michael Cheng): Arm64 does not export dcache_clean_inval_poc as a symbol that could be use by other modules, thus use caches_clean_inval_pou instead. Also this version removes include for cacheflush, since its already included base on architecture type.
Signed-off-by: Michael Cheng michael.cheng@intel.com Reviewed-by: Matt Roper matthew.d.roper@intel.com
drivers/gpu/drm/drm_cache.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c index c3e6e615bf09..81c28714f930 100644 --- a/drivers/gpu/drm/drm_cache.c +++ b/drivers/gpu/drm/drm_cache.c @@ -174,6 +174,11 @@ drm_clflush_virt_range(void *addr, unsigned long length) if (wbinvd_on_all_cpus()) pr_err("Timed out waiting for cache flush\n");
+#elif defined(CONFIG_ARM64) + void *end = addr + length; + caches_clean_inval_pou((unsigned long)addr, (unsigned long)end);
Why does i915 need to ensure the CPU's instruction cache is coherent with its data cache? Is it a self-modifying driver?
Robin.
(Note that the above is somewhat of a loaded question, and I do actually have half an idea of what you're trying to do here and why it won't fly, but I'd like to at least assume you've read the documentation of the function you decided was OK to use)
#else WARN_ONCE(1, "Architecture has no drm_cache.c support\n"); #endif
On Wed, Mar 2, 2022 at 10:55 AM Michael Cheng michael.cheng@intel.com wrote:
Thanks for the feedback Robin!
Sorry my choices of word weren't that great, but what I meant is to understand how ARM flushes a range of dcache for device drivers, and not an equal to x86 clflush.
I believe the concern is if the CPU writes an update, that update might only be sitting in the CPU cache and never make it to device memory where the device can see it; there are specific places that we are supposed to flush the CPU caches to make sure our updates are visible to the hardware.
+Matt Roper
Matt, Lucas, any feed back here?
MMIO (e.g., PCI BARs, etc.) should be mapped uncached. If it's not you'll have a lot of problems using a GPU on that architecture. One thing that you may want to check is if your device has its own caches or write queues on the BAR aperture. You may have to flush them after CPU access to the BAR to make sure CPU updates land in device memory. For system memory, PCI, per the spec, should be cache coherent with the CPU. If it's not, you'll have a lot of trouble using a GPU on that platform.
Alex
On 2022-03-02 4:49 a.m., Robin Murphy wrote:
On 2022-02-25 19:27, Michael Cheng wrote:
Hi Robin,
[ +arm64 maintainers for their awareness, which would have been a good thing to do from the start ]
- Thanks for adding the arm64 maintainer and sorry I didn't rope them in sooner.
Why does i915 need to ensure the CPU's instruction cache is coherent with its data cache? Is it a self-modifying driver?
- Also thanks for pointing this out. Initially I was using dcache_clean_inval_poc, which seem to be the equivalently to what x86 is doing for dcache flushing, but it was giving me build errors since its not on the global list of kernel symbols. And after revisiting the documentation for caches_clean_inval_pou, it won't fly for what we are trying to do. Moving forward, what would you (or someone in the ARM community) suggest we do? Could it be possible to export dcache_clean_inval_poc as a global symbol?
Unlikely, unless something with a legitimate need for CPU-centric cache maintenance like kexec or CPU hotplug ever becomes modular.
In the case of a device driver, it's not even the basic issues of assuming to find direct equivalents to x86 semantics in other CPU architectures, or effectively reinventing parts of the DMA API, it's even bigger than that. Once you move from being integrated in a single vendor's system architecture to being on a discrete card, you fundamentally *no longer have any control over cache coherency*. Whether the host CPU architecture happens to be AArch64, RISC-V, or whatever doesn't really matter, you're at the mercy of 3rd-party PCIe and interconnect IP vendors, and SoC integrators. You'll find yourself in systems where PCIe simply cannot snoop any caches, where you'd better have the correct DMA API calls in place to have any hope of even the most basic functionality working properly; you'll find yourself in systems where even if the PCIe root complex claims to support No Snoop, your uncached traffic will still end up snooping stale data that got prefetched back into caches you thought you'd invalidated; you'll find yourself in systems where your memory attributes may or may not get forcibly rewritten by an IOMMU depending on the kernel config and/or command line.
It's not about simply finding a substitute for clflush, it's that the reasons you have for using clflush in the first place can no longer be assumed to be valid.
Robin.
On 2022-02-25 10:24 a.m., Robin Murphy wrote:
[ +arm64 maintainers for their awareness, which would have been a good thing to do from the start ]
On 2022-02-25 03:24, Michael Cheng wrote:
Add arm64 support for drm_clflush_virt_range. caches_clean_inval_pou performs a flush by first performing a clean, follow by an invalidation operation.
v2 (Michael Cheng): Use correct macro for cleaning and invalidation the dcache. Thanks Tvrtko for the suggestion.
v3 (Michael Cheng): Replace asm/cacheflush.h with linux/cacheflush.h
v4 (Michael Cheng): Arm64 does not export dcache_clean_inval_poc as a symbol that could be use by other modules, thus use caches_clean_inval_pou instead. Also this version removes include for cacheflush, since its already included base on architecture type.
Signed-off-by: Michael Cheng michael.cheng@intel.com Reviewed-by: Matt Roper matthew.d.roper@intel.com
drivers/gpu/drm/drm_cache.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c index c3e6e615bf09..81c28714f930 100644 --- a/drivers/gpu/drm/drm_cache.c +++ b/drivers/gpu/drm/drm_cache.c @@ -174,6 +174,11 @@ drm_clflush_virt_range(void *addr, unsigned long length) if (wbinvd_on_all_cpus()) pr_err("Timed out waiting for cache flush\n");
+#elif defined(CONFIG_ARM64)
- void *end = addr + length;
- caches_clean_inval_pou((unsigned long)addr, (unsigned long)end);
Why does i915 need to ensure the CPU's instruction cache is coherent with its data cache? Is it a self-modifying driver?
Robin.
(Note that the above is somewhat of a loaded question, and I do actually have half an idea of what you're trying to do here and why it won't fly, but I'd like to at least assume you've read the documentation of the function you decided was OK to use)
- #else WARN_ONCE(1, "Architecture has no drm_cache.c support\n"); #endif
On 2022-03-02 15:55, Michael Cheng wrote:
Thanks for the feedback Robin!
Sorry my choices of word weren't that great, but what I meant is to understand how ARM flushes a range of dcache for device drivers, and not an equal to x86 clflush.
I believe the concern is if the CPU writes an update, that update might only be sitting in the CPU cache and never make it to device memory where the device can see it; there are specific places that we are supposed to flush the CPU caches to make sure our updates are visible to the hardware.
Ah, OK, if it's more about ordering, and it's actually write buffers rather than caches that you care about flushing, then we might be a lot safer, phew!
For a very simple overview, in a case where the device itself needs to observe memory writes in the correct order, e.g.:
data_descriptor.valid = 1;
clflush(&data_descriptor);
command_descriptor.data = &data_descriptor
writel(/* control register to read command to then read data */)
then dma_wmb() between the first two writes should be the right tool to ensure that the command does not observe the command update while the data update is still sat somewhere in a CPU write buffer.
If you want a slightly stronger notion that, at a given point, all prior writes have actually been issued and should now be visible (rather than just that they won't become visible in the wrong order whenever they do), then wmb() should suffice on arm64.
Note that wioth arm64 memory types, a Non-Cacheable mapping of DRAM for a non-coherent DMA mapping, or of VRAM in a prefetchable BAR, can still be write-buffered, so barriers still matter even when actual cache maintenance ops don't (and as before if you're trying to perform cache maintenance outside the DMA API then you've already lost anyway). MMIO registers should be mapped as Device memory via ioremap(), which is not bufferable, hence the barrier implicit in writel() effectively pushes out any prior buffered writes ahead of a register write, which is why we don't need to worry about this most of the time.
This is only a very rough overview, though, and I'm not familiar enough with x86 semantics, your hardware, or the exact use-case to be able to say whether barriers alone are anywhere near the right answer or not.
Robin.
+Matt Roper
Matt, Lucas, any feed back here?
On 2022-03-02 4:49 a.m., Robin Murphy wrote:
On 2022-02-25 19:27, Michael Cheng wrote:
Hi Robin,
[ +arm64 maintainers for their awareness, which would have been a good thing to do from the start ]
* Thanks for adding the arm64 maintainer and sorry I didn't rope them in sooner.
Why does i915 need to ensure the CPU's instruction cache is coherent with its data cache? Is it a self-modifying driver?
* Also thanks for pointing this out. Initially I was using dcache_clean_inval_poc, which seem to be the equivalently to what x86 is doing for dcache flushing, but it was giving me build errors since its not on the global list of kernel symbols. And after revisiting the documentation for caches_clean_inval_pou, it won't fly for what we are trying to do. Moving forward, what would you (or someone in the ARM community) suggest we do? Could it be possible to export dcache_clean_inval_poc as a global symbol?
Unlikely, unless something with a legitimate need for CPU-centric cache maintenance like kexec or CPU hotplug ever becomes modular.
In the case of a device driver, it's not even the basic issues of assuming to find direct equivalents to x86 semantics in other CPU architectures, or effectively reinventing parts of the DMA API, it's even bigger than that. Once you move from being integrated in a single vendor's system architecture to being on a discrete card, you fundamentally *no longer have any control over cache coherency*. Whether the host CPU architecture happens to be AArch64, RISC-V, or whatever doesn't really matter, you're at the mercy of 3rd-party PCIe and interconnect IP vendors, and SoC integrators. You'll find yourself in systems where PCIe simply cannot snoop any caches, where you'd better have the correct DMA API calls in place to have any hope of even the most basic functionality working properly; you'll find yourself in systems where even if the PCIe root complex claims to support No Snoop, your uncached traffic will still end up snooping stale data that got prefetched back into caches you thought you'd invalidated; you'll find yourself in systems where your memory attributes may or may not get forcibly rewritten by an IOMMU depending on the kernel config and/or command line.
It's not about simply finding a substitute for clflush, it's that the reasons you have for using clflush in the first place can no longer be assumed to be valid.
Robin.
On 2022-02-25 10:24 a.m., Robin Murphy wrote:
[ +arm64 maintainers for their awareness, which would have been a good thing to do from the start ]
On 2022-02-25 03:24, Michael Cheng wrote:
Add arm64 support for drm_clflush_virt_range. caches_clean_inval_pou performs a flush by first performing a clean, follow by an invalidation operation.
v2 (Michael Cheng): Use correct macro for cleaning and invalidation the dcache. Thanks Tvrtko for the suggestion.
v3 (Michael Cheng): Replace asm/cacheflush.h with linux/cacheflush.h
v4 (Michael Cheng): Arm64 does not export dcache_clean_inval_poc as a symbol that could be use by other modules, thus use caches_clean_inval_pou instead. Also this version removes include for cacheflush, since its already included base on architecture type.
Signed-off-by: Michael Cheng michael.cheng@intel.com Reviewed-by: Matt Roper matthew.d.roper@intel.com
drivers/gpu/drm/drm_cache.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c index c3e6e615bf09..81c28714f930 100644 --- a/drivers/gpu/drm/drm_cache.c +++ b/drivers/gpu/drm/drm_cache.c @@ -174,6 +174,11 @@ drm_clflush_virt_range(void *addr, unsigned long length) if (wbinvd_on_all_cpus()) pr_err("Timed out waiting for cache flush\n");
+#elif defined(CONFIG_ARM64) + void *end = addr + length; + caches_clean_inval_pou((unsigned long)addr, (unsigned long)end);
Why does i915 need to ensure the CPU's instruction cache is coherent with its data cache? Is it a self-modifying driver?
Robin.
(Note that the above is somewhat of a loaded question, and I do actually have half an idea of what you're trying to do here and why it won't fly, but I'd like to at least assume you've read the documentation of the function you decided was OK to use)
#else WARN_ONCE(1, "Architecture has no drm_cache.c support\n"); #endif
Ah Thanks for the great feedback!
@Lucas or @Matt, could you please chime in?
Michael Cheng
On 2022-03-02 11:10 a.m., Robin Murphy wrote:
On 2022-03-02 15:55, Michael Cheng wrote:
Thanks for the feedback Robin!
Sorry my choices of word weren't that great, but what I meant is to understand how ARM flushes a range of dcache for device drivers, and not an equal to x86 clflush.
I believe the concern is if the CPU writes an update, that update might only be sitting in the CPU cache and never make it to device memory where the device can see it; there are specific places that we are supposed to flush the CPU caches to make sure our updates are visible to the hardware.
Ah, OK, if it's more about ordering, and it's actually write buffers rather than caches that you care about flushing, then we might be a lot safer, phew!
For a very simple overview, in a case where the device itself needs to observe memory writes in the correct order, e.g.:
data_descriptor.valid = 1;
clflush(&data_descriptor);
command_descriptor.data = &data_descriptor
writel(/* control register to read command to then read data */)
then dma_wmb() between the first two writes should be the right tool to ensure that the command does not observe the command update while the data update is still sat somewhere in a CPU write buffer.
If you want a slightly stronger notion that, at a given point, all prior writes have actually been issued and should now be visible (rather than just that they won't become visible in the wrong order whenever they do), then wmb() should suffice on arm64.
Note that wioth arm64 memory types, a Non-Cacheable mapping of DRAM for a non-coherent DMA mapping, or of VRAM in a prefetchable BAR, can still be write-buffered, so barriers still matter even when actual cache maintenance ops don't (and as before if you're trying to perform cache maintenance outside the DMA API then you've already lost anyway). MMIO registers should be mapped as Device memory via ioremap(), which is not bufferable, hence the barrier implicit in writel() effectively pushes out any prior buffered writes ahead of a register write, which is why we don't need to worry about this most of the time.
This is only a very rough overview, though, and I'm not familiar enough with x86 semantics, your hardware, or the exact use-case to be able to say whether barriers alone are anywhere near the right answer or not.
Robin.
+Matt Roper
Matt, Lucas, any feed back here?
On 2022-03-02 4:49 a.m., Robin Murphy wrote:
On 2022-02-25 19:27, Michael Cheng wrote:
Hi Robin,
[ +arm64 maintainers for their awareness, which would have been a good thing to do from the start ]
* Thanks for adding the arm64 maintainer and sorry I didn't rope them in sooner.
Why does i915 need to ensure the CPU's instruction cache is coherent with its data cache? Is it a self-modifying driver?
* Also thanks for pointing this out. Initially I was using dcache_clean_inval_poc, which seem to be the equivalently to what x86 is doing for dcache flushing, but it was giving me build errors since its not on the global list of kernel symbols. And after revisiting the documentation for caches_clean_inval_pou, it won't fly for what we are trying to do. Moving forward, what would you (or someone in the ARM community) suggest we do? Could it be possible to export dcache_clean_inval_poc as a global symbol?
Unlikely, unless something with a legitimate need for CPU-centric cache maintenance like kexec or CPU hotplug ever becomes modular.
In the case of a device driver, it's not even the basic issues of assuming to find direct equivalents to x86 semantics in other CPU architectures, or effectively reinventing parts of the DMA API, it's even bigger than that. Once you move from being integrated in a single vendor's system architecture to being on a discrete card, you fundamentally *no longer have any control over cache coherency*. Whether the host CPU architecture happens to be AArch64, RISC-V, or whatever doesn't really matter, you're at the mercy of 3rd-party PCIe and interconnect IP vendors, and SoC integrators. You'll find yourself in systems where PCIe simply cannot snoop any caches, where you'd better have the correct DMA API calls in place to have any hope of even the most basic functionality working properly; you'll find yourself in systems where even if the PCIe root complex claims to support No Snoop, your uncached traffic will still end up snooping stale data that got prefetched back into caches you thought you'd invalidated; you'll find yourself in systems where your memory attributes may or may not get forcibly rewritten by an IOMMU depending on the kernel config and/or command line.
It's not about simply finding a substitute for clflush, it's that the reasons you have for using clflush in the first place can no longer be assumed to be valid.
Robin.
On 2022-02-25 10:24 a.m., Robin Murphy wrote:
[ +arm64 maintainers for their awareness, which would have been a good thing to do from the start ]
On 2022-02-25 03:24, Michael Cheng wrote:
Add arm64 support for drm_clflush_virt_range. caches_clean_inval_pou performs a flush by first performing a clean, follow by an invalidation operation.
v2 (Michael Cheng): Use correct macro for cleaning and invalidation the dcache. Thanks Tvrtko for the suggestion.
v3 (Michael Cheng): Replace asm/cacheflush.h with linux/cacheflush.h
v4 (Michael Cheng): Arm64 does not export dcache_clean_inval_poc as a symbol that could be use by other modules, thus use caches_clean_inval_pou instead. Also this version removes include for cacheflush, since its already included base on architecture type.
Signed-off-by: Michael Cheng michael.cheng@intel.com Reviewed-by: Matt Roper matthew.d.roper@intel.com
drivers/gpu/drm/drm_cache.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c index c3e6e615bf09..81c28714f930 100644 --- a/drivers/gpu/drm/drm_cache.c +++ b/drivers/gpu/drm/drm_cache.c @@ -174,6 +174,11 @@ drm_clflush_virt_range(void *addr, unsigned long length) if (wbinvd_on_all_cpus()) pr_err("Timed out waiting for cache flush\n");
+#elif defined(CONFIG_ARM64) + void *end = addr + length; + caches_clean_inval_pou((unsigned long)addr, (unsigned long)end);
Why does i915 need to ensure the CPU's instruction cache is coherent with its data cache? Is it a self-modifying driver?
Robin.
(Note that the above is somewhat of a loaded question, and I do actually have half an idea of what you're trying to do here and why it won't fly, but I'd like to at least assume you've read the documentation of the function you decided was OK to use)
#else WARN_ONCE(1, "Architecture has no drm_cache.c support\n"); #endif
Re-work intel_write_status_page to use drm_clflush_virt_range. This will prevent compiler errors when building for non-x86 architectures.
Signed-off-by: Michael Cheng michael.cheng@intel.com Reviewed-by: Matt Roper matthew.d.roper@intel.com --- drivers/gpu/drm/i915/gt/intel_engine.h | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h index be4b1e65442f..818468e0a02e 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine.h +++ b/drivers/gpu/drm/i915/gt/intel_engine.h @@ -4,6 +4,7 @@
#include <asm/cacheflush.h> #include <drm/drm_util.h> +#include <drm/drm_cache.h>
#include <linux/hashtable.h> #include <linux/irq_work.h> @@ -143,15 +144,9 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value) * of extra paranoia to try and ensure that the HWS takes the value * we give and that it doesn't end up trapped inside the CPU! */ - if (static_cpu_has(X86_FEATURE_CLFLUSH)) { - mb(); - clflush(&engine->status_page.addr[reg]); - engine->status_page.addr[reg] = value; - clflush(&engine->status_page.addr[reg]); - mb(); - } else { - WRITE_ONCE(engine->status_page.addr[reg], value); - } + drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value)); + WRITE_ONCE(engine->status_page.addr[reg], value); + drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value)); }
/*
Drop invalidate_csb_entries and directly call drm_clflush_virt_range. This allows for one less function call, and prevent complier errors when building for non-x86 architectures.
v2(Michael Cheng): Drop invalidate_csb_entries function and directly invoke drm_clflush_virt_range. Thanks to Tvrtko for the sugguestion.
v3(Michael Cheng): Use correct parameters for drm_clflush_virt_range. Thanks to Tvrtko for pointing this out.
v4(Michael Cheng): Simplify &execlists->csb_status[0] to execlists->csb_status. Thanks to Matt Roper for the suggestion.
Signed-off-by: Michael Cheng michael.cheng@intel.com Reviewed-by: Matt Roper matthew.d.roper@intel.com --- .../gpu/drm/i915/gt/intel_execlists_submission.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index 961d795220a3..e5e73a1b2e4e 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -1646,12 +1646,6 @@ cancel_port_requests(struct intel_engine_execlists * const execlists, return inactive; }
-static void invalidate_csb_entries(const u64 *first, const u64 *last) -{ - clflush((void *)first); - clflush((void *)last); -} - /* * Starting with Gen12, the status has a new format: * @@ -1999,7 +1993,7 @@ process_csb(struct intel_engine_cs *engine, struct i915_request **inactive) * the wash as hardware, working or not, will need to do the * invalidation before. */ - invalidate_csb_entries(&buf[0], &buf[num_entries - 1]); + drm_clflush_virt_range(&buf[0], num_entries * sizeof(buf[0]));
/* * We assume that any event reflects a change in context flow @@ -2783,8 +2777,9 @@ static void reset_csb_pointers(struct intel_engine_cs *engine)
/* Check that the GPU does indeed update the CSB entries! */ memset(execlists->csb_status, -1, (reset_value + 1) * sizeof(u64)); - invalidate_csb_entries(&execlists->csb_status[0], - &execlists->csb_status[reset_value]); + drm_clflush_virt_range(execlists->csb_status, + execlists->csb_size * + sizeof(execlists->csb_status));
/* Once more for luck and our trusty paranoia */ ENGINE_WRITE(engine, RING_CONTEXT_STATUS_PTR,
Use drm_clflush_virt_range instead of directly invoking clflush. This will prevent compiler errors when building for non-x86 architectures.
v2(Michael Cheng): Remove extra clflush
v3(Michael Cheng): Remove memory barrier since drm_clflush_virt_range takes care of it.
v4(Michael Cheng): Get the size of value and not the size of the pointer when passing in execlists->csb_write. Thanks to Matt Roper for pointing this out.
Signed-off-by: Michael Cheng michael.cheng@intel.com Reviewed-by: Matt Roper matthew.d.roper@intel.com --- drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index e5e73a1b2e4e..89aef3ce53f0 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -2945,9 +2945,8 @@ reset_csb(struct intel_engine_cs *engine, struct i915_request **inactive) { struct intel_engine_execlists * const execlists = &engine->execlists;
- mb(); /* paranoia: read the CSB pointers from after the reset */ - clflush(execlists->csb_write); - mb(); + drm_clflush_virt_range(execlists->csb_write, + sizeof(execlists->csb_write[0]));
inactive = process_csb(engine, inactive); /* drain preemption events */
Use drm_clflush_virt_range instead of clflushopt and remove the memory barrier, since drm_clflush_virt_range takes care of that.
v2(Michael Cheng): Use sizeof(*addr) instead of sizeof(addr) to get the actual size of the page. Thanks to Matt Roper for pointing this out.
Signed-off-by: Michael Cheng michael.cheng@intel.com Reviewed-by: Matt Roper matthew.d.roper@intel.com --- drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 89aa0557ade1..0ca6c3d810da 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -1333,10 +1333,8 @@ static void *reloc_vaddr(struct i915_vma *vma, static void clflush_write32(u32 *addr, u32 value, unsigned int flushes) { if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) { - if (flushes & CLFLUSH_BEFORE) { - clflushopt(addr); - mb(); - } + if (flushes & CLFLUSH_BEFORE) + drm_clflush_virt_range(addr, sizeof(*addr));
*addr = value;
@@ -1348,7 +1346,7 @@ static void clflush_write32(u32 *addr, u32 value, unsigned int flushes) * to ensure ordering of clflush wrt to the system. */ if (flushes & CLFLUSH_AFTER) - clflushopt(addr); + drm_clflush_virt_range(addr, sizeof(*addr)); } else *addr = value; }
Replace all occurrence of cache_clflush_range with drm_clflush_virt_range. This will prevent compile errors on non-x86 platforms.
Signed-off-by: Michael Cheng michael.cheng@intel.com Reviewed-by: Matt Roper matthew.d.roper@intel.com --- drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 12 ++++++------ drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +- drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +- drivers/gpu/drm/i915/gt/intel_ppgtt.c | 2 +- drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +- 5 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c index f574da00eff1..c7bd5d71b03e 100644 --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c @@ -454,11 +454,11 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt, pd = pdp->entry[gen8_pd_index(idx, 2)]; }
- clflush_cache_range(vaddr, PAGE_SIZE); + drm_clflush_virt_range(vaddr, PAGE_SIZE); vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1))); } } while (1); - clflush_cache_range(vaddr, PAGE_SIZE); + drm_clflush_virt_range(vaddr, PAGE_SIZE);
return idx; } @@ -631,7 +631,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm, } } while (rem >= page_size && index < I915_PDES);
- clflush_cache_range(vaddr, PAGE_SIZE); + drm_clflush_virt_range(vaddr, PAGE_SIZE);
/* * Is it safe to mark the 2M block as 64K? -- Either we have @@ -647,7 +647,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm, I915_GTT_PAGE_SIZE_2M)))) { vaddr = px_vaddr(pd); vaddr[maybe_64K] |= GEN8_PDE_IPS_64K; - clflush_cache_range(vaddr, PAGE_SIZE); + drm_clflush_virt_range(vaddr, PAGE_SIZE); page_size = I915_GTT_PAGE_SIZE_64K;
/* @@ -668,7 +668,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm, for (i = 1; i < index; i += 16) memset64(vaddr + i, encode, 15);
- clflush_cache_range(vaddr, PAGE_SIZE); + drm_clflush_virt_range(vaddr, PAGE_SIZE); } }
@@ -722,7 +722,7 @@ static void gen8_ppgtt_insert_entry(struct i915_address_space *vm,
vaddr = px_vaddr(pt); vaddr[gen8_pd_index(idx, 0)] = gen8_pte_encode(addr, level, flags); - clflush_cache_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr)); + drm_clflush_virt_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr)); }
static void __xehpsdv_ppgtt_insert_entry_lm(struct i915_address_space *vm, diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index 89aef3ce53f0..d6f02dce45a0 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -2823,7 +2823,7 @@ static void execlists_sanitize(struct intel_engine_cs *engine) sanitize_hwsp(engine);
/* And scrub the dirty cachelines for the HWSP */ - clflush_cache_range(engine->status_page.addr, PAGE_SIZE); + drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE);
intel_engine_reset_pinned_contexts(engine); } diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c index c548c193cd35..fc314946d426 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.c +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c @@ -268,7 +268,7 @@ fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count) void *vaddr = __px_vaddr(p);
memset64(vaddr, val, count); - clflush_cache_range(vaddr, PAGE_SIZE); + drm_clflush_virt_range(vaddr, PAGE_SIZE); }
static void poison_scratch_page(struct drm_i915_gem_object *scratch) diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c index d91e2beb7517..d8b94d638559 100644 --- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c @@ -91,7 +91,7 @@ write_dma_entry(struct drm_i915_gem_object * const pdma, u64 * const vaddr = __px_vaddr(pdma);
vaddr[idx] = encoded_entry; - clflush_cache_range(&vaddr[idx], sizeof(u64)); + drm_clflush_virt_range(&vaddr[idx], sizeof(u64)); }
void diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index b3a429a92c0d..89020706adc4 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -3573,7 +3573,7 @@ static void guc_sanitize(struct intel_engine_cs *engine) sanitize_hwsp(engine);
/* And scrub the dirty cachelines for the HWSP */ - clflush_cache_range(engine->status_page.addr, PAGE_SIZE); + drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE);
intel_engine_reset_pinned_contexts(engine); }
dri-devel@lists.freedesktop.org
-
Alex Deucher -
Matthew Wilcox -
Michael Cheng -
Robin Murphy -
Tvrtko Ursulin