These patches try to make all current rockchip full framework vop works on drm, fill missing vop on full framework. Vop Full framework now has following vops: IP version chipname 3.1 rk3288 3.2 rk3368 3.4 rk3366 3.5 rk3399 big 3.6 rk3399 lit 3.7 rk3228 3.8 rk3328
Group the vop register, it would make register definition clearer and more easily to reuse same group register define for difference vops.
Tested on rk3399 excavator board with kernel 4.13-rc1.
And other chips tested on rockchip kernel 4.4: https://github.com/rockchip-linux/kernel/tree/release-4.4/drivers/gpu/drm/ro...
Changes in v6: - fix some patches complie error - fix rk3036 display blank
Changes in v5: - clean document commit title - move changes description out of docummit commit msg
Changes in v4: - rebase to newest torvalds kernel, fix merge conflict
Changes in v3: - group vop register instead using VOP_REG_VER mechanism - Explain more on patch commit message - move write_relaxed flags to vop registers - fix rk3328 overlay abnormal
Changes in v2: - rename rk322x to rk3228 - correct some vop registers define
Mark Yao (7): drm/rockchip: vop: initialize registers directly drm/rockchip: vop: move write_relaxed flags to vop register drm/rockchip: vop: move line_flag_num to interrupt registers drm/rockchip: vop: group vop registers drm/rockchip: vop: add a series of vop support dt-bindings: display: rockchip: fill Documents for vop series drm/rockchip: vop: rk3328: fix overlay abnormal
.../bindings/display/rockchip/rockchip-vop.txt | 4 + drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 109 ++- drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 81 +- drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 375 ++++++--- drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 905 ++++++++++++++++----- 5 files changed, 1075 insertions(+), 399 deletions(-)
At present we are using init_table to initialize some registers, but the Register init table use un-document define, it is unreadable, and sometimes we only want to update tiny bits, init table method is not friendly, it's diffcult to reuse for difference chips.
To make it clean, initialize registers directly, and drops init_table mechanism out.
Signed-off-by: Mark Yao mark.yao@rock-chips.com --- Changes in v6: - fix rk3036 blank display
Changes in v3: - Explain more in details
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 6 ++-- drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 10 ++----- drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 44 ++++------------------------- 3 files changed, 11 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 5d45033..81164d6 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -1395,7 +1395,6 @@ static void vop_destroy_crtc(struct vop *vop) static int vop_initial(struct vop *vop) { const struct vop_data *vop_data = vop->data; - const struct vop_reg_data *init_table = vop_data->init_table; struct reset_control *ahb_rst; int i, ret;
@@ -1455,13 +1454,14 @@ static int vop_initial(struct vop *vop)
memcpy(vop->regsbak, vop->regs, vop->len);
- for (i = 0; i < vop_data->table_size; i++) - vop_writel(vop, init_table[i].offset, init_table[i].value); + VOP_CTRL_SET(vop, global_regdone_en, 1); + VOP_CTRL_SET(vop, dsp_blank, 0);
for (i = 0; i < vop_data->win_size; i++) { const struct vop_win_data *win = &vop_data->win[i];
VOP_WIN_SET(vop, win, enable, 0); + VOP_WIN_SET(vop, win, gate, 1); }
vop_cfg_done(vop); diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h index 9979fd0..084d3b2 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h @@ -24,11 +24,6 @@ enum vop_data_format { VOP_FMT_YUV444SP, };
-struct vop_reg_data { - uint32_t offset; - uint32_t value; -}; - struct vop_reg { uint32_t offset; uint32_t shift; @@ -46,6 +41,7 @@ struct vop_ctrl { struct vop_reg hdmi_en; struct vop_reg mipi_en; struct vop_reg dp_en; + struct vop_reg dsp_blank; struct vop_reg out_mode; struct vop_reg dither_down; struct vop_reg dither_up; @@ -65,6 +61,7 @@ struct vop_ctrl {
struct vop_reg line_flag_num[2];
+ struct vop_reg global_regdone_en; struct vop_reg cfg_done; };
@@ -115,6 +112,7 @@ struct vop_win_phy { uint32_t nformats;
struct vop_reg enable; + struct vop_reg gate; struct vop_reg format; struct vop_reg rb_swap; struct vop_reg act_info; @@ -136,8 +134,6 @@ struct vop_win_data { };
struct vop_data { - const struct vop_reg_data *init_table; - unsigned int table_size; const struct vop_ctrl *ctrl; const struct vop_intr *intr; const struct vop_win_data *win; diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index bafd698..58da855 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -119,6 +119,7 @@ .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), + .dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24), .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), @@ -127,13 +128,7 @@ .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), };
-static const struct vop_reg_data rk3036_vop_init_reg_table[] = { - {RK3036_DSP_CTRL1, 0x00000000}, -}; - static const struct vop_data rk3036_vop = { - .init_table = rk3036_vop_init_reg_table, - .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table), .ctrl = &rk3036_ctrl_data, .intr = &rk3036_intr, .win = rk3036_vop_win_data, @@ -193,7 +188,8 @@ static const struct vop_win_phy rk3288_win23_data = { .data_formats = formats_win_lite, .nformats = ARRAY_SIZE(formats_win_lite), - .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0), + .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 4), + .gate = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0), .format = VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1), .rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12), .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO0, 0x0fff0fff, 0), @@ -215,6 +211,7 @@ .dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1), .dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6), .data_blank = VOP_REG(RK3288_DSP_CTRL0, 0x1, 19), + .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18), .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0), .pin_pol = VOP_REG(RK3288_DSP_CTRL0, 0xf, 4), .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), @@ -224,22 +221,10 @@ .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0), .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0), .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12), + .global_regdone_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 11), .cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0), };
-static const struct vop_reg_data rk3288_init_reg_table[] = { - {RK3288_SYS_CTRL, 0x00c00000}, - {RK3288_DSP_CTRL0, 0x00000000}, - {RK3288_WIN0_CTRL0, 0x00000080}, - {RK3288_WIN1_CTRL0, 0x00000080}, - /* TODO: Win2/3 support multiple area function, but we haven't found - * a suitable way to use it yet, so let's just use them as other windows - * with only area 0 enabled. - */ - {RK3288_WIN2_CTRL0, 0x00000010}, - {RK3288_WIN3_CTRL0, 0x00000010}, -}; - /* * Note: rk3288 has a dedicated 'cursor' window, however, that window requires * special support to get alpha blending working. For now, just use overlay @@ -273,8 +258,6 @@ };
static const struct vop_data rk3288_vop = { - .init_table = rk3288_init_reg_table, - .table_size = ARRAY_SIZE(rk3288_init_reg_table), .feature = VOP_FEATURE_OUTPUT_RGB10, .intr = &rk3288_vop_intr, .ctrl = &rk3288_ctrl_data, @@ -328,22 +311,7 @@ .clear = VOP_REG_MASK(RK3399_INTR_CLEAR0, 0xffff, 0), };
-static const struct vop_reg_data rk3399_init_reg_table[] = { - {RK3399_SYS_CTRL, 0x2000f800}, - {RK3399_DSP_CTRL0, 0x00000000}, - {RK3399_WIN0_CTRL0, 0x00000080}, - {RK3399_WIN1_CTRL0, 0x00000080}, - /* TODO: Win2/3 support multiple area function, but we haven't found - * a suitable way to use it yet, so let's just use them as other windows - * with only area 0 enabled. - */ - {RK3399_WIN2_CTRL0, 0x00000010}, - {RK3399_WIN3_CTRL0, 0x00000010}, -}; - static const struct vop_data rk3399_vop_big = { - .init_table = rk3399_init_reg_table, - .table_size = ARRAY_SIZE(rk3399_init_reg_table), .feature = VOP_FEATURE_OUTPUT_RGB10, .intr = &rk3399_vop_intr, .ctrl = &rk3399_ctrl_data, @@ -362,8 +330,6 @@ };
static const struct vop_data rk3399_vop_lit = { - .init_table = rk3399_init_reg_table, - .table_size = ARRAY_SIZE(rk3399_init_reg_table), .intr = &rk3399_vop_intr, .ctrl = &rk3399_ctrl_data, /*
Am Mittwoch, 26. Juli 2017, 14:19:05 CEST schrieb Mark Yao:
At present we are using init_table to initialize some registers, but the Register init table use un-document define, it is unreadable, and sometimes we only want to update tiny bits, init table method is not friendly, it's diffcult to reuse for difference chips.
To make it clean, initialize registers directly, and drops init_table mechanism out.
Signed-off-by: Mark Yao mark.yao@rock-chips.com
on rk3036 and rk3288 Tested-by: Heiko Stuebner heiko@sntech.de
Heiko
Hi mark,
On 07/26/2017 02:19 PM, Mark yao wrote:
At present we are using init_table to initialize some registers, but the Register init table use un-document define, it is unreadable, and sometimes we only want to update tiny bits, init table method is not friendly, it's diffcult to reuse for difference chips.
To make it clean, initialize registers directly, and drops init_table mechanism out.
Signed-off-by: Mark Yaomark.yao@rock-chips.com Tested-by: Heiko Stuebnerheiko@sntech.de
Reviewed-by: Jeffy Chen jeffy.chen@rock-chips.com
Since the drm atomic framework, only a small part of the vop register needs sync write, Currently seems only following registers need sync write: cfg_done, standby and interrupt related register.
All ctrl registers are using the sync write method that is inefficient, hardcode the write_relaxed flags to vop registers, then can only do synchronize write for those actual needed register.
Signed-off-by: Mark Yao mark.yao@rock-chips.com --- Changes in v6: - fix compile error
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 28 ++++++++----------- drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 1 + drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 42 ++++++++++++++++------------- 3 files changed, 36 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 81164d6..a792ea3 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -42,33 +42,27 @@ #include "rockchip_drm_psr.h" #include "rockchip_drm_vop.h"
-#define __REG_SET_RELAXED(x, off, mask, shift, v, write_mask) \ - vop_mask_write(x, off, mask, shift, v, write_mask, true) - -#define __REG_SET_NORMAL(x, off, mask, shift, v, write_mask) \ - vop_mask_write(x, off, mask, shift, v, write_mask, false) - -#define REG_SET(x, base, reg, v, mode) \ - __REG_SET_##mode(x, base + reg.offset, \ - reg.mask, reg.shift, v, reg.write_mask) -#define REG_SET_MASK(x, base, reg, mask, v, mode) \ - __REG_SET_##mode(x, base + reg.offset, \ - mask, reg.shift, v, reg.write_mask) +#define REG_SET(x, base, reg, v) \ + vop_mask_write(x, base + reg.offset, reg.mask, reg.shift, \ + v, reg.write_mask, reg.relaxed) +#define REG_SET_MASK(x, base, reg, mask, v) \ + vop_mask_write(x, base + reg.offset, \ + mask, reg.shift, v, reg.write_mask, reg.relaxed)
#define VOP_WIN_SET(x, win, name, v) \ - REG_SET(x, win->base, win->phy->name, v, RELAXED) + REG_SET(x, win->base, win->phy->name, v) #define VOP_SCL_SET(x, win, name, v) \ - REG_SET(x, win->base, win->phy->scl->name, v, RELAXED) + REG_SET(x, win->base, win->phy->scl->name, v) #define VOP_SCL_SET_EXT(x, win, name, v) \ - REG_SET(x, win->base, win->phy->scl->ext->name, v, RELAXED) + REG_SET(x, win->base, win->phy->scl->ext->name, v) #define VOP_CTRL_SET(x, name, v) \ - REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL) + REG_SET(x, 0, (x)->data->ctrl->name, v)
#define VOP_INTR_GET(vop, name) \ vop_read_reg(vop, 0, &vop->data->ctrl->name)
#define VOP_INTR_SET(vop, name, mask, v) \ - REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v, NORMAL) + REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v) #define VOP_INTR_SET_TYPE(vop, name, type, v) \ do { \ int i, reg = 0, mask = 0; \ diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h index 084d3b2..056b974 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h @@ -29,6 +29,7 @@ struct vop_reg { uint32_t shift; uint32_t mask; bool write_mask; + bool relaxed; };
struct vop_ctrl { diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index 58da855..d7974da 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -20,17 +20,23 @@ #include "rockchip_drm_vop.h" #include "rockchip_vop_reg.h"
-#define VOP_REG(off, _mask, s) \ - {.offset = off, \ +#define _VOP_REG(off, _mask, _shift, _write_mask, _relaxed) \ + { \ + .offset = off, \ .mask = _mask, \ - .shift = s, \ - .write_mask = false,} + .shift = _shift, \ + .write_mask = _write_mask, \ + .relaxed = _relaxed, \ + }
-#define VOP_REG_MASK(off, _mask, s) \ - {.offset = off, \ - .mask = _mask, \ - .shift = s, \ - .write_mask = true,} +#define VOP_REG(off, _mask, _shift) \ + _VOP_REG(off, _mask, _shift, false, true) + +#define VOP_REG_SYNC(off, _mask, _shift) \ + _VOP_REG(off, _mask, _shift, false, false) + +#define VOP_REG_MASK_SYNC(off, _mask, _shift) \ + _VOP_REG(off, _mask, _shift, true, false)
static const uint32_t formats_win_full[] = { DRM_FORMAT_XRGB8888, @@ -116,7 +122,7 @@ };
static const struct vop_ctrl rk3036_ctrl_data = { - .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), + .standby = VOP_REG_SYNC(RK3036_SYS_CTRL, 0x1, 30), .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), .dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24), @@ -125,7 +131,7 @@ .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12), - .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), + .cfg_done = VOP_REG_SYNC(RK3036_REG_CFG_DONE, 0x1, 0), };
static const struct vop_data rk3036_vop = { @@ -201,7 +207,7 @@ };
static const struct vop_ctrl rk3288_ctrl_data = { - .standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22), + .standby = VOP_REG_SYNC(RK3288_SYS_CTRL, 0x1, 22), .gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23), .mmu_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 20), .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12), @@ -222,7 +228,7 @@ .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0), .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12), .global_regdone_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 11), - .cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0), + .cfg_done = VOP_REG_SYNC(RK3288_REG_CFG_DONE, 0x1, 0), };
/* @@ -266,7 +272,7 @@ };
static const struct vop_ctrl rk3399_ctrl_data = { - .standby = VOP_REG(RK3399_SYS_CTRL, 0x1, 22), + .standby = VOP_REG_SYNC(RK3399_SYS_CTRL, 0x1, 22), .gate_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 23), .dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11), .rgb_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 12), @@ -290,7 +296,7 @@ .vpost_st_end = VOP_REG(RK3399_POST_DSP_VACT_INFO, 0x1fff1fff, 0), .line_flag_num[0] = VOP_REG(RK3399_LINE_FLAG, 0xffff, 0), .line_flag_num[1] = VOP_REG(RK3399_LINE_FLAG, 0xffff, 16), - .cfg_done = VOP_REG_MASK(RK3399_REG_CFG_DONE, 0x1, 0), + .cfg_done = VOP_REG_MASK_SYNC(RK3399_REG_CFG_DONE, 0x1, 0), };
static const int rk3399_vop_intrs[] = { @@ -306,9 +312,9 @@ static const struct vop_intr rk3399_vop_intr = { .intrs = rk3399_vop_intrs, .nintrs = ARRAY_SIZE(rk3399_vop_intrs), - .status = VOP_REG_MASK(RK3399_INTR_STATUS0, 0xffff, 0), - .enable = VOP_REG_MASK(RK3399_INTR_EN0, 0xffff, 0), - .clear = VOP_REG_MASK(RK3399_INTR_CLEAR0, 0xffff, 0), + .status = VOP_REG_MASK_SYNC(RK3399_INTR_STATUS0, 0xffff, 0), + .enable = VOP_REG_MASK_SYNC(RK3399_INTR_EN0, 0xffff, 0), + .clear = VOP_REG_MASK_SYNC(RK3399_INTR_CLEAR0, 0xffff, 0), };
static const struct vop_data rk3399_vop_big = {
Am Mittwoch, 26. Juli 2017, 14:19:12 CEST schrieb Mark Yao:
Since the drm atomic framework, only a small part of the vop register needs sync write, Currently seems only following registers need sync write: cfg_done, standby and interrupt related register.
All ctrl registers are using the sync write method that is inefficient, hardcode the write_relaxed flags to vop registers, then can only do synchronize write for those actual needed register.
Signed-off-by: Mark Yao mark.yao@rock-chips.com
on rk3036 and rk3288 Tested-by: Heiko Stuebner heiko@sntech.de
Heiko
Hi mark,
On 07/26/2017 02:19 PM, Mark yao wrote:
Since the drm atomic framework, only a small part of the vop register needs sync write, Currently seems only following registers need sync write: cfg_done, standby and interrupt related register.
All ctrl registers are using the sync write method that is inefficient, hardcode the write_relaxed flags to vop registers, then can only do synchronize write for those actual needed register.
Signed-off-by: Mark Yaomark.yao@rock-chips.com Tested-by: Heiko Stuebnerheiko@sntech.de
Reviewed-by: Jeffy Chen jeffy.chen@rock-chips.com
In the hardware design process, the design of line flags register is associated with the interrupt register, placing the line flags in the interrupt definition is more reasonable, and it would make multi-vop define easilier.
Signed-off-by: Mark Yao mark.yao@rock-chips.com Reviewed-by: Sean Paul seanpaul@chromium.org --- Changes in v6: - fixes complie error
Changes in v3: - Explain more in details, introduce why we need this patch
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 10 +++++++--- drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 4 ++-- drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 8 ++++---- 3 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index a792ea3..fd47da5 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -61,8 +61,12 @@ #define VOP_INTR_GET(vop, name) \ vop_read_reg(vop, 0, &vop->data->ctrl->name)
-#define VOP_INTR_SET(vop, name, mask, v) \ +#define VOP_INTR_SET(vop, name, v) \ + REG_SET(vop, 0, vop->data->intr->name, v) + +#define VOP_INTR_SET_MASK(vop, name, mask, v) \ REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v) + #define VOP_INTR_SET_TYPE(vop, name, type, v) \ do { \ int i, reg = 0, mask = 0; \ @@ -72,7 +76,7 @@ mask |= 1 << i; \ } \ } \ - VOP_INTR_SET(vop, name, mask, reg); \ + VOP_INTR_SET_MASK(vop, name, mask, reg); \ } while (0) #define VOP_INTR_GET_TYPE(vop, name, type) \ vop_get_intr_type(vop, &vop->data->intr->name, type) @@ -982,7 +986,7 @@ static void vop_crtc_enable(struct drm_crtc *crtc) VOP_CTRL_SET(vop, vact_st_end, val); VOP_CTRL_SET(vop, vpost_st_end, val);
- VOP_CTRL_SET(vop, line_flag_num[0], vact_end); + VOP_INTR_SET(vop, line_flag_num[0], vact_end);
clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h index 056b974..850f8e4 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h @@ -60,8 +60,6 @@ struct vop_ctrl { struct vop_reg hpost_st_end; struct vop_reg vpost_st_end;
- struct vop_reg line_flag_num[2]; - struct vop_reg global_regdone_en; struct vop_reg cfg_done; }; @@ -69,6 +67,8 @@ struct vop_ctrl { struct vop_intr { const int *intrs; uint32_t nintrs; + + struct vop_reg line_flag_num[2]; struct vop_reg enable; struct vop_reg clear; struct vop_reg status; diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index d7974da..0a5f0d2 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -116,6 +116,7 @@ static const struct vop_intr rk3036_intr = { .intrs = rk3036_vop_intrs, .nintrs = ARRAY_SIZE(rk3036_vop_intrs), + .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12), .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0), .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4), .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8), @@ -130,7 +131,6 @@ .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), - .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12), .cfg_done = VOP_REG_SYNC(RK3036_REG_CFG_DONE, 0x1, 0), };
@@ -226,7 +226,6 @@ .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0), .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0), .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0), - .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12), .global_regdone_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 11), .cfg_done = VOP_REG_SYNC(RK3288_REG_CFG_DONE, 0x1, 0), }; @@ -258,6 +257,7 @@ static const struct vop_intr rk3288_vop_intr = { .intrs = rk3288_vop_intrs, .nintrs = ARRAY_SIZE(rk3288_vop_intrs), + .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12), .status = VOP_REG(RK3288_INTR_CTRL0, 0xf, 0), .enable = VOP_REG(RK3288_INTR_CTRL0, 0xf, 4), .clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8), @@ -294,8 +294,6 @@ .vact_st_end = VOP_REG(RK3399_DSP_VACT_ST_END, 0x1fff1fff, 0), .hpost_st_end = VOP_REG(RK3399_POST_DSP_HACT_INFO, 0x1fff1fff, 0), .vpost_st_end = VOP_REG(RK3399_POST_DSP_VACT_INFO, 0x1fff1fff, 0), - .line_flag_num[0] = VOP_REG(RK3399_LINE_FLAG, 0xffff, 0), - .line_flag_num[1] = VOP_REG(RK3399_LINE_FLAG, 0xffff, 16), .cfg_done = VOP_REG_MASK_SYNC(RK3399_REG_CFG_DONE, 0x1, 0), };
@@ -312,6 +310,8 @@ static const struct vop_intr rk3399_vop_intr = { .intrs = rk3399_vop_intrs, .nintrs = ARRAY_SIZE(rk3399_vop_intrs), + .line_flag_num[0] = VOP_REG(RK3399_LINE_FLAG, 0xffff, 0), + .line_flag_num[1] = VOP_REG(RK3399_LINE_FLAG, 0xffff, 16), .status = VOP_REG_MASK_SYNC(RK3399_INTR_STATUS0, 0xffff, 0), .enable = VOP_REG_MASK_SYNC(RK3399_INTR_EN0, 0xffff, 0), .clear = VOP_REG_MASK_SYNC(RK3399_INTR_CLEAR0, 0xffff, 0),
Am Mittwoch, 26. Juli 2017, 14:19:19 CEST schrieb Mark Yao:
In the hardware design process, the design of line flags register is associated with the interrupt register, placing the line flags in the interrupt definition is more reasonable, and it would make multi-vop define easilier.
Signed-off-by: Mark Yao mark.yao@rock-chips.com Reviewed-by: Sean Paul seanpaul@chromium.org
on rk3036 and rk3288 Tested-by: Heiko Stuebner heiko@sntech.de
Heiko
Grouping the vop registers facilitates make register definition clearer, and also is useful for different vop reuse the same group register.
Signed-off-by: Mark Yao mark.yao@rock-chips.com --- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 99 ++++++++++++------------ drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 60 ++++++++------- drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 112 +++++++++++++++------------- 3 files changed, 144 insertions(+), 127 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index fd47da5..92d098b 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -42,30 +42,19 @@ #include "rockchip_drm_psr.h" #include "rockchip_drm_vop.h"
-#define REG_SET(x, base, reg, v) \ - vop_mask_write(x, base + reg.offset, reg.mask, reg.shift, \ - v, reg.write_mask, reg.relaxed) -#define REG_SET_MASK(x, base, reg, mask, v) \ - vop_mask_write(x, base + reg.offset, \ - mask, reg.shift, v, reg.write_mask, reg.relaxed) - #define VOP_WIN_SET(x, win, name, v) \ - REG_SET(x, win->base, win->phy->name, v) + vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name) #define VOP_SCL_SET(x, win, name, v) \ - REG_SET(x, win->base, win->phy->scl->name, v) + vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name) #define VOP_SCL_SET_EXT(x, win, name, v) \ - REG_SET(x, win->base, win->phy->scl->ext->name, v) -#define VOP_CTRL_SET(x, name, v) \ - REG_SET(x, 0, (x)->data->ctrl->name, v) - -#define VOP_INTR_GET(vop, name) \ - vop_read_reg(vop, 0, &vop->data->ctrl->name) - -#define VOP_INTR_SET(vop, name, v) \ - REG_SET(vop, 0, vop->data->intr->name, v) + vop_reg_set(vop, &win->phy->scl->ext->name, \ + win->base, ~0, v, #name)
#define VOP_INTR_SET_MASK(vop, name, mask, v) \ - REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v) + vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name) + +#define VOP_REG_SET(vop, group, name, v) \ + vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name)
#define VOP_INTR_SET_TYPE(vop, name, type, v) \ do { \ @@ -82,7 +71,7 @@ vop_get_intr_type(vop, &vop->data->intr->name, type)
#define VOP_WIN_GET(x, win, name) \ - vop_read_reg(x, win->base, &win->phy->name) + vop_read_reg(x, win->offset, win->phy->name)
#define VOP_WIN_GET_YRGBADDR(vop, win) \ vop_readl(vop, win->base + win->phy->yrgb_mst.offset) @@ -164,14 +153,20 @@ static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; }
-static inline void vop_mask_write(struct vop *vop, uint32_t offset, - uint32_t mask, uint32_t shift, uint32_t v, - bool write_mask, bool relaxed) +static void vop_reg_set(struct vop *vop, const struct vop_reg *reg, + uint32_t _offset, uint32_t _mask, uint32_t v, + const char *reg_name) { - if (!mask) + int offset = reg->offset + _offset; + int mask = reg->mask & _mask; + int shift = reg->shift; + + if (!reg || !reg->mask) { + dev_dbg(vop->dev, "Warning: not support %s\n", reg_name); return; + }
- if (write_mask) { + if (reg->write_mask) { v = ((v << shift) & 0xffff) | (mask << (shift + 16)); } else { uint32_t cached_val = vop->regsbak[offset >> 2]; @@ -180,7 +175,7 @@ static inline void vop_mask_write(struct vop *vop, uint32_t offset, vop->regsbak[offset >> 2] = v; }
- if (relaxed) + if (reg->relaxed) writel_relaxed(v, vop->regs + offset); else writel(v, vop->regs + offset); @@ -202,7 +197,7 @@ static inline uint32_t vop_get_intr_type(struct vop *vop,
static inline void vop_cfg_done(struct vop *vop) { - VOP_CTRL_SET(vop, cfg_done, 1); + VOP_REG_SET(vop, common, cfg_done, 1); }
static bool has_rb_swapped(uint32_t format) @@ -540,7 +535,7 @@ static int vop_enable(struct drm_crtc *crtc)
spin_lock(&vop->reg_lock);
- VOP_CTRL_SET(vop, standby, 0); + VOP_REG_SET(vop, common, standby, 1);
spin_unlock(&vop->reg_lock);
@@ -600,7 +595,7 @@ static void vop_crtc_disable(struct drm_crtc *crtc)
spin_lock(&vop->reg_lock);
- VOP_CTRL_SET(vop, standby, 1); + VOP_REG_SET(vop, common, standby, 1);
spin_unlock(&vop->reg_lock);
@@ -923,7 +918,7 @@ static void vop_crtc_enable(struct drm_crtc *crtc)
spin_lock(&vop->reg_lock);
- VOP_CTRL_SET(vop, standby, 1); + VOP_REG_SET(vop, common, standby, 1);
spin_unlock(&vop->reg_lock);
@@ -937,29 +932,29 @@ static void vop_crtc_enable(struct drm_crtc *crtc) BIT(HSYNC_POSITIVE) : 0; pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ? BIT(VSYNC_POSITIVE) : 0; - VOP_CTRL_SET(vop, pin_pol, pin_pol); + VOP_REG_SET(vop, output, pin_pol, pin_pol);
switch (s->output_type) { case DRM_MODE_CONNECTOR_LVDS: - VOP_CTRL_SET(vop, rgb_en, 1); - VOP_CTRL_SET(vop, rgb_pin_pol, pin_pol); + VOP_REG_SET(vop, output, rgb_en, 1); + VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol); break; case DRM_MODE_CONNECTOR_eDP: - VOP_CTRL_SET(vop, edp_pin_pol, pin_pol); - VOP_CTRL_SET(vop, edp_en, 1); + VOP_REG_SET(vop, output, edp_pin_pol, pin_pol); + VOP_REG_SET(vop, output, edp_en, 1); break; case DRM_MODE_CONNECTOR_HDMIA: - VOP_CTRL_SET(vop, hdmi_pin_pol, pin_pol); - VOP_CTRL_SET(vop, hdmi_en, 1); + VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol); + VOP_REG_SET(vop, output, hdmi_en, 1); break; case DRM_MODE_CONNECTOR_DSI: - VOP_CTRL_SET(vop, mipi_pin_pol, pin_pol); - VOP_CTRL_SET(vop, mipi_en, 1); + VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol); + VOP_REG_SET(vop, output, mipi_en, 1); break; case DRM_MODE_CONNECTOR_DisplayPort: pin_pol &= ~BIT(DCLK_INVERT); - VOP_CTRL_SET(vop, dp_pin_pol, pin_pol); - VOP_CTRL_SET(vop, dp_en, 1); + VOP_REG_SET(vop, output, dp_pin_pol, pin_pol); + VOP_REG_SET(vop, output, dp_en, 1); break; default: DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n", @@ -972,25 +967,25 @@ static void vop_crtc_enable(struct drm_crtc *crtc) if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) s->output_mode = ROCKCHIP_OUT_MODE_P888; - VOP_CTRL_SET(vop, out_mode, s->output_mode); + VOP_REG_SET(vop, common, out_mode, s->output_mode);
- VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len); + VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len); val = hact_st << 16; val |= hact_end; - VOP_CTRL_SET(vop, hact_st_end, val); - VOP_CTRL_SET(vop, hpost_st_end, val); + VOP_REG_SET(vop, modeset, hact_st_end, val); + VOP_REG_SET(vop, modeset, hpost_st_end, val);
- VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len); + VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len); val = vact_st << 16; val |= vact_end; - VOP_CTRL_SET(vop, vact_st_end, val); - VOP_CTRL_SET(vop, vpost_st_end, val); + VOP_REG_SET(vop, modeset, vact_st_end, val); + VOP_REG_SET(vop, modeset, vpost_st_end, val);
- VOP_INTR_SET(vop, line_flag_num[0], vact_end); + VOP_REG_SET(vop, intr, line_flag_num[0], vact_end);
clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
- VOP_CTRL_SET(vop, standby, 0); + VOP_REG_SET(vop, common, standby, 0);
rockchip_drm_psr_activate(&vop->crtc); } @@ -1452,8 +1447,8 @@ static int vop_initial(struct vop *vop)
memcpy(vop->regsbak, vop->regs, vop->len);
- VOP_CTRL_SET(vop, global_regdone_en, 1); - VOP_CTRL_SET(vop, dsp_blank, 0); + VOP_REG_SET(vop, misc, global_regdone_en, 1); + VOP_REG_SET(vop, common, dsp_blank, 0);
for (i = 0; i < vop_data->win_size; i++) { const struct vop_win_data *win = &vop_data->win[i]; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h index 850f8e4..3ba962c 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h @@ -25,43 +25,50 @@ enum vop_data_format { };
struct vop_reg { - uint32_t offset; - uint32_t shift; uint32_t mask; + uint16_t offset; + uint8_t shift; bool write_mask; bool relaxed; };
-struct vop_ctrl { - struct vop_reg standby; - struct vop_reg data_blank; - struct vop_reg gate_en; - struct vop_reg mmu_en; - struct vop_reg rgb_en; +struct vop_modeset { + struct vop_reg htotal_pw; + struct vop_reg hact_st_end; + struct vop_reg hpost_st_end; + struct vop_reg vtotal_pw; + struct vop_reg vact_st_end; + struct vop_reg vpost_st_end; +}; + +struct vop_output { + struct vop_reg pin_pol; + struct vop_reg dp_pin_pol; + struct vop_reg edp_pin_pol; + struct vop_reg hdmi_pin_pol; + struct vop_reg mipi_pin_pol; + struct vop_reg rgb_pin_pol; + struct vop_reg dp_en; struct vop_reg edp_en; struct vop_reg hdmi_en; struct vop_reg mipi_en; - struct vop_reg dp_en; + struct vop_reg rgb_en; +}; + +struct vop_common { + struct vop_reg cfg_done; struct vop_reg dsp_blank; - struct vop_reg out_mode; + struct vop_reg data_blank; struct vop_reg dither_down; struct vop_reg dither_up; - struct vop_reg pin_pol; - struct vop_reg rgb_pin_pol; - struct vop_reg hdmi_pin_pol; - struct vop_reg edp_pin_pol; - struct vop_reg mipi_pin_pol; - struct vop_reg dp_pin_pol; - - struct vop_reg htotal_pw; - struct vop_reg hact_st_end; - struct vop_reg vtotal_pw; - struct vop_reg vact_st_end; - struct vop_reg hpost_st_end; - struct vop_reg vpost_st_end; + struct vop_reg gate_en; + struct vop_reg mmu_en; + struct vop_reg out_mode; + struct vop_reg standby; +};
+struct vop_misc { struct vop_reg global_regdone_en; - struct vop_reg cfg_done; };
struct vop_intr { @@ -135,8 +142,11 @@ struct vop_win_data { };
struct vop_data { - const struct vop_ctrl *ctrl; const struct vop_intr *intr; + const struct vop_common *common; + const struct vop_misc *misc; + const struct vop_modeset *modeset; + const struct vop_output *output; const struct vop_win_data *win; unsigned int win_size;
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index 0a5f0d2..20607a8 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -117,26 +117,34 @@ .intrs = rk3036_vop_intrs, .nintrs = ARRAY_SIZE(rk3036_vop_intrs), .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12), - .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0), - .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4), - .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8), + .status = VOP_REG_SYNC(RK3036_INT_STATUS, 0xf, 0), + .enable = VOP_REG_SYNC(RK3036_INT_STATUS, 0xf, 4), + .clear = VOP_REG_SYNC(RK3036_INT_STATUS, 0xf, 8), };
-static const struct vop_ctrl rk3036_ctrl_data = { - .standby = VOP_REG_SYNC(RK3036_SYS_CTRL, 0x1, 30), - .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), - .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), - .dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24), +static const struct vop_modeset rk3036_modeset = { .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), +}; + +static const struct vop_output rk3036_output = { + .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), +}; + +static const struct vop_common rk3036_common = { + .standby = VOP_REG_SYNC(RK3036_SYS_CTRL, 0x1, 30), + .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), + .dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24), .cfg_done = VOP_REG_SYNC(RK3036_REG_CFG_DONE, 0x1, 0), };
static const struct vop_data rk3036_vop = { - .ctrl = &rk3036_ctrl_data, .intr = &rk3036_intr, + .common = &rk3036_common, + .modeset = &rk3036_modeset, + .output = &rk3036_output, .win = rk3036_vop_win_data, .win_size = ARRAY_SIZE(rk3036_vop_win_data), }; @@ -206,27 +214,32 @@ .dst_alpha_ctl = VOP_REG(RK3288_WIN2_DST_ALPHA_CTRL, 0xff, 0), };
-static const struct vop_ctrl rk3288_ctrl_data = { - .standby = VOP_REG_SYNC(RK3288_SYS_CTRL, 0x1, 22), - .gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23), - .mmu_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 20), +static const struct vop_modeset rk3288_modeset = { + .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), + .hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0), + .vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), + .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0), + .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0), + .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0), +}; + +static const struct vop_output rk3288_output = { + .pin_pol = VOP_REG(RK3288_DSP_CTRL0, 0xf, 4), .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12), .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13), .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14), .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15), +}; + +static const struct vop_common rk3288_common = { + .standby = VOP_REG_SYNC(RK3288_SYS_CTRL, 0x1, 22), + .gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23), + .mmu_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 20), .dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1), .dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6), .data_blank = VOP_REG(RK3288_DSP_CTRL0, 0x1, 19), .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18), .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0), - .pin_pol = VOP_REG(RK3288_DSP_CTRL0, 0xf, 4), - .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), - .hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0), - .vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), - .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0), - .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0), - .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0), - .global_regdone_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 11), .cfg_done = VOP_REG_SYNC(RK3288_REG_CFG_DONE, 0x1, 0), };
@@ -266,37 +279,13 @@ static const struct vop_data rk3288_vop = { .feature = VOP_FEATURE_OUTPUT_RGB10, .intr = &rk3288_vop_intr, - .ctrl = &rk3288_ctrl_data, + .common = &rk3288_common, + .modeset = &rk3288_modeset, + .output = &rk3288_output, .win = rk3288_vop_win_data, .win_size = ARRAY_SIZE(rk3288_vop_win_data), };
-static const struct vop_ctrl rk3399_ctrl_data = { - .standby = VOP_REG_SYNC(RK3399_SYS_CTRL, 0x1, 22), - .gate_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 23), - .dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11), - .rgb_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 12), - .hdmi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 13), - .edp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 14), - .mipi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 15), - .dither_down = VOP_REG(RK3399_DSP_CTRL1, 0xf, 1), - .dither_up = VOP_REG(RK3399_DSP_CTRL1, 0x1, 6), - .data_blank = VOP_REG(RK3399_DSP_CTRL0, 0x1, 19), - .out_mode = VOP_REG(RK3399_DSP_CTRL0, 0xf, 0), - .rgb_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 16), - .dp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 16), - .hdmi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 20), - .edp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 24), - .mipi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 28), - .htotal_pw = VOP_REG(RK3399_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), - .hact_st_end = VOP_REG(RK3399_DSP_HACT_ST_END, 0x1fff1fff, 0), - .vtotal_pw = VOP_REG(RK3399_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), - .vact_st_end = VOP_REG(RK3399_DSP_VACT_ST_END, 0x1fff1fff, 0), - .hpost_st_end = VOP_REG(RK3399_POST_DSP_HACT_INFO, 0x1fff1fff, 0), - .vpost_st_end = VOP_REG(RK3399_POST_DSP_VACT_INFO, 0x1fff1fff, 0), - .cfg_done = VOP_REG_MASK_SYNC(RK3399_REG_CFG_DONE, 0x1, 0), -}; - static const int rk3399_vop_intrs[] = { FS_INTR, 0, 0, @@ -317,10 +306,30 @@ .clear = VOP_REG_MASK_SYNC(RK3399_INTR_CLEAR0, 0xffff, 0), };
+static const struct vop_output rk3399_output = { + .dp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 16), + .rgb_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 16), + .hdmi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 20), + .edp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 24), + .mipi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 28), + .dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11), + .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12), + .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13), + .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14), + .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15), +}; + +static const struct vop_misc rk3399_misc = { + .global_regdone_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11), +}; + static const struct vop_data rk3399_vop_big = { .feature = VOP_FEATURE_OUTPUT_RGB10, .intr = &rk3399_vop_intr, - .ctrl = &rk3399_ctrl_data, + .common = &rk3288_common, + .modeset = &rk3288_modeset, + .output = &rk3399_output, + .misc = &rk3399_misc, /* * rk3399 vop big windows register layout is same as rk3288. */ @@ -337,7 +346,10 @@
static const struct vop_data rk3399_vop_lit = { .intr = &rk3399_vop_intr, - .ctrl = &rk3399_ctrl_data, + .common = &rk3288_common, + .modeset = &rk3288_modeset, + .output = &rk3399_output, + .misc = &rk3399_misc, /* * rk3399 vop lit windows register layout is same as rk3288, * but cut off the win1 and win3 windows.
Hi mark,
On 07/26/2017 02:19 PM, Mark yao wrote:
Grouping the vop registers facilitates make register definition clearer, and also is useful for different vop reuse the same group register.
Signed-off-by: Mark Yaomark.yao@rock-chips.com
Reviewed-by: Jeffy Chen jeffy.chen@rock-chips.com
Hi Mark,
Am Mittwoch, 26. Juli 2017, 14:19:25 CEST schrieb Mark Yao:
Grouping the vop registers facilitates make register definition clearer, and also is useful for different vop reuse the same group register.
Signed-off-by: Mark Yao mark.yao@rock-chips.com
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 99 ++++++++++++------------ drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 60 ++++++++------- drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 112 +++++++++++++++------------- 3 files changed, 144 insertions(+), 127 deletions(-)
This breaks display support on both rk3036 and rk3288 and I end up with a null pointer dereference in
[ 10.640297] Unable to handle kernel NULL pointer dereference at virtual address 00000000 [ 10.654430] pgd = c0204000 [ 10.657452] [00000000] *pgd=00000000 [ 10.661473] Internal error: Oops: 5 [#1] SMP ARM [ 10.666635] Modules linked in: snd_pcm media snd_timer phy_rockchip_dp snd soundcore rockchipdrm dw_hdmi analogix_dp rtc_rk808 pwm_rockchip clk_rk808 spi_rockchip [ 10.682897] CPU: 2 PID: 143 Comm: kworker/2:2 Not tainted 4.13.0-rc2-01791-g2b86603d0515 #355 [ 10.692430] Hardware name: Rockchip (Device Tree) [ 10.697692] Workqueue: events deferred_probe_work_func [ 10.702152] Linux video capture interface: v2.00 [ 10.708590] task: ee38c800 task.stack: ed2e6000 [ 10.713656] PC is at vop_reg_set.constprop.4+0x4/0xa8 [rockchipdrm] [ 10.720668] LR is at vop_bind+0x568/0x8a0 [rockchipdrm] [ 10.726507] pc : [<bf04db28>] lr : [<bf04e134>] psr: 40010013 [ 10.733514] sp : ed2e7d68 ip : 00000004 fp : bf054988 [ 10.739350] r10: bf054988 r9 : 00000000 r8 : 00000001 [ 10.745189] r7 : ed66f500 r6 : ee29da10 r5 : 00000000 r4 : ed22e010 [ 10.752487] r3 : ffffffff r2 : 00000000 r1 : 00000000 r0 : ed22e010 [ 10.759785] Flags: nZcv IRQs on FIQs on Mode SVC_32 ISA ARM Segment none [ 10.767763] Control: 10c5387d Table: 2d4e806a DAC: 00000051 [ 10.774188] Process kworker/2:2 (pid: 143, stack limit = 0xed2e6220) [...] [ 11.058818] [<bf04db28>] (vop_reg_set.constprop.4 [rockchipdrm]) from [<bf04e134>] (vop_bind+0x568/0x8a0 [rockchipdrm]) [ 11.058828] [<bf04e134>] (vop_bind [rockchipdrm]) from [<c0870400>] (component_bind_all+0x11c/0x23c) [ 11.058836] [<c0870400>] (component_bind_all) from [<bf04c1cc>] (rockchip_drm_bind+0x90/0x1d4 [rockchipdrm]) [ 11.058843] [<bf04c1cc>] (rockchip_drm_bind [rockchipdrm]) from [<c0870854>] (try_to_bring_up_master+0x148/0x184) [ 11.058847] [<c0870854>] (try_to_bring_up_master) from [<c0870928>] (component_add+0x98/0x144) [ 11.058853] [<c0870928>] (component_add) from [<bf050d90>] (rockchip_dp_probe+0x7c/0x8c [rockchipdrm]) [ 11.058860] [<bf050d90>] (rockchip_dp_probe [rockchipdrm]) from [<c0877660>] (platform_drv_probe+0x50/0xb0) [ 11.058865] [<c0877660>] (platform_drv_probe) from [<c0875b48>] (driver_probe_device+0x230/0x2e4) [ 11.058869] [<c0875b48>] (driver_probe_device) from [<c0874208>] (bus_for_each_drv+0x60/0x94) [ 11.058873] [<c0874208>] (bus_for_each_drv) from [<c0875838>] (__device_attach+0xb0/0x114) [ 11.058876] [<c0875838>] (__device_attach) from [<c0874ec8>] (bus_probe_device+0x84/0x8c) [ 11.058879] [<c0874ec8>] (bus_probe_device) from [<c087534c>] (deferred_probe_work_func+0x68/0x94) [ 11.058884] [<c087534c>] (deferred_probe_work_func) from [<c035a884>] (process_one_work+0x200/0x504) [ 11.058889] [<c035a884>] (process_one_work) from [<c035b610>] (worker_thread+0x38/0x594) [ 11.058894] [<c035b610>] (worker_thread) from [<c036045c>] (kthread+0x128/0x158) [ 11.058900] [<c036045c>] (kthread) from [<c0307d18>] (ret_from_fork+0x14/0x3c) [ 11.058904] Code: eaffffe0 e3a03004 eaffffef e92d4070 (e5914000) [ 11.058930] ---[ end trace 9caa88bbcb1af5e4 ]---
I'll try to investigate a bit more, but maybe you'll be able to find the issue faster than me in the meantime.
Heiko
Am Donnerstag, 27. Juli 2017, 11:51:06 CEST schrieb Heiko Stübner:
Hi Mark,
Am Mittwoch, 26. Juli 2017, 14:19:25 CEST schrieb Mark Yao:
Grouping the vop registers facilitates make register definition clearer, and also is useful for different vop reuse the same group register.
Signed-off-by: Mark Yao mark.yao@rock-chips.com
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 99 ++++++++++++------------ drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 60 ++++++++------- drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 112
+++++++++++++++------------- 3 files changed, 144 insertions(+), 127 deletions(-)
This breaks display support on both rk3036 and rk3288 and I end up with a null pointer dereference in
[ 10.640297] Unable to handle kernel NULL pointer dereference at virtual address 00000000 [ 10.654430] pgd = c0204000 [ 10.657452] [00000000] *pgd=00000000 [ 10.661473] Internal error: Oops: 5 [#1] SMP ARM [ 10.666635] Modules linked in: snd_pcm media snd_timer phy_rockchip_dp snd soundcore rockchipdrm dw_hdmi analogix_dp rtc_rk808 pwm_rockchip clk_rk808 spi_rockchip [ 10.682897] CPU: 2 PID: 143 Comm: kworker/2:2 Not tainted 4.13.0-rc2-01791-g2b86603d0515 #355 [ 10.692430] Hardware name: Rockchip (Device Tree) [ 10.697692] Workqueue: events deferred_probe_work_func [ 10.702152] Linux video capture interface: v2.00 [ 10.708590] task: ee38c800 task.stack: ed2e6000 [ 10.713656] PC is at vop_reg_set.constprop.4+0x4/0xa8 [rockchipdrm] [ 10.720668] LR is at vop_bind+0x568/0x8a0 [rockchipdrm]
The obvious reason for that is
@@ -164,14 +153,20 @@ static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; }
-static inline void vop_mask_write(struct vop *vop, uint32_t offset,
uint32_t mask, uint32_t shift, uint32_t v,bool write_mask, bool relaxed)+static void vop_reg_set(struct vop *vop, const struct vop_reg *reg,
uint32_t _offset, uint32_t _mask, uint32_t v,const char *reg_name){
- if (!mask)
- int offset = reg->offset + _offset;
- int mask = reg->mask & _mask;
- int shift = reg->shift;
- if (!reg || !reg->mask) {
dev_dbg(vop->dev, "Warning: not support %s\n", reg_name);- }
where the check for !reg happens after it got already dereferenced. But even with that fixed I end up with
on rk3288: [ 7.254823] rockchip-vop ff930000.vop: Warning: not support global_regdone_en [ 7.262847] rockchip-vop ff930000.vop: Warning: not support gate [ 7.269580] rockchip-vop ff930000.vop: Warning: not support gate [ 7.302765] rockchip-vop ff940000.vop: Warning: not support global_regdone_en [ 7.310758] rockchip-vop ff940000.vop: Warning: not support gate [ 7.317475] rockchip-vop ff940000.vop: Warning: not support gate [ 7.425724] rockchip-vop ff930000.vop: Warning: not support edp_pin_pol [ 7.526298] rockchip-vop ff940000.vop: Warning: not support hdmi_pin_pol
on rk3036: [ 12.389138] rockchip-vop 10118000.vop: Warning: not support global_regdone_en [ 12.397324] rockchip-vop 10118000.vop: Warning: not support gate [ 12.404165] rockchip-vop 10118000.vop: Warning: not support gate [ 13.747361] rockchip-vop 10118000.vop: Warning: not support hdmi_pin_pol [ 13.747371] rockchip-vop 10118000.vop: Warning: not support hdmi_en [ 13.747379] rockchip-vop 10118000.vop: Warning: not support hpost_st_end [ 13.747385] rockchip-vop 10118000.vop: Warning: not support vpost_st_end [ 13.747461] rockchip-vop 10118000.vop: Warning: not support src_alpha_ctl [ 13.767098] rockchip-vop 10118000.vop: Warning: not support src_alpha_ctl [ 13.786060] rockchip-vop 10118000.vop: Warning: not support src_alpha_ctl
While reqdone and friends are obviously features of newer vops, at least the hdmi pin-pol is available on both these socs.
With this patch applied (and null-ptr fixed) I end up without hdmi output on both socs.
Heiko
Hi Heiko
Thanks for the test.
On 2017年07月27日 18:10, Heiko Stübner wrote:
Am Donnerstag, 27. Juli 2017, 11:51:06 CEST schrieb Heiko Stübner:
Hi Mark,
Am Mittwoch, 26. Juli 2017, 14:19:25 CEST schrieb Mark Yao:
Grouping the vop registers facilitates make register definition clearer, and also is useful for different vop reuse the same group register.
Signed-off-by: Mark Yao mark.yao@rock-chips.com
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 99 ++++++++++++------------ drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 60 ++++++++------- drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 112
+++++++++++++++------------- 3 files changed, 144 insertions(+), 127 deletions(-)
This breaks display support on both rk3036 and rk3288 and I end up with a null pointer dereference in
[ 10.640297] Unable to handle kernel NULL pointer dereference at virtual address 00000000 [ 10.654430] pgd = c0204000 [ 10.657452] [00000000] *pgd=00000000 [ 10.661473] Internal error: Oops: 5 [#1] SMP ARM [ 10.666635] Modules linked in: snd_pcm media snd_timer phy_rockchip_dp snd soundcore rockchipdrm dw_hdmi analogix_dp rtc_rk808 pwm_rockchip clk_rk808 spi_rockchip [ 10.682897] CPU: 2 PID: 143 Comm: kworker/2:2 Not tainted 4.13.0-rc2-01791-g2b86603d0515 #355 [ 10.692430] Hardware name: Rockchip (Device Tree) [ 10.697692] Workqueue: events deferred_probe_work_func [ 10.702152] Linux video capture interface: v2.00 [ 10.708590] task: ee38c800 task.stack: ed2e6000 [ 10.713656] PC is at vop_reg_set.constprop.4+0x4/0xa8 [rockchipdrm] [ 10.720668] LR is at vop_bind+0x568/0x8a0 [rockchipdrm]
The obvious reason for that is
@@ -164,14 +153,20 @@ static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; }
-static inline void vop_mask_write(struct vop *vop, uint32_t offset,
uint32_t mask, uint32_t shift, uint32_t v,bool write_mask, bool relaxed)+static void vop_reg_set(struct vop *vop, const struct vop_reg *reg,
uint32_t _offset, uint32_t _mask, uint32_t v,const char *reg_name)
- if (!mask)
- int offset = reg->offset + _offset;
- int mask = reg->mask & _mask;
- int shift = reg->shift;
Does the crash is that using reg->offset/mask/shift before !reg checking?
- if (!reg || !reg->mask) {
dev_dbg(vop->dev, "Warning: not support %s\n", reg_name);- }
where the check for !reg happens after it got already dereferenced. But even with that fixed I end up with
on rk3288: [ 7.254823] rockchip-vop ff930000.vop: Warning: not support global_regdone_en [ 7.262847] rockchip-vop ff930000.vop: Warning: not support gate [ 7.269580] rockchip-vop ff930000.vop: Warning: not support gate [ 7.302765] rockchip-vop ff940000.vop: Warning: not support global_regdone_en [ 7.310758] rockchip-vop ff940000.vop: Warning: not support gate [ 7.317475] rockchip-vop ff940000.vop: Warning: not support gate [ 7.425724] rockchip-vop ff930000.vop: Warning: not support edp_pin_pol [ 7.526298] rockchip-vop ff940000.vop: Warning: not support hdmi_pin_pol
Rk3288 does not support independent pin_pol settings, all output interfaces share the pin_pol register, So not support hdmi_pin_pol here is correct.
hdmi pin pol would be set by following register: .pin_pol = VOP_REG(RK3288_DSP_CTRL0, 0xf, 4),
on rk3036: [ 12.389138] rockchip-vop 10118000.vop: Warning: not support global_regdone_en [ 12.397324] rockchip-vop 10118000.vop: Warning: not support gate [ 12.404165] rockchip-vop 10118000.vop: Warning: not support gate [ 13.747361] rockchip-vop 10118000.vop: Warning: not support hdmi_pin_pol [ 13.747371] rockchip-vop 10118000.vop: Warning: not support hdmi_en [ 13.747379] rockchip-vop 10118000.vop: Warning: not support hpost_st_end [ 13.747385] rockchip-vop 10118000.vop: Warning: not support vpost_st_end [ 13.747461] rockchip-vop 10118000.vop: Warning: not support src_alpha_ctl [ 13.767098] rockchip-vop 10118000.vop: Warning: not support src_alpha_ctl [ 13.786060] rockchip-vop 10118000.vop: Warning: not support src_alpha_ctl
While reqdone and friends are obviously features of newer vops, at least the hdmi pin-pol is available on both these socs.
With this patch applied (and null-ptr fixed) I end up without hdmi output on both socs.
Hmmm, I am confused, from code review, I didn't see what will cause hdmi not work on rk3036 and rk3288,
Give me some time, I try to bringup my popmetal rk3288 board to do the test.
Heiko, Thanks very much for your test.
Heiko
Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip
Hi Heiko
On 2017年07月28日 09:02, Mark yao wrote:
Hi Heiko
Thanks for the test.
On 2017年07月27日 18:10, Heiko Stübner wrote:
Am Donnerstag, 27. Juli 2017, 11:51:06 CEST schrieb Heiko Stübner:
Hi Mark,
Am Mittwoch, 26. Juli 2017, 14:19:25 CEST schrieb Mark Yao:
Grouping the vop registers facilitates make register definition clearer, and also is useful for different vop reuse the same group register.
Signed-off-by: Mark Yao mark.yao@rock-chips.com
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 99 ++++++++++++------------ drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 60 ++++++++------- drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 112
+++++++++++++++------------- 3 files changed, 144 insertions(+), 127 deletions(-)
This breaks display support on both rk3036 and rk3288 and I end up with a null pointer dereference in
[ 10.640297] Unable to handle kernel NULL pointer dereference at virtual address 00000000 [ 10.654430] pgd = c0204000 [ 10.657452] [00000000] *pgd=00000000 [ 10.661473] Internal error: Oops: 5 [#1] SMP ARM [ 10.666635] Modules linked in: snd_pcm media snd_timer phy_rockchip_dp snd soundcore rockchipdrm dw_hdmi analogix_dp rtc_rk808 pwm_rockchip clk_rk808 spi_rockchip [ 10.682897] CPU: 2 PID: 143 Comm: kworker/2:2 Not tainted 4.13.0-rc2-01791-g2b86603d0515 #355 [ 10.692430] Hardware name: Rockchip (Device Tree) [ 10.697692] Workqueue: events deferred_probe_work_func [ 10.702152] Linux video capture interface: v2.00 [ 10.708590] task: ee38c800 task.stack: ed2e6000 [ 10.713656] PC is at vop_reg_set.constprop.4+0x4/0xa8 [rockchipdrm] [ 10.720668] LR is at vop_bind+0x568/0x8a0 [rockchipdrm]
The obvious reason for that is
@@ -164,14 +153,20 @@ static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; }
-static inline void vop_mask_write(struct vop *vop, uint32_t offset,
uint32_t mask, uint32_t shift, uint32_t v,bool write_mask, bool relaxed)+static void vop_reg_set(struct vop *vop, const struct vop_reg *reg,
uint32_t _offset, uint32_t _mask, uint32_t v,const char *reg_name)
- if (!mask)
- int offset = reg->offset + _offset;
- int mask = reg->mask & _mask;
- int shift = reg->shift;
Does the crash is that using reg->offset/mask/shift before !reg checking?
I reproduce this cause, from objdump, it crash on "int mask = reg->mask & _mask; " Seems difference gcc has difference behavior, my aarch64 gcc maybe optimize it, only access when the value be used. I think that is the reason why rk3399 works on my test.
I will fix it at next version.
- if (!reg || !reg->mask) {
dev_dbg(vop->dev, "Warning: not support %s\n", reg_name); return;- }
where the check for !reg happens after it got already dereferenced. But even with that fixed I end up with
on rk3288: [ 7.254823] rockchip-vop ff930000.vop: Warning: not support global_regdone_en [ 7.262847] rockchip-vop ff930000.vop: Warning: not support gate [ 7.269580] rockchip-vop ff930000.vop: Warning: not support gate [ 7.302765] rockchip-vop ff940000.vop: Warning: not support global_regdone_en [ 7.310758] rockchip-vop ff940000.vop: Warning: not support gate [ 7.317475] rockchip-vop ff940000.vop: Warning: not support gate [ 7.425724] rockchip-vop ff930000.vop: Warning: not support edp_pin_pol [ 7.526298] rockchip-vop ff940000.vop: Warning: not support hdmi_pin_pol
Rk3288 does not support independent pin_pol settings, all output interfaces share the pin_pol register, So not support hdmi_pin_pol here is correct.
hdmi pin pol would be set by following register: .pin_pol = VOP_REG(RK3288_DSP_CTRL0, 0xf, 4),
on rk3036: [ 12.389138] rockchip-vop 10118000.vop: Warning: not support global_regdone_en [ 12.397324] rockchip-vop 10118000.vop: Warning: not support gate [ 12.404165] rockchip-vop 10118000.vop: Warning: not support gate [ 13.747361] rockchip-vop 10118000.vop: Warning: not support hdmi_pin_pol [ 13.747371] rockchip-vop 10118000.vop: Warning: not support hdmi_en [ 13.747379] rockchip-vop 10118000.vop: Warning: not support hpost_st_end [ 13.747385] rockchip-vop 10118000.vop: Warning: not support vpost_st_end [ 13.747461] rockchip-vop 10118000.vop: Warning: not support src_alpha_ctl [ 13.767098] rockchip-vop 10118000.vop: Warning: not support src_alpha_ctl [ 13.786060] rockchip-vop 10118000.vop: Warning: not support src_alpha_ctl
While reqdone and friends are obviously features of newer vops, at least the hdmi pin-pol is available on both these socs.
With this patch applied (and null-ptr fixed) I end up without hdmi output on both socs.
Hmmm, I am confused, from code review, I didn't see what will cause hdmi not work on rk3036 and rk3288,
Give me some time, I try to bringup my popmetal rk3288 board to do the test.
Heiko, Thanks very much for your test.
Hi Heiko
After fix null pointer problem, On rk3288 popmetal board, hdmi works good on my test, Can you double check it?
Thanks.
Heiko
Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip
Grouping the vop registers facilitates make register definition clearer, and also is useful for different vop reuse the same group register.
Signed-off-by: Mark Yao mark.yao@rock-chips.com Reviewed-by: Jeffy Chen jeffy.chen@rock-chips.com --- Changes in v6.1 - fix Null pointer crash on vop_reg_set
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 101 ++++++++++++------------- drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 60 ++++++++------- drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 112 +++++++++++++++------------- 3 files changed, 146 insertions(+), 127 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index fd47da5..39912f2 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -42,30 +42,19 @@ #include "rockchip_drm_psr.h" #include "rockchip_drm_vop.h"
-#define REG_SET(x, base, reg, v) \ - vop_mask_write(x, base + reg.offset, reg.mask, reg.shift, \ - v, reg.write_mask, reg.relaxed) -#define REG_SET_MASK(x, base, reg, mask, v) \ - vop_mask_write(x, base + reg.offset, \ - mask, reg.shift, v, reg.write_mask, reg.relaxed) - #define VOP_WIN_SET(x, win, name, v) \ - REG_SET(x, win->base, win->phy->name, v) + vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name) #define VOP_SCL_SET(x, win, name, v) \ - REG_SET(x, win->base, win->phy->scl->name, v) + vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name) #define VOP_SCL_SET_EXT(x, win, name, v) \ - REG_SET(x, win->base, win->phy->scl->ext->name, v) -#define VOP_CTRL_SET(x, name, v) \ - REG_SET(x, 0, (x)->data->ctrl->name, v) - -#define VOP_INTR_GET(vop, name) \ - vop_read_reg(vop, 0, &vop->data->ctrl->name) - -#define VOP_INTR_SET(vop, name, v) \ - REG_SET(vop, 0, vop->data->intr->name, v) + vop_reg_set(vop, &win->phy->scl->ext->name, \ + win->base, ~0, v, #name)
#define VOP_INTR_SET_MASK(vop, name, mask, v) \ - REG_SET_MASK(vop, 0, vop->data->intr->name, mask, v) + vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name) + +#define VOP_REG_SET(vop, group, name, v) \ + vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name)
#define VOP_INTR_SET_TYPE(vop, name, type, v) \ do { \ @@ -82,7 +71,7 @@ vop_get_intr_type(vop, &vop->data->intr->name, type)
#define VOP_WIN_GET(x, win, name) \ - vop_read_reg(x, win->base, &win->phy->name) + vop_read_reg(x, win->offset, win->phy->name)
#define VOP_WIN_GET_YRGBADDR(vop, win) \ vop_readl(vop, win->base + win->phy->yrgb_mst.offset) @@ -164,14 +153,22 @@ static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base, return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask; }
-static inline void vop_mask_write(struct vop *vop, uint32_t offset, - uint32_t mask, uint32_t shift, uint32_t v, - bool write_mask, bool relaxed) +static void vop_reg_set(struct vop *vop, const struct vop_reg *reg, + uint32_t _offset, uint32_t _mask, uint32_t v, + const char *reg_name) { - if (!mask) + int offset, mask, shift; + + if (!reg || !reg->mask) { + dev_dbg(vop->dev, "Warning: not support %s\n", reg_name); return; + } + + offset = reg->offset + _offset; + mask = reg->mask & _mask; + shift = reg->shift;
- if (write_mask) { + if (reg->write_mask) { v = ((v << shift) & 0xffff) | (mask << (shift + 16)); } else { uint32_t cached_val = vop->regsbak[offset >> 2]; @@ -180,7 +177,7 @@ static inline void vop_mask_write(struct vop *vop, uint32_t offset, vop->regsbak[offset >> 2] = v; }
- if (relaxed) + if (reg->relaxed) writel_relaxed(v, vop->regs + offset); else writel(v, vop->regs + offset); @@ -202,7 +199,7 @@ static inline uint32_t vop_get_intr_type(struct vop *vop,
static inline void vop_cfg_done(struct vop *vop) { - VOP_CTRL_SET(vop, cfg_done, 1); + VOP_REG_SET(vop, common, cfg_done, 1); }
static bool has_rb_swapped(uint32_t format) @@ -540,7 +537,7 @@ static int vop_enable(struct drm_crtc *crtc)
spin_lock(&vop->reg_lock);
- VOP_CTRL_SET(vop, standby, 0); + VOP_REG_SET(vop, common, standby, 1);
spin_unlock(&vop->reg_lock);
@@ -600,7 +597,7 @@ static void vop_crtc_disable(struct drm_crtc *crtc)
spin_lock(&vop->reg_lock);
- VOP_CTRL_SET(vop, standby, 1); + VOP_REG_SET(vop, common, standby, 1);
spin_unlock(&vop->reg_lock);
@@ -923,7 +920,7 @@ static void vop_crtc_enable(struct drm_crtc *crtc)
spin_lock(&vop->reg_lock);
- VOP_CTRL_SET(vop, standby, 1); + VOP_REG_SET(vop, common, standby, 1);
spin_unlock(&vop->reg_lock);
@@ -937,29 +934,29 @@ static void vop_crtc_enable(struct drm_crtc *crtc) BIT(HSYNC_POSITIVE) : 0; pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ? BIT(VSYNC_POSITIVE) : 0; - VOP_CTRL_SET(vop, pin_pol, pin_pol); + VOP_REG_SET(vop, output, pin_pol, pin_pol);
switch (s->output_type) { case DRM_MODE_CONNECTOR_LVDS: - VOP_CTRL_SET(vop, rgb_en, 1); - VOP_CTRL_SET(vop, rgb_pin_pol, pin_pol); + VOP_REG_SET(vop, output, rgb_en, 1); + VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol); break; case DRM_MODE_CONNECTOR_eDP: - VOP_CTRL_SET(vop, edp_pin_pol, pin_pol); - VOP_CTRL_SET(vop, edp_en, 1); + VOP_REG_SET(vop, output, edp_pin_pol, pin_pol); + VOP_REG_SET(vop, output, edp_en, 1); break; case DRM_MODE_CONNECTOR_HDMIA: - VOP_CTRL_SET(vop, hdmi_pin_pol, pin_pol); - VOP_CTRL_SET(vop, hdmi_en, 1); + VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol); + VOP_REG_SET(vop, output, hdmi_en, 1); break; case DRM_MODE_CONNECTOR_DSI: - VOP_CTRL_SET(vop, mipi_pin_pol, pin_pol); - VOP_CTRL_SET(vop, mipi_en, 1); + VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol); + VOP_REG_SET(vop, output, mipi_en, 1); break; case DRM_MODE_CONNECTOR_DisplayPort: pin_pol &= ~BIT(DCLK_INVERT); - VOP_CTRL_SET(vop, dp_pin_pol, pin_pol); - VOP_CTRL_SET(vop, dp_en, 1); + VOP_REG_SET(vop, output, dp_pin_pol, pin_pol); + VOP_REG_SET(vop, output, dp_en, 1); break; default: DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n", @@ -972,25 +969,25 @@ static void vop_crtc_enable(struct drm_crtc *crtc) if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10)) s->output_mode = ROCKCHIP_OUT_MODE_P888; - VOP_CTRL_SET(vop, out_mode, s->output_mode); + VOP_REG_SET(vop, common, out_mode, s->output_mode);
- VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len); + VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len); val = hact_st << 16; val |= hact_end; - VOP_CTRL_SET(vop, hact_st_end, val); - VOP_CTRL_SET(vop, hpost_st_end, val); + VOP_REG_SET(vop, modeset, hact_st_end, val); + VOP_REG_SET(vop, modeset, hpost_st_end, val);
- VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len); + VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len); val = vact_st << 16; val |= vact_end; - VOP_CTRL_SET(vop, vact_st_end, val); - VOP_CTRL_SET(vop, vpost_st_end, val); + VOP_REG_SET(vop, modeset, vact_st_end, val); + VOP_REG_SET(vop, modeset, vpost_st_end, val);
- VOP_INTR_SET(vop, line_flag_num[0], vact_end); + VOP_REG_SET(vop, intr, line_flag_num[0], vact_end);
clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
- VOP_CTRL_SET(vop, standby, 0); + VOP_REG_SET(vop, common, standby, 0);
rockchip_drm_psr_activate(&vop->crtc); } @@ -1452,8 +1449,8 @@ static int vop_initial(struct vop *vop)
memcpy(vop->regsbak, vop->regs, vop->len);
- VOP_CTRL_SET(vop, global_regdone_en, 1); - VOP_CTRL_SET(vop, dsp_blank, 0); + VOP_REG_SET(vop, misc, global_regdone_en, 1); + VOP_REG_SET(vop, common, dsp_blank, 0);
for (i = 0; i < vop_data->win_size; i++) { const struct vop_win_data *win = &vop_data->win[i]; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h index 850f8e4..3ba962c 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h @@ -25,43 +25,50 @@ enum vop_data_format { };
struct vop_reg { - uint32_t offset; - uint32_t shift; uint32_t mask; + uint16_t offset; + uint8_t shift; bool write_mask; bool relaxed; };
-struct vop_ctrl { - struct vop_reg standby; - struct vop_reg data_blank; - struct vop_reg gate_en; - struct vop_reg mmu_en; - struct vop_reg rgb_en; +struct vop_modeset { + struct vop_reg htotal_pw; + struct vop_reg hact_st_end; + struct vop_reg hpost_st_end; + struct vop_reg vtotal_pw; + struct vop_reg vact_st_end; + struct vop_reg vpost_st_end; +}; + +struct vop_output { + struct vop_reg pin_pol; + struct vop_reg dp_pin_pol; + struct vop_reg edp_pin_pol; + struct vop_reg hdmi_pin_pol; + struct vop_reg mipi_pin_pol; + struct vop_reg rgb_pin_pol; + struct vop_reg dp_en; struct vop_reg edp_en; struct vop_reg hdmi_en; struct vop_reg mipi_en; - struct vop_reg dp_en; + struct vop_reg rgb_en; +}; + +struct vop_common { + struct vop_reg cfg_done; struct vop_reg dsp_blank; - struct vop_reg out_mode; + struct vop_reg data_blank; struct vop_reg dither_down; struct vop_reg dither_up; - struct vop_reg pin_pol; - struct vop_reg rgb_pin_pol; - struct vop_reg hdmi_pin_pol; - struct vop_reg edp_pin_pol; - struct vop_reg mipi_pin_pol; - struct vop_reg dp_pin_pol; - - struct vop_reg htotal_pw; - struct vop_reg hact_st_end; - struct vop_reg vtotal_pw; - struct vop_reg vact_st_end; - struct vop_reg hpost_st_end; - struct vop_reg vpost_st_end; + struct vop_reg gate_en; + struct vop_reg mmu_en; + struct vop_reg out_mode; + struct vop_reg standby; +};
+struct vop_misc { struct vop_reg global_regdone_en; - struct vop_reg cfg_done; };
struct vop_intr { @@ -135,8 +142,11 @@ struct vop_win_data { };
struct vop_data { - const struct vop_ctrl *ctrl; const struct vop_intr *intr; + const struct vop_common *common; + const struct vop_misc *misc; + const struct vop_modeset *modeset; + const struct vop_output *output; const struct vop_win_data *win; unsigned int win_size;
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index 0a5f0d2..20607a8 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -117,26 +117,34 @@ .intrs = rk3036_vop_intrs, .nintrs = ARRAY_SIZE(rk3036_vop_intrs), .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12), - .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0), - .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4), - .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8), + .status = VOP_REG_SYNC(RK3036_INT_STATUS, 0xf, 0), + .enable = VOP_REG_SYNC(RK3036_INT_STATUS, 0xf, 4), + .clear = VOP_REG_SYNC(RK3036_INT_STATUS, 0xf, 8), };
-static const struct vop_ctrl rk3036_ctrl_data = { - .standby = VOP_REG_SYNC(RK3036_SYS_CTRL, 0x1, 30), - .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), - .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), - .dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24), +static const struct vop_modeset rk3036_modeset = { .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), +}; + +static const struct vop_output rk3036_output = { + .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), +}; + +static const struct vop_common rk3036_common = { + .standby = VOP_REG_SYNC(RK3036_SYS_CTRL, 0x1, 30), + .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), + .dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24), .cfg_done = VOP_REG_SYNC(RK3036_REG_CFG_DONE, 0x1, 0), };
static const struct vop_data rk3036_vop = { - .ctrl = &rk3036_ctrl_data, .intr = &rk3036_intr, + .common = &rk3036_common, + .modeset = &rk3036_modeset, + .output = &rk3036_output, .win = rk3036_vop_win_data, .win_size = ARRAY_SIZE(rk3036_vop_win_data), }; @@ -206,27 +214,32 @@ .dst_alpha_ctl = VOP_REG(RK3288_WIN2_DST_ALPHA_CTRL, 0xff, 0), };
-static const struct vop_ctrl rk3288_ctrl_data = { - .standby = VOP_REG_SYNC(RK3288_SYS_CTRL, 0x1, 22), - .gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23), - .mmu_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 20), +static const struct vop_modeset rk3288_modeset = { + .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), + .hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0), + .vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), + .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0), + .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0), + .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0), +}; + +static const struct vop_output rk3288_output = { + .pin_pol = VOP_REG(RK3288_DSP_CTRL0, 0xf, 4), .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12), .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13), .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14), .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15), +}; + +static const struct vop_common rk3288_common = { + .standby = VOP_REG_SYNC(RK3288_SYS_CTRL, 0x1, 22), + .gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23), + .mmu_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 20), .dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1), .dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6), .data_blank = VOP_REG(RK3288_DSP_CTRL0, 0x1, 19), .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18), .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0), - .pin_pol = VOP_REG(RK3288_DSP_CTRL0, 0xf, 4), - .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), - .hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0), - .vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), - .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0), - .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0), - .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0), - .global_regdone_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 11), .cfg_done = VOP_REG_SYNC(RK3288_REG_CFG_DONE, 0x1, 0), };
@@ -266,37 +279,13 @@ static const struct vop_data rk3288_vop = { .feature = VOP_FEATURE_OUTPUT_RGB10, .intr = &rk3288_vop_intr, - .ctrl = &rk3288_ctrl_data, + .common = &rk3288_common, + .modeset = &rk3288_modeset, + .output = &rk3288_output, .win = rk3288_vop_win_data, .win_size = ARRAY_SIZE(rk3288_vop_win_data), };
-static const struct vop_ctrl rk3399_ctrl_data = { - .standby = VOP_REG_SYNC(RK3399_SYS_CTRL, 0x1, 22), - .gate_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 23), - .dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11), - .rgb_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 12), - .hdmi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 13), - .edp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 14), - .mipi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 15), - .dither_down = VOP_REG(RK3399_DSP_CTRL1, 0xf, 1), - .dither_up = VOP_REG(RK3399_DSP_CTRL1, 0x1, 6), - .data_blank = VOP_REG(RK3399_DSP_CTRL0, 0x1, 19), - .out_mode = VOP_REG(RK3399_DSP_CTRL0, 0xf, 0), - .rgb_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 16), - .dp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 16), - .hdmi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 20), - .edp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 24), - .mipi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 28), - .htotal_pw = VOP_REG(RK3399_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), - .hact_st_end = VOP_REG(RK3399_DSP_HACT_ST_END, 0x1fff1fff, 0), - .vtotal_pw = VOP_REG(RK3399_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), - .vact_st_end = VOP_REG(RK3399_DSP_VACT_ST_END, 0x1fff1fff, 0), - .hpost_st_end = VOP_REG(RK3399_POST_DSP_HACT_INFO, 0x1fff1fff, 0), - .vpost_st_end = VOP_REG(RK3399_POST_DSP_VACT_INFO, 0x1fff1fff, 0), - .cfg_done = VOP_REG_MASK_SYNC(RK3399_REG_CFG_DONE, 0x1, 0), -}; - static const int rk3399_vop_intrs[] = { FS_INTR, 0, 0, @@ -317,10 +306,30 @@ .clear = VOP_REG_MASK_SYNC(RK3399_INTR_CLEAR0, 0xffff, 0), };
+static const struct vop_output rk3399_output = { + .dp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 16), + .rgb_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 16), + .hdmi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 20), + .edp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 24), + .mipi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 28), + .dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11), + .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12), + .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13), + .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14), + .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15), +}; + +static const struct vop_misc rk3399_misc = { + .global_regdone_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11), +}; + static const struct vop_data rk3399_vop_big = { .feature = VOP_FEATURE_OUTPUT_RGB10, .intr = &rk3399_vop_intr, - .ctrl = &rk3399_ctrl_data, + .common = &rk3288_common, + .modeset = &rk3288_modeset, + .output = &rk3399_output, + .misc = &rk3399_misc, /* * rk3399 vop big windows register layout is same as rk3288. */ @@ -337,7 +346,10 @@
static const struct vop_data rk3399_vop_lit = { .intr = &rk3399_vop_intr, - .ctrl = &rk3399_ctrl_data, + .common = &rk3288_common, + .modeset = &rk3288_modeset, + .output = &rk3399_output, + .misc = &rk3399_misc, /* * rk3399 vop lit windows register layout is same as rk3288, * but cut off the win1 and win3 windows.
Am Freitag, 28. Juli 2017, 14:06:25 CEST schrieb Mark Yao:
Grouping the vop registers facilitates make register definition clearer, and also is useful for different vop reuse the same group register.
Signed-off-by: Mark Yao mark.yao@rock-chips.com Reviewed-by: Jeffy Chen jeffy.chen@rock-chips.com
on rk3036 and rk3288 Tested-by: Heiko Stuebner heiko@sntech.de
Vop Full framework now has following vops: IP version chipname 3.1 rk3288 3.2 rk3368 3.4 rk3366 3.5 rk3399 big 3.6 rk3399 lit 3.7 rk3228 3.8 rk3328
The above IP version is from H/W define, some of vop support get the IP version from VERSION_INFO register, some are not. hardcode the IP version for each vop to identify them.
major version: used for IP structure, Vop full framework is 3, vop little framework is 2. minor version: on same structure, newer design vop will bigger then old one.
Signed-off-by: Mark Yao mark.yao@rock-chips.com --- Changes in v3: - fixup some mistake - use separate structures instead VOP_REG_VER mechanism
Changes in v2: - rename rk322x to rk3228(Heiko Stübner) - correct some vop registers define
drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 9 + drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 218 ++++++- drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 905 ++++++++++++++++++++++------ 3 files changed, 908 insertions(+), 224 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h index 3ba962c..43d08c8 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h @@ -15,6 +15,14 @@ #ifndef _ROCKCHIP_DRM_VOP_H #define _ROCKCHIP_DRM_VOP_H
+/* + * major: IP major version, used for IP structure + * minor: big feature change under same structure + */ +#define VOP_VERSION(major, minor) ((major) << 8 | (minor)) +#define VOP_MAJOR(version) ((version) >> 8) +#define VOP_MINOR(version) ((version) & 0xff) + enum vop_data_format { VOP_FMT_ARGB8888 = 0, VOP_FMT_RGB888, @@ -142,6 +150,7 @@ struct vop_win_data { };
struct vop_data { + uint32_t version; const struct vop_intr *intr; const struct vop_common *common; const struct vop_misc *misc; diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index 20607a8..bc7b2d0 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -277,6 +277,7 @@ };
static const struct vop_data rk3288_vop = { + .version = VOP_VERSION(3, 1), .feature = VOP_FEATURE_OUTPUT_RGB10, .intr = &rk3288_vop_intr, .common = &rk3288_common, @@ -286,7 +287,7 @@ .win_size = ARRAY_SIZE(rk3288_vop_win_data), };
-static const int rk3399_vop_intrs[] = { +static const int rk3368_vop_intrs[] = { FS_INTR, 0, 0, LINE_FLAG_INTR, @@ -296,22 +297,95 @@ DSP_HOLD_VALID_INTR, };
-static const struct vop_intr rk3399_vop_intr = { - .intrs = rk3399_vop_intrs, - .nintrs = ARRAY_SIZE(rk3399_vop_intrs), - .line_flag_num[0] = VOP_REG(RK3399_LINE_FLAG, 0xffff, 0), - .line_flag_num[1] = VOP_REG(RK3399_LINE_FLAG, 0xffff, 16), - .status = VOP_REG_MASK_SYNC(RK3399_INTR_STATUS0, 0xffff, 0), - .enable = VOP_REG_MASK_SYNC(RK3399_INTR_EN0, 0xffff, 0), - .clear = VOP_REG_MASK_SYNC(RK3399_INTR_CLEAR0, 0xffff, 0), +static const struct vop_intr rk3368_vop_intr = { + .intrs = rk3368_vop_intrs, + .nintrs = ARRAY_SIZE(rk3368_vop_intrs), + .line_flag_num[0] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 0), + .line_flag_num[1] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 16), + .status = VOP_REG_MASK_SYNC(RK3368_INTR_STATUS, 0x3fff, 0), + .enable = VOP_REG_MASK_SYNC(RK3368_INTR_EN, 0x3fff, 0), + .clear = VOP_REG_MASK_SYNC(RK3368_INTR_CLEAR, 0x3fff, 0), +}; + +static const struct vop_win_phy rk3368_win23_data = { + .data_formats = formats_win_lite, + .nformats = ARRAY_SIZE(formats_win_lite), + .gate = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 0), + .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 4), + .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 5), + .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 20), + .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO0, 0x0fff0fff, 0), + .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST0, 0x1fff1fff, 0), + .yrgb_mst = VOP_REG(RK3368_WIN2_MST0, 0xffffffff, 0), + .yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 0), + .src_alpha_ctl = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0xff, 0), + .dst_alpha_ctl = VOP_REG(RK3368_WIN2_DST_ALPHA_CTRL, 0xff, 0), +}; + +static const struct vop_win_data rk3368_vop_win_data[] = { + { .base = 0x00, .phy = &rk3288_win01_data, + .type = DRM_PLANE_TYPE_PRIMARY }, + { .base = 0x40, .phy = &rk3288_win01_data, + .type = DRM_PLANE_TYPE_OVERLAY }, + { .base = 0x00, .phy = &rk3368_win23_data, + .type = DRM_PLANE_TYPE_OVERLAY }, + { .base = 0x50, .phy = &rk3368_win23_data, + .type = DRM_PLANE_TYPE_CURSOR }, +}; + +static const struct vop_output rk3368_output = { + .rgb_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 16), + .hdmi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 20), + .edp_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 24), + .mipi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 28), + .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12), + .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13), + .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14), + .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15), +}; + +static const struct vop_misc rk3368_misc = { + .global_regdone_en = VOP_REG(RK3368_SYS_CTRL, 0x1, 11), +}; + +static const struct vop_data rk3368_vop = { + .version = VOP_VERSION(3, 2), + .intr = &rk3368_vop_intr, + .common = &rk3288_common, + .modeset = &rk3288_modeset, + .output = &rk3368_output, + .misc = &rk3368_misc, + .win = rk3368_vop_win_data, + .win_size = ARRAY_SIZE(rk3368_vop_win_data), +}; + +static const struct vop_intr rk3366_vop_intr = { + .intrs = rk3368_vop_intrs, + .nintrs = ARRAY_SIZE(rk3368_vop_intrs), + .line_flag_num[0] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 0), + .line_flag_num[1] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 16), + .status = VOP_REG_MASK_SYNC(RK3366_INTR_STATUS0, 0xffff, 0), + .enable = VOP_REG_MASK_SYNC(RK3366_INTR_EN0, 0xffff, 0), + .clear = VOP_REG_MASK_SYNC(RK3366_INTR_CLEAR0, 0xffff, 0), +}; + +static const struct vop_data rk3366_vop = { + .version = VOP_VERSION(3, 4), + .intr = &rk3366_vop_intr, + .common = &rk3288_common, + .modeset = &rk3288_modeset, + .output = &rk3368_output, + .misc = &rk3368_misc, + .win = rk3368_vop_win_data, + .win_size = ARRAY_SIZE(rk3368_vop_win_data), };
static const struct vop_output rk3399_output = { .dp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 16), - .rgb_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 16), - .hdmi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 20), - .edp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 24), - .mipi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 28), + .rgb_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 16), + .hdmi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 20), + .edp_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 24), + .mipi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 28), .dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11), .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12), .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13), @@ -319,54 +393,136 @@ .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15), };
-static const struct vop_misc rk3399_misc = { - .global_regdone_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11), -}; - static const struct vop_data rk3399_vop_big = { + .version = VOP_VERSION(3, 5), .feature = VOP_FEATURE_OUTPUT_RGB10, - .intr = &rk3399_vop_intr, + .intr = &rk3366_vop_intr, .common = &rk3288_common, .modeset = &rk3288_modeset, .output = &rk3399_output, - .misc = &rk3399_misc, - /* - * rk3399 vop big windows register layout is same as rk3288. - */ - .win = rk3288_vop_win_data, - .win_size = ARRAY_SIZE(rk3288_vop_win_data), + .misc = &rk3368_misc, + .win = rk3368_vop_win_data, + .win_size = ARRAY_SIZE(rk3368_vop_win_data), };
static const struct vop_win_data rk3399_vop_lit_win_data[] = { { .base = 0x00, .phy = &rk3288_win01_data, .type = DRM_PLANE_TYPE_PRIMARY }, - { .base = 0x00, .phy = &rk3288_win23_data, + { .base = 0x00, .phy = &rk3368_win23_data, .type = DRM_PLANE_TYPE_CURSOR}, };
static const struct vop_data rk3399_vop_lit = { - .intr = &rk3399_vop_intr, + .version = VOP_VERSION(3, 6), + .intr = &rk3366_vop_intr, .common = &rk3288_common, .modeset = &rk3288_modeset, .output = &rk3399_output, - .misc = &rk3399_misc, - /* - * rk3399 vop lit windows register layout is same as rk3288, - * but cut off the win1 and win3 windows. - */ + .misc = &rk3368_misc, .win = rk3399_vop_lit_win_data, .win_size = ARRAY_SIZE(rk3399_vop_lit_win_data), };
+static const struct vop_win_data rk3228_vop_win_data[] = { + { .base = 0x00, .phy = &rk3288_win01_data, + .type = DRM_PLANE_TYPE_PRIMARY }, + { .base = 0x40, .phy = &rk3288_win01_data, + .type = DRM_PLANE_TYPE_CURSOR }, +}; + +static const struct vop_data rk3228_vop = { + .version = VOP_VERSION(3, 7), + .feature = VOP_FEATURE_OUTPUT_RGB10, + .intr = &rk3366_vop_intr, + .common = &rk3288_common, + .modeset = &rk3288_modeset, + .output = &rk3399_output, + .misc = &rk3368_misc, + .win = rk3228_vop_win_data, + .win_size = ARRAY_SIZE(rk3228_vop_win_data), +}; + +static const struct vop_modeset rk3328_modeset = { + .htotal_pw = VOP_REG(RK3328_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), + .hact_st_end = VOP_REG(RK3328_DSP_HACT_ST_END, 0x1fff1fff, 0), + .vtotal_pw = VOP_REG(RK3328_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), + .vact_st_end = VOP_REG(RK3328_DSP_VACT_ST_END, 0x1fff1fff, 0), + .hpost_st_end = VOP_REG(RK3328_POST_DSP_HACT_INFO, 0x1fff1fff, 0), + .vpost_st_end = VOP_REG(RK3328_POST_DSP_VACT_INFO, 0x1fff1fff, 0), +}; + +static const struct vop_output rk3328_output = { + .rgb_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 12), + .hdmi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 13), + .edp_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 14), + .mipi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 15), + .rgb_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 16), + .hdmi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 20), + .edp_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 24), + .mipi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 28), +}; + +static const struct vop_misc rk3328_misc = { + .global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11), +}; + +static const struct vop_common rk3328_common = { + .standby = VOP_REG_SYNC(RK3328_SYS_CTRL, 0x1, 22), + .dither_down = VOP_REG(RK3328_DSP_CTRL1, 0xf, 1), + .dither_up = VOP_REG(RK3328_DSP_CTRL1, 0x1, 6), + .dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18), + .out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0), + .cfg_done = VOP_REG_SYNC(RK3328_REG_CFG_DONE, 0x1, 0), +}; + +static const struct vop_intr rk3328_vop_intr = { + .intrs = rk3368_vop_intrs, + .nintrs = ARRAY_SIZE(rk3368_vop_intrs), + .line_flag_num[0] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 0), + .line_flag_num[1] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 16), + .status = VOP_REG_MASK_SYNC(RK3328_INTR_STATUS0, 0xffff, 0), + .enable = VOP_REG_MASK_SYNC(RK3328_INTR_EN0, 0xffff, 0), + .clear = VOP_REG_MASK_SYNC(RK3328_INTR_CLEAR0, 0xffff, 0), +}; + +static const struct vop_win_data rk3328_vop_win_data[] = { + { .base = 0xd0, .phy = &rk3288_win01_data, + .type = DRM_PLANE_TYPE_PRIMARY }, + { .base = 0x1d0, .phy = &rk3288_win01_data, + .type = DRM_PLANE_TYPE_OVERLAY }, + { .base = 0x2d0, .phy = &rk3288_win01_data, + .type = DRM_PLANE_TYPE_CURSOR }, +}; + +static const struct vop_data rk3328_vop = { + .version = VOP_VERSION(3, 8), + .feature = VOP_FEATURE_OUTPUT_RGB10, + .intr = &rk3328_vop_intr, + .common = &rk3328_common, + .modeset = &rk3328_modeset, + .output = &rk3328_output, + .misc = &rk3328_misc, + .win = rk3328_vop_win_data, + .win_size = ARRAY_SIZE(rk3328_vop_win_data), +}; + static const struct of_device_id vop_driver_dt_match[] = { { .compatible = "rockchip,rk3036-vop", .data = &rk3036_vop }, { .compatible = "rockchip,rk3288-vop", .data = &rk3288_vop }, + { .compatible = "rockchip,rk3368-vop", + .data = &rk3368_vop }, + { .compatible = "rockchip,rk3366-vop", + .data = &rk3366_vop }, { .compatible = "rockchip,rk3399-vop-big", .data = &rk3399_vop_big }, { .compatible = "rockchip,rk3399-vop-lit", .data = &rk3399_vop_lit }, + { .compatible = "rockchip,rk3228-vop", + .data = &rk3228_vop }, + { .compatible = "rockchip,rk3328-vop", + .data = &rk3328_vop }, {}, }; MODULE_DEVICE_TABLE(of, vop_driver_dt_match); diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h index cd19726..4a4799f 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.h +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.h @@ -41,6 +41,7 @@ #define RK3288_WIN0_SRC_ALPHA_CTRL 0x0060 #define RK3288_WIN0_DST_ALPHA_CTRL 0x0064 #define RK3288_WIN0_FADING_CTRL 0x0068 +#define RK3288_WIN0_CTRL2 0x006c
/* win1 register */ #define RK3288_WIN1_CTRL0 0x0070 @@ -122,6 +123,717 @@ #define RK3288_DSP_VACT_ST_END_F1 0x019c /* register definition end */
+/* rk3368 register definition */ +#define RK3368_REG_CFG_DONE 0x0000 +#define RK3368_VERSION_INFO 0x0004 +#define RK3368_SYS_CTRL 0x0008 +#define RK3368_SYS_CTRL1 0x000c +#define RK3368_DSP_CTRL0 0x0010 +#define RK3368_DSP_CTRL1 0x0014 +#define RK3368_DSP_BG 0x0018 +#define RK3368_MCU_CTRL 0x001c +#define RK3368_LINE_FLAG 0x0020 +#define RK3368_INTR_EN 0x0024 +#define RK3368_INTR_CLEAR 0x0028 +#define RK3368_INTR_STATUS 0x002c +#define RK3368_WIN0_CTRL0 0x0030 +#define RK3368_WIN0_CTRL1 0x0034 +#define RK3368_WIN0_COLOR_KEY 0x0038 +#define RK3368_WIN0_VIR 0x003c +#define RK3368_WIN0_YRGB_MST 0x0040 +#define RK3368_WIN0_CBR_MST 0x0044 +#define RK3368_WIN0_ACT_INFO 0x0048 +#define RK3368_WIN0_DSP_INFO 0x004c +#define RK3368_WIN0_DSP_ST 0x0050 +#define RK3368_WIN0_SCL_FACTOR_YRGB 0x0054 +#define RK3368_WIN0_SCL_FACTOR_CBR 0x0058 +#define RK3368_WIN0_SCL_OFFSET 0x005c +#define RK3368_WIN0_SRC_ALPHA_CTRL 0x0060 +#define RK3368_WIN0_DST_ALPHA_CTRL 0x0064 +#define RK3368_WIN0_FADING_CTRL 0x0068 +#define RK3368_WIN0_CTRL2 0x006c +#define RK3368_WIN1_CTRL0 0x0070 +#define RK3368_WIN1_CTRL1 0x0074 +#define RK3368_WIN1_COLOR_KEY 0x0078 +#define RK3368_WIN1_VIR 0x007c +#define RK3368_WIN1_YRGB_MST 0x0080 +#define RK3368_WIN1_CBR_MST 0x0084 +#define RK3368_WIN1_ACT_INFO 0x0088 +#define RK3368_WIN1_DSP_INFO 0x008c +#define RK3368_WIN1_DSP_ST 0x0090 +#define RK3368_WIN1_SCL_FACTOR_YRGB 0x0094 +#define RK3368_WIN1_SCL_FACTOR_CBR 0x0098 +#define RK3368_WIN1_SCL_OFFSET 0x009c +#define RK3368_WIN1_SRC_ALPHA_CTRL 0x00a0 +#define RK3368_WIN1_DST_ALPHA_CTRL 0x00a4 +#define RK3368_WIN1_FADING_CTRL 0x00a8 +#define RK3368_WIN1_CTRL2 0x00ac +#define RK3368_WIN2_CTRL0 0x00b0 +#define RK3368_WIN2_CTRL1 0x00b4 +#define RK3368_WIN2_VIR0_1 0x00b8 +#define RK3368_WIN2_VIR2_3 0x00bc +#define RK3368_WIN2_MST0 0x00c0 +#define RK3368_WIN2_DSP_INFO0 0x00c4 +#define RK3368_WIN2_DSP_ST0 0x00c8 +#define RK3368_WIN2_COLOR_KEY 0x00cc +#define RK3368_WIN2_MST1 0x00d0 +#define RK3368_WIN2_DSP_INFO1 0x00d4 +#define RK3368_WIN2_DSP_ST1 0x00d8 +#define RK3368_WIN2_SRC_ALPHA_CTRL 0x00dc +#define RK3368_WIN2_MST2 0x00e0 +#define RK3368_WIN2_DSP_INFO2 0x00e4 +#define RK3368_WIN2_DSP_ST2 0x00e8 +#define RK3368_WIN2_DST_ALPHA_CTRL 0x00ec +#define RK3368_WIN2_MST3 0x00f0 +#define RK3368_WIN2_DSP_INFO3 0x00f4 +#define RK3368_WIN2_DSP_ST3 0x00f8 +#define RK3368_WIN2_FADING_CTRL 0x00fc +#define RK3368_WIN3_CTRL0 0x0100 +#define RK3368_WIN3_CTRL1 0x0104 +#define RK3368_WIN3_VIR0_1 0x0108 +#define RK3368_WIN3_VIR2_3 0x010c +#define RK3368_WIN3_MST0 0x0110 +#define RK3368_WIN3_DSP_INFO0 0x0114 +#define RK3368_WIN3_DSP_ST0 0x0118 +#define RK3368_WIN3_COLOR_KEY 0x011c +#define RK3368_WIN3_MST1 0x0120 +#define RK3368_WIN3_DSP_INFO1 0x0124 +#define RK3368_WIN3_DSP_ST1 0x0128 +#define RK3368_WIN3_SRC_ALPHA_CTRL 0x012c +#define RK3368_WIN3_MST2 0x0130 +#define RK3368_WIN3_DSP_INFO2 0x0134 +#define RK3368_WIN3_DSP_ST2 0x0138 +#define RK3368_WIN3_DST_ALPHA_CTRL 0x013c +#define RK3368_WIN3_MST3 0x0140 +#define RK3368_WIN3_DSP_INFO3 0x0144 +#define RK3368_WIN3_DSP_ST3 0x0148 +#define RK3368_WIN3_FADING_CTRL 0x014c +#define RK3368_HWC_CTRL0 0x0150 +#define RK3368_HWC_CTRL1 0x0154 +#define RK3368_HWC_MST 0x0158 +#define RK3368_HWC_DSP_ST 0x015c +#define RK3368_HWC_SRC_ALPHA_CTRL 0x0160 +#define RK3368_HWC_DST_ALPHA_CTRL 0x0164 +#define RK3368_HWC_FADING_CTRL 0x0168 +#define RK3368_HWC_RESERVED1 0x016c +#define RK3368_POST_DSP_HACT_INFO 0x0170 +#define RK3368_POST_DSP_VACT_INFO 0x0174 +#define RK3368_POST_SCL_FACTOR_YRGB 0x0178 +#define RK3368_POST_RESERVED 0x017c +#define RK3368_POST_SCL_CTRL 0x0180 +#define RK3368_POST_DSP_VACT_INFO_F1 0x0184 +#define RK3368_DSP_HTOTAL_HS_END 0x0188 +#define RK3368_DSP_HACT_ST_END 0x018c +#define RK3368_DSP_VTOTAL_VS_END 0x0190 +#define RK3368_DSP_VACT_ST_END 0x0194 +#define RK3368_DSP_VS_ST_END_F1 0x0198 +#define RK3368_DSP_VACT_ST_END_F1 0x019c +#define RK3368_PWM_CTRL 0x01a0 +#define RK3368_PWM_PERIOD_HPR 0x01a4 +#define RK3368_PWM_DUTY_LPR 0x01a8 +#define RK3368_PWM_CNT 0x01ac +#define RK3368_BCSH_COLOR_BAR 0x01b0 +#define RK3368_BCSH_BCS 0x01b4 +#define RK3368_BCSH_H 0x01b8 +#define RK3368_BCSH_CTRL 0x01bc +#define RK3368_CABC_CTRL0 0x01c0 +#define RK3368_CABC_CTRL1 0x01c4 +#define RK3368_CABC_CTRL2 0x01c8 +#define RK3368_CABC_CTRL3 0x01cc +#define RK3368_CABC_GAUSS_LINE0_0 0x01d0 +#define RK3368_CABC_GAUSS_LINE0_1 0x01d4 +#define RK3368_CABC_GAUSS_LINE1_0 0x01d8 +#define RK3368_CABC_GAUSS_LINE1_1 0x01dc +#define RK3368_CABC_GAUSS_LINE2_0 0x01e0 +#define RK3368_CABC_GAUSS_LINE2_1 0x01e4 +#define RK3368_FRC_LOWER01_0 0x01e8 +#define RK3368_FRC_LOWER01_1 0x01ec +#define RK3368_FRC_LOWER10_0 0x01f0 +#define RK3368_FRC_LOWER10_1 0x01f4 +#define RK3368_FRC_LOWER11_0 0x01f8 +#define RK3368_FRC_LOWER11_1 0x01fc +#define RK3368_IFBDC_CTRL 0x0200 +#define RK3368_IFBDC_TILES_NUM 0x0204 +#define RK3368_IFBDC_FRAME_RST_CYCLE 0x0208 +#define RK3368_IFBDC_BASE_ADDR 0x020c +#define RK3368_IFBDC_MB_SIZE 0x0210 +#define RK3368_IFBDC_CMP_INDEX_INIT 0x0214 +#define RK3368_IFBDC_VIR 0x0220 +#define RK3368_IFBDC_DEBUG0 0x0230 +#define RK3368_IFBDC_DEBUG1 0x0234 +#define RK3368_LATENCY_CTRL0 0x0250 +#define RK3368_RD_MAX_LATENCY_NUM0 0x0254 +#define RK3368_RD_LATENCY_THR_NUM0 0x0258 +#define RK3368_RD_LATENCY_SAMP_NUM0 0x025c +#define RK3368_WIN0_DSP_BG 0x0260 +#define RK3368_WIN1_DSP_BG 0x0264 +#define RK3368_WIN2_DSP_BG 0x0268 +#define RK3368_WIN3_DSP_BG 0x026c +#define RK3368_SCAN_LINE_NUM 0x0270 +#define RK3368_CABC_DEBUG0 0x0274 +#define RK3368_CABC_DEBUG1 0x0278 +#define RK3368_CABC_DEBUG2 0x027c +#define RK3368_DBG_REG_000 0x0280 +#define RK3368_DBG_REG_001 0x0284 +#define RK3368_DBG_REG_002 0x0288 +#define RK3368_DBG_REG_003 0x028c +#define RK3368_DBG_REG_004 0x0290 +#define RK3368_DBG_REG_005 0x0294 +#define RK3368_DBG_REG_006 0x0298 +#define RK3368_DBG_REG_007 0x029c +#define RK3368_DBG_REG_008 0x02a0 +#define RK3368_DBG_REG_016 0x02c0 +#define RK3368_DBG_REG_017 0x02c4 +#define RK3368_DBG_REG_018 0x02c8 +#define RK3368_DBG_REG_019 0x02cc +#define RK3368_DBG_REG_020 0x02d0 +#define RK3368_DBG_REG_021 0x02d4 +#define RK3368_DBG_REG_022 0x02d8 +#define RK3368_DBG_REG_023 0x02dc +#define RK3368_DBG_REG_028 0x02f0 +#define RK3368_MMU_DTE_ADDR 0x0300 +#define RK3368_MMU_STATUS 0x0304 +#define RK3368_MMU_COMMAND 0x0308 +#define RK3368_MMU_PAGE_FAULT_ADDR 0x030c +#define RK3368_MMU_ZAP_ONE_LINE 0x0310 +#define RK3368_MMU_INT_RAWSTAT 0x0314 +#define RK3368_MMU_INT_CLEAR 0x0318 +#define RK3368_MMU_INT_MASK 0x031c +#define RK3368_MMU_INT_STATUS 0x0320 +#define RK3368_MMU_AUTO_GATING 0x0324 +#define RK3368_WIN2_LUT_ADDR 0x0400 +#define RK3368_WIN3_LUT_ADDR 0x0800 +#define RK3368_HWC_LUT_ADDR 0x0c00 +#define RK3368_GAMMA_LUT_ADDR 0x1000 +#define RK3368_CABC_GAMMA_LUT_ADDR 0x1800 +#define RK3368_MCU_BYPASS_WPORT 0x2200 +#define RK3368_MCU_BYPASS_RPORT 0x2300 +/* rk3368 register definition end */ + +#define RK3366_REG_CFG_DONE 0x0000 +#define RK3366_VERSION_INFO 0x0004 +#define RK3366_SYS_CTRL 0x0008 +#define RK3366_SYS_CTRL1 0x000c +#define RK3366_DSP_CTRL0 0x0010 +#define RK3366_DSP_CTRL1 0x0014 +#define RK3366_DSP_BG 0x0018 +#define RK3366_MCU_CTRL 0x001c +#define RK3366_WB_CTRL0 0x0020 +#define RK3366_WB_CTRL1 0x0024 +#define RK3366_WB_YRGB_MST 0x0028 +#define RK3366_WB_CBR_MST 0x002c +#define RK3366_WIN0_CTRL0 0x0030 +#define RK3366_WIN0_CTRL1 0x0034 +#define RK3366_WIN0_COLOR_KEY 0x0038 +#define RK3366_WIN0_VIR 0x003c +#define RK3366_WIN0_YRGB_MST 0x0040 +#define RK3366_WIN0_CBR_MST 0x0044 +#define RK3366_WIN0_ACT_INFO 0x0048 +#define RK3366_WIN0_DSP_INFO 0x004c +#define RK3366_WIN0_DSP_ST 0x0050 +#define RK3366_WIN0_SCL_FACTOR_YRGB 0x0054 +#define RK3366_WIN0_SCL_FACTOR_CBR 0x0058 +#define RK3366_WIN0_SCL_OFFSET 0x005c +#define RK3366_WIN0_SRC_ALPHA_CTRL 0x0060 +#define RK3366_WIN0_DST_ALPHA_CTRL 0x0064 +#define RK3366_WIN0_FADING_CTRL 0x0068 +#define RK3366_WIN0_CTRL2 0x006c +#define RK3366_WIN1_CTRL0 0x0070 +#define RK3366_WIN1_CTRL1 0x0074 +#define RK3366_WIN1_COLOR_KEY 0x0078 +#define RK3366_WIN1_VIR 0x007c +#define RK3366_WIN1_YRGB_MST 0x0080 +#define RK3366_WIN1_CBR_MST 0x0084 +#define RK3366_WIN1_ACT_INFO 0x0088 +#define RK3366_WIN1_DSP_INFO 0x008c +#define RK3366_WIN1_DSP_ST 0x0090 +#define RK3366_WIN1_SCL_FACTOR_YRGB 0x0094 +#define RK3366_WIN1_SCL_FACTOR_CBR 0x0098 +#define RK3366_WIN1_SCL_OFFSET 0x009c +#define RK3366_WIN1_SRC_ALPHA_CTRL 0x00a0 +#define RK3366_WIN1_DST_ALPHA_CTRL 0x00a4 +#define RK3366_WIN1_FADING_CTRL 0x00a8 +#define RK3366_WIN1_CTRL2 0x00ac +#define RK3366_WIN2_CTRL0 0x00b0 +#define RK3366_WIN2_CTRL1 0x00b4 +#define RK3366_WIN2_VIR0_1 0x00b8 +#define RK3366_WIN2_VIR2_3 0x00bc +#define RK3366_WIN2_MST0 0x00c0 +#define RK3366_WIN2_DSP_INFO0 0x00c4 +#define RK3366_WIN2_DSP_ST0 0x00c8 +#define RK3366_WIN2_COLOR_KEY 0x00cc +#define RK3366_WIN2_MST1 0x00d0 +#define RK3366_WIN2_DSP_INFO1 0x00d4 +#define RK3366_WIN2_DSP_ST1 0x00d8 +#define RK3366_WIN2_SRC_ALPHA_CTRL 0x00dc +#define RK3366_WIN2_MST2 0x00e0 +#define RK3366_WIN2_DSP_INFO2 0x00e4 +#define RK3366_WIN2_DSP_ST2 0x00e8 +#define RK3366_WIN2_DST_ALPHA_CTRL 0x00ec +#define RK3366_WIN2_MST3 0x00f0 +#define RK3366_WIN2_DSP_INFO3 0x00f4 +#define RK3366_WIN2_DSP_ST3 0x00f8 +#define RK3366_WIN2_FADING_CTRL 0x00fc +#define RK3366_WIN3_CTRL0 0x0100 +#define RK3366_WIN3_CTRL1 0x0104 +#define RK3366_WIN3_VIR0_1 0x0108 +#define RK3366_WIN3_VIR2_3 0x010c +#define RK3366_WIN3_MST0 0x0110 +#define RK3366_WIN3_DSP_INFO0 0x0114 +#define RK3366_WIN3_DSP_ST0 0x0118 +#define RK3366_WIN3_COLOR_KEY 0x011c +#define RK3366_WIN3_MST1 0x0120 +#define RK3366_WIN3_DSP_INFO1 0x0124 +#define RK3366_WIN3_DSP_ST1 0x0128 +#define RK3366_WIN3_SRC_ALPHA_CTRL 0x012c +#define RK3366_WIN3_MST2 0x0130 +#define RK3366_WIN3_DSP_INFO2 0x0134 +#define RK3366_WIN3_DSP_ST2 0x0138 +#define RK3366_WIN3_DST_ALPHA_CTRL 0x013c +#define RK3366_WIN3_MST3 0x0140 +#define RK3366_WIN3_DSP_INFO3 0x0144 +#define RK3366_WIN3_DSP_ST3 0x0148 +#define RK3366_WIN3_FADING_CTRL 0x014c +#define RK3366_HWC_CTRL0 0x0150 +#define RK3366_HWC_CTRL1 0x0154 +#define RK3366_HWC_MST 0x0158 +#define RK3366_HWC_DSP_ST 0x015c +#define RK3366_HWC_SRC_ALPHA_CTRL 0x0160 +#define RK3366_HWC_DST_ALPHA_CTRL 0x0164 +#define RK3366_HWC_FADING_CTRL 0x0168 +#define RK3366_HWC_RESERVED1 0x016c +#define RK3366_POST_DSP_HACT_INFO 0x0170 +#define RK3366_POST_DSP_VACT_INFO 0x0174 +#define RK3366_POST_SCL_FACTOR_YRGB 0x0178 +#define RK3366_POST_RESERVED 0x017c +#define RK3366_POST_SCL_CTRL 0x0180 +#define RK3366_POST_DSP_VACT_INFO_F1 0x0184 +#define RK3366_DSP_HTOTAL_HS_END 0x0188 +#define RK3366_DSP_HACT_ST_END 0x018c +#define RK3366_DSP_VTOTAL_VS_END 0x0190 +#define RK3366_DSP_VACT_ST_END 0x0194 +#define RK3366_DSP_VS_ST_END_F1 0x0198 +#define RK3366_DSP_VACT_ST_END_F1 0x019c +#define RK3366_PWM_CTRL 0x01a0 +#define RK3366_PWM_PERIOD_HPR 0x01a4 +#define RK3366_PWM_DUTY_LPR 0x01a8 +#define RK3366_PWM_CNT 0x01ac +#define RK3366_BCSH_COLOR_BAR 0x01b0 +#define RK3366_BCSH_BCS 0x01b4 +#define RK3366_BCSH_H 0x01b8 +#define RK3366_BCSH_CTRL 0x01bc +#define RK3366_CABC_CTRL0 0x01c0 +#define RK3366_CABC_CTRL1 0x01c4 +#define RK3366_CABC_CTRL2 0x01c8 +#define RK3366_CABC_CTRL3 0x01cc +#define RK3366_CABC_GAUSS_LINE0_0 0x01d0 +#define RK3366_CABC_GAUSS_LINE0_1 0x01d4 +#define RK3366_CABC_GAUSS_LINE1_0 0x01d8 +#define RK3366_CABC_GAUSS_LINE1_1 0x01dc +#define RK3366_CABC_GAUSS_LINE2_0 0x01e0 +#define RK3366_CABC_GAUSS_LINE2_1 0x01e4 +#define RK3366_FRC_LOWER01_0 0x01e8 +#define RK3366_FRC_LOWER01_1 0x01ec +#define RK3366_FRC_LOWER10_0 0x01f0 +#define RK3366_FRC_LOWER10_1 0x01f4 +#define RK3366_FRC_LOWER11_0 0x01f8 +#define RK3366_FRC_LOWER11_1 0x01fc +#define RK3366_INTR_EN0 0x0280 +#define RK3366_INTR_CLEAR0 0x0284 +#define RK3366_INTR_STATUS0 0x0288 +#define RK3366_INTR_RAW_STATUS0 0x028c +#define RK3366_INTR_EN1 0x0290 +#define RK3366_INTR_CLEAR1 0x0294 +#define RK3366_INTR_STATUS1 0x0298 +#define RK3366_INTR_RAW_STATUS1 0x029c +#define RK3366_LINE_FLAG 0x02a0 +#define RK3366_VOP_STATUS 0x02a4 +#define RK3366_BLANKING_VALUE 0x02a8 +#define RK3366_WIN0_DSP_BG 0x02b0 +#define RK3366_WIN1_DSP_BG 0x02b4 +#define RK3366_WIN2_DSP_BG 0x02b8 +#define RK3366_WIN3_DSP_BG 0x02bc +#define RK3366_WIN2_LUT_ADDR 0x0400 +#define RK3366_WIN3_LUT_ADDR 0x0800 +#define RK3366_HWC_LUT_ADDR 0x0c00 +#define RK3366_GAMMA0_LUT_ADDR 0x1000 +#define RK3366_GAMMA1_LUT_ADDR 0x1400 +#define RK3366_CABC_GAMMA_LUT_ADDR 0x1800 +#define RK3366_MCU_BYPASS_WPORT 0x2200 +#define RK3366_MCU_BYPASS_RPORT 0x2300 +#define RK3366_MMU_DTE_ADDR 0x2400 +#define RK3366_MMU_STATUS 0x2404 +#define RK3366_MMU_COMMAND 0x2408 +#define RK3366_MMU_PAGE_FAULT_ADDR 0x240c +#define RK3366_MMU_ZAP_ONE_LINE 0x2410 +#define RK3366_MMU_INT_RAWSTAT 0x2414 +#define RK3366_MMU_INT_CLEAR 0x2418 +#define RK3366_MMU_INT_MASK 0x241c +#define RK3366_MMU_INT_STATUS 0x2420 +#define RK3366_MMU_AUTO_GATING 0x2424 + +/* rk3399 register definition */ +#define RK3399_REG_CFG_DONE 0x0000 +#define RK3399_VERSION_INFO 0x0004 +#define RK3399_SYS_CTRL 0x0008 +#define RK3399_SYS_CTRL1 0x000c +#define RK3399_DSP_CTRL0 0x0010 +#define RK3399_DSP_CTRL1 0x0014 +#define RK3399_DSP_BG 0x0018 +#define RK3399_MCU_CTRL 0x001c +#define RK3399_WB_CTRL0 0x0020 +#define RK3399_WB_CTRL1 0x0024 +#define RK3399_WB_YRGB_MST 0x0028 +#define RK3399_WB_CBR_MST 0x002c +#define RK3399_WIN0_CTRL0 0x0030 +#define RK3399_WIN0_CTRL1 0x0034 +#define RK3399_WIN0_COLOR_KEY 0x0038 +#define RK3399_WIN0_VIR 0x003c +#define RK3399_WIN0_YRGB_MST 0x0040 +#define RK3399_WIN0_CBR_MST 0x0044 +#define RK3399_WIN0_ACT_INFO 0x0048 +#define RK3399_WIN0_DSP_INFO 0x004c +#define RK3399_WIN0_DSP_ST 0x0050 +#define RK3399_WIN0_SCL_FACTOR_YRGB 0x0054 +#define RK3399_WIN0_SCL_FACTOR_CBR 0x0058 +#define RK3399_WIN0_SCL_OFFSET 0x005c +#define RK3399_WIN0_SRC_ALPHA_CTRL 0x0060 +#define RK3399_WIN0_DST_ALPHA_CTRL 0x0064 +#define RK3399_WIN0_FADING_CTRL 0x0068 +#define RK3399_WIN0_CTRL2 0x006c +#define RK3399_WIN1_CTRL0 0x0070 +#define RK3399_WIN1_CTRL1 0x0074 +#define RK3399_WIN1_COLOR_KEY 0x0078 +#define RK3399_WIN1_VIR 0x007c +#define RK3399_WIN1_YRGB_MST 0x0080 +#define RK3399_WIN1_CBR_MST 0x0084 +#define RK3399_WIN1_ACT_INFO 0x0088 +#define RK3399_WIN1_DSP_INFO 0x008c +#define RK3399_WIN1_DSP_ST 0x0090 +#define RK3399_WIN1_SCL_FACTOR_YRGB 0x0094 +#define RK3399_WIN1_SCL_FACTOR_CBR 0x0098 +#define RK3399_WIN1_SCL_OFFSET 0x009c +#define RK3399_WIN1_SRC_ALPHA_CTRL 0x00a0 +#define RK3399_WIN1_DST_ALPHA_CTRL 0x00a4 +#define RK3399_WIN1_FADING_CTRL 0x00a8 +#define RK3399_WIN1_CTRL2 0x00ac +#define RK3399_WIN2_CTRL0 0x00b0 +#define RK3399_WIN2_CTRL1 0x00b4 +#define RK3399_WIN2_VIR0_1 0x00b8 +#define RK3399_WIN2_VIR2_3 0x00bc +#define RK3399_WIN2_MST0 0x00c0 +#define RK3399_WIN2_DSP_INFO0 0x00c4 +#define RK3399_WIN2_DSP_ST0 0x00c8 +#define RK3399_WIN2_COLOR_KEY 0x00cc +#define RK3399_WIN2_MST1 0x00d0 +#define RK3399_WIN2_DSP_INFO1 0x00d4 +#define RK3399_WIN2_DSP_ST1 0x00d8 +#define RK3399_WIN2_SRC_ALPHA_CTRL 0x00dc +#define RK3399_WIN2_MST2 0x00e0 +#define RK3399_WIN2_DSP_INFO2 0x00e4 +#define RK3399_WIN2_DSP_ST2 0x00e8 +#define RK3399_WIN2_DST_ALPHA_CTRL 0x00ec +#define RK3399_WIN2_MST3 0x00f0 +#define RK3399_WIN2_DSP_INFO3 0x00f4 +#define RK3399_WIN2_DSP_ST3 0x00f8 +#define RK3399_WIN2_FADING_CTRL 0x00fc +#define RK3399_WIN3_CTRL0 0x0100 +#define RK3399_WIN3_CTRL1 0x0104 +#define RK3399_WIN3_VIR0_1 0x0108 +#define RK3399_WIN3_VIR2_3 0x010c +#define RK3399_WIN3_MST0 0x0110 +#define RK3399_WIN3_DSP_INFO0 0x0114 +#define RK3399_WIN3_DSP_ST0 0x0118 +#define RK3399_WIN3_COLOR_KEY 0x011c +#define RK3399_WIN3_MST1 0x0120 +#define RK3399_WIN3_DSP_INFO1 0x0124 +#define RK3399_WIN3_DSP_ST1 0x0128 +#define RK3399_WIN3_SRC_ALPHA_CTRL 0x012c +#define RK3399_WIN3_MST2 0x0130 +#define RK3399_WIN3_DSP_INFO2 0x0134 +#define RK3399_WIN3_DSP_ST2 0x0138 +#define RK3399_WIN3_DST_ALPHA_CTRL 0x013c +#define RK3399_WIN3_MST3 0x0140 +#define RK3399_WIN3_DSP_INFO3 0x0144 +#define RK3399_WIN3_DSP_ST3 0x0148 +#define RK3399_WIN3_FADING_CTRL 0x014c +#define RK3399_HWC_CTRL0 0x0150 +#define RK3399_HWC_CTRL1 0x0154 +#define RK3399_HWC_MST 0x0158 +#define RK3399_HWC_DSP_ST 0x015c +#define RK3399_HWC_SRC_ALPHA_CTRL 0x0160 +#define RK3399_HWC_DST_ALPHA_CTRL 0x0164 +#define RK3399_HWC_FADING_CTRL 0x0168 +#define RK3399_HWC_RESERVED1 0x016c +#define RK3399_POST_DSP_HACT_INFO 0x0170 +#define RK3399_POST_DSP_VACT_INFO 0x0174 +#define RK3399_POST_SCL_FACTOR_YRGB 0x0178 +#define RK3399_POST_RESERVED 0x017c +#define RK3399_POST_SCL_CTRL 0x0180 +#define RK3399_POST_DSP_VACT_INFO_F1 0x0184 +#define RK3399_DSP_HTOTAL_HS_END 0x0188 +#define RK3399_DSP_HACT_ST_END 0x018c +#define RK3399_DSP_VTOTAL_VS_END 0x0190 +#define RK3399_DSP_VACT_ST_END 0x0194 +#define RK3399_DSP_VS_ST_END_F1 0x0198 +#define RK3399_DSP_VACT_ST_END_F1 0x019c +#define RK3399_PWM_CTRL 0x01a0 +#define RK3399_PWM_PERIOD_HPR 0x01a4 +#define RK3399_PWM_DUTY_LPR 0x01a8 +#define RK3399_PWM_CNT 0x01ac +#define RK3399_BCSH_COLOR_BAR 0x01b0 +#define RK3399_BCSH_BCS 0x01b4 +#define RK3399_BCSH_H 0x01b8 +#define RK3399_BCSH_CTRL 0x01bc +#define RK3399_CABC_CTRL0 0x01c0 +#define RK3399_CABC_CTRL1 0x01c4 +#define RK3399_CABC_CTRL2 0x01c8 +#define RK3399_CABC_CTRL3 0x01cc +#define RK3399_CABC_GAUSS_LINE0_0 0x01d0 +#define RK3399_CABC_GAUSS_LINE0_1 0x01d4 +#define RK3399_CABC_GAUSS_LINE1_0 0x01d8 +#define RK3399_CABC_GAUSS_LINE1_1 0x01dc +#define RK3399_CABC_GAUSS_LINE2_0 0x01e0 +#define RK3399_CABC_GAUSS_LINE2_1 0x01e4 +#define RK3399_FRC_LOWER01_0 0x01e8 +#define RK3399_FRC_LOWER01_1 0x01ec +#define RK3399_FRC_LOWER10_0 0x01f0 +#define RK3399_FRC_LOWER10_1 0x01f4 +#define RK3399_FRC_LOWER11_0 0x01f8 +#define RK3399_FRC_LOWER11_1 0x01fc +#define RK3399_AFBCD0_CTRL 0x0200 +#define RK3399_AFBCD0_HDR_PTR 0x0204 +#define RK3399_AFBCD0_PIC_SIZE 0x0208 +#define RK3399_AFBCD0_STATUS 0x020c +#define RK3399_AFBCD1_CTRL 0x0220 +#define RK3399_AFBCD1_HDR_PTR 0x0224 +#define RK3399_AFBCD1_PIC_SIZE 0x0228 +#define RK3399_AFBCD1_STATUS 0x022c +#define RK3399_AFBCD2_CTRL 0x0240 +#define RK3399_AFBCD2_HDR_PTR 0x0244 +#define RK3399_AFBCD2_PIC_SIZE 0x0248 +#define RK3399_AFBCD2_STATUS 0x024c +#define RK3399_AFBCD3_CTRL 0x0260 +#define RK3399_AFBCD3_HDR_PTR 0x0264 +#define RK3399_AFBCD3_PIC_SIZE 0x0268 +#define RK3399_AFBCD3_STATUS 0x026c +#define RK3399_INTR_EN0 0x0280 +#define RK3399_INTR_CLEAR0 0x0284 +#define RK3399_INTR_STATUS0 0x0288 +#define RK3399_INTR_RAW_STATUS0 0x028c +#define RK3399_INTR_EN1 0x0290 +#define RK3399_INTR_CLEAR1 0x0294 +#define RK3399_INTR_STATUS1 0x0298 +#define RK3399_INTR_RAW_STATUS1 0x029c +#define RK3399_LINE_FLAG 0x02a0 +#define RK3399_VOP_STATUS 0x02a4 +#define RK3399_BLANKING_VALUE 0x02a8 +#define RK3399_MCU_BYPASS_PORT 0x02ac +#define RK3399_WIN0_DSP_BG 0x02b0 +#define RK3399_WIN1_DSP_BG 0x02b4 +#define RK3399_WIN2_DSP_BG 0x02b8 +#define RK3399_WIN3_DSP_BG 0x02bc +#define RK3399_YUV2YUV_WIN 0x02c0 +#define RK3399_YUV2YUV_POST 0x02c4 +#define RK3399_AUTO_GATING_EN 0x02cc +#define RK3399_WIN0_CSC_COE 0x03a0 +#define RK3399_WIN1_CSC_COE 0x03c0 +#define RK3399_WIN2_CSC_COE 0x03e0 +#define RK3399_WIN3_CSC_COE 0x0400 +#define RK3399_HWC_CSC_COE 0x0420 +#define RK3399_BCSH_R2Y_CSC_COE 0x0440 +#define RK3399_BCSH_Y2R_CSC_COE 0x0460 +#define RK3399_POST_YUV2YUV_Y2R_COE 0x0480 +#define RK3399_POST_YUV2YUV_3X3_COE 0x04a0 +#define RK3399_POST_YUV2YUV_R2Y_COE 0x04c0 +#define RK3399_WIN0_YUV2YUV_Y2R 0x04e0 +#define RK3399_WIN0_YUV2YUV_3X3 0x0500 +#define RK3399_WIN0_YUV2YUV_R2Y 0x0520 +#define RK3399_WIN1_YUV2YUV_Y2R 0x0540 +#define RK3399_WIN1_YUV2YUV_3X3 0x0560 +#define RK3399_WIN1_YUV2YUV_R2Y 0x0580 +#define RK3399_WIN2_YUV2YUV_Y2R 0x05a0 +#define RK3399_WIN2_YUV2YUV_3X3 0x05c0 +#define RK3399_WIN2_YUV2YUV_R2Y 0x05e0 +#define RK3399_WIN3_YUV2YUV_Y2R 0x0600 +#define RK3399_WIN3_YUV2YUV_3X3 0x0620 +#define RK3399_WIN3_YUV2YUV_R2Y 0x0640 +#define RK3399_WIN2_LUT_ADDR 0x1000 +#define RK3399_WIN3_LUT_ADDR 0x1400 +#define RK3399_HWC_LUT_ADDR 0x1800 +#define RK3399_CABC_GAMMA_LUT_ADDR 0x1c00 +#define RK3399_GAMMA_LUT_ADDR 0x2000 +/* rk3399 register definition end */ + +/* rk3328 register definition end */ +#define RK3328_REG_CFG_DONE 0x00000000 +#define RK3328_VERSION_INFO 0x00000004 +#define RK3328_SYS_CTRL 0x00000008 +#define RK3328_SYS_CTRL1 0x0000000c +#define RK3328_DSP_CTRL0 0x00000010 +#define RK3328_DSP_CTRL1 0x00000014 +#define RK3328_DSP_BG 0x00000018 +#define RK3328_AUTO_GATING_EN 0x0000003c +#define RK3328_LINE_FLAG 0x00000040 +#define RK3328_VOP_STATUS 0x00000044 +#define RK3328_BLANKING_VALUE 0x00000048 +#define RK3328_WIN0_DSP_BG 0x00000050 +#define RK3328_WIN1_DSP_BG 0x00000054 +#define RK3328_DBG_PERF_LATENCY_CTRL0 0x000000c0 +#define RK3328_DBG_PERF_RD_MAX_LATENCY_NUM0 0x000000c4 +#define RK3328_DBG_PERF_RD_LATENCY_THR_NUM0 0x000000c8 +#define RK3328_DBG_PERF_RD_LATENCY_SAMP_NUM0 0x000000cc +#define RK3328_INTR_EN0 0x000000e0 +#define RK3328_INTR_CLEAR0 0x000000e4 +#define RK3328_INTR_STATUS0 0x000000e8 +#define RK3328_INTR_RAW_STATUS0 0x000000ec +#define RK3328_INTR_EN1 0x000000f0 +#define RK3328_INTR_CLEAR1 0x000000f4 +#define RK3328_INTR_STATUS1 0x000000f8 +#define RK3328_INTR_RAW_STATUS1 0x000000fc +#define RK3328_WIN0_CTRL0 0x00000100 +#define RK3328_WIN0_CTRL1 0x00000104 +#define RK3328_WIN0_COLOR_KEY 0x00000108 +#define RK3328_WIN0_VIR 0x0000010c +#define RK3328_WIN0_YRGB_MST 0x00000110 +#define RK3328_WIN0_CBR_MST 0x00000114 +#define RK3328_WIN0_ACT_INFO 0x00000118 +#define RK3328_WIN0_DSP_INFO 0x0000011c +#define RK3328_WIN0_DSP_ST 0x00000120 +#define RK3328_WIN0_SCL_FACTOR_YRGB 0x00000124 +#define RK3328_WIN0_SCL_FACTOR_CBR 0x00000128 +#define RK3328_WIN0_SCL_OFFSET 0x0000012c +#define RK3328_WIN0_SRC_ALPHA_CTRL 0x00000130 +#define RK3328_WIN0_DST_ALPHA_CTRL 0x00000134 +#define RK3328_WIN0_FADING_CTRL 0x00000138 +#define RK3328_WIN0_CTRL2 0x0000013c +#define RK3328_DBG_WIN0_REG0 0x000001f0 +#define RK3328_DBG_WIN0_REG1 0x000001f4 +#define RK3328_DBG_WIN0_REG2 0x000001f8 +#define RK3328_DBG_WIN0_RESERVED 0x000001fc +#define RK3328_WIN1_CTRL0 0x00000200 +#define RK3328_WIN1_CTRL1 0x00000204 +#define RK3328_WIN1_COLOR_KEY 0x00000208 +#define RK3328_WIN1_VIR 0x0000020c +#define RK3328_WIN1_YRGB_MST 0x00000210 +#define RK3328_WIN1_CBR_MST 0x00000214 +#define RK3328_WIN1_ACT_INFO 0x00000218 +#define RK3328_WIN1_DSP_INFO 0x0000021c +#define RK3328_WIN1_DSP_ST 0x00000220 +#define RK3328_WIN1_SCL_FACTOR_YRGB 0x00000224 +#define RK3328_WIN1_SCL_FACTOR_CBR 0x00000228 +#define RK3328_WIN1_SCL_OFFSET 0x0000022c +#define RK3328_WIN1_SRC_ALPHA_CTRL 0x00000230 +#define RK3328_WIN1_DST_ALPHA_CTRL 0x00000234 +#define RK3328_WIN1_FADING_CTRL 0x00000238 +#define RK3328_WIN1_CTRL2 0x0000023c +#define RK3328_DBG_WIN1_REG0 0x000002f0 +#define RK3328_DBG_WIN1_REG1 0x000002f4 +#define RK3328_DBG_WIN1_REG2 0x000002f8 +#define RK3328_DBG_WIN1_RESERVED 0x000002fc +#define RK3328_WIN2_CTRL0 0x00000300 +#define RK3328_WIN2_CTRL1 0x00000304 +#define RK3328_WIN2_COLOR_KEY 0x00000308 +#define RK3328_WIN2_VIR 0x0000030c +#define RK3328_WIN2_YRGB_MST 0x00000310 +#define RK3328_WIN2_CBR_MST 0x00000314 +#define RK3328_WIN2_ACT_INFO 0x00000318 +#define RK3328_WIN2_DSP_INFO 0x0000031c +#define RK3328_WIN2_DSP_ST 0x00000320 +#define RK3328_WIN2_SCL_FACTOR_YRGB 0x00000324 +#define RK3328_WIN2_SCL_FACTOR_CBR 0x00000328 +#define RK3328_WIN2_SCL_OFFSET 0x0000032c +#define RK3328_WIN2_SRC_ALPHA_CTRL 0x00000330 +#define RK3328_WIN2_DST_ALPHA_CTRL 0x00000334 +#define RK3328_WIN2_FADING_CTRL 0x00000338 +#define RK3328_WIN2_CTRL2 0x0000033c +#define RK3328_DBG_WIN2_REG0 0x000003f0 +#define RK3328_DBG_WIN2_REG1 0x000003f4 +#define RK3328_DBG_WIN2_REG2 0x000003f8 +#define RK3328_DBG_WIN2_RESERVED 0x000003fc +#define RK3328_WIN3_CTRL0 0x00000400 +#define RK3328_WIN3_CTRL1 0x00000404 +#define RK3328_WIN3_COLOR_KEY 0x00000408 +#define RK3328_WIN3_VIR 0x0000040c +#define RK3328_WIN3_YRGB_MST 0x00000410 +#define RK3328_WIN3_CBR_MST 0x00000414 +#define RK3328_WIN3_ACT_INFO 0x00000418 +#define RK3328_WIN3_DSP_INFO 0x0000041c +#define RK3328_WIN3_DSP_ST 0x00000420 +#define RK3328_WIN3_SCL_FACTOR_YRGB 0x00000424 +#define RK3328_WIN3_SCL_FACTOR_CBR 0x00000428 +#define RK3328_WIN3_SCL_OFFSET 0x0000042c +#define RK3328_WIN3_SRC_ALPHA_CTRL 0x00000430 +#define RK3328_WIN3_DST_ALPHA_CTRL 0x00000434 +#define RK3328_WIN3_FADING_CTRL 0x00000438 +#define RK3328_WIN3_CTRL2 0x0000043c +#define RK3328_DBG_WIN3_REG0 0x000004f0 +#define RK3328_DBG_WIN3_REG1 0x000004f4 +#define RK3328_DBG_WIN3_REG2 0x000004f8 +#define RK3328_DBG_WIN3_RESERVED 0x000004fc + +#define RK3328_HWC_CTRL0 0x00000500 +#define RK3328_HWC_CTRL1 0x00000504 +#define RK3328_HWC_MST 0x00000508 +#define RK3328_HWC_DSP_ST 0x0000050c +#define RK3328_HWC_SRC_ALPHA_CTRL 0x00000510 +#define RK3328_HWC_DST_ALPHA_CTRL 0x00000514 +#define RK3328_HWC_FADING_CTRL 0x00000518 +#define RK3328_HWC_RESERVED1 0x0000051c +#define RK3328_POST_DSP_HACT_INFO 0x00000600 +#define RK3328_POST_DSP_VACT_INFO 0x00000604 +#define RK3328_POST_SCL_FACTOR_YRGB 0x00000608 +#define RK3328_POST_RESERVED 0x0000060c +#define RK3328_POST_SCL_CTRL 0x00000610 +#define RK3328_POST_DSP_VACT_INFO_F1 0x00000614 +#define RK3328_DSP_HTOTAL_HS_END 0x00000618 +#define RK3328_DSP_HACT_ST_END 0x0000061c +#define RK3328_DSP_VTOTAL_VS_END 0x00000620 +#define RK3328_DSP_VACT_ST_END 0x00000624 +#define RK3328_DSP_VS_ST_END_F1 0x00000628 +#define RK3328_DSP_VACT_ST_END_F1 0x0000062c +#define RK3328_BCSH_COLOR_BAR 0x00000640 +#define RK3328_BCSH_BCS 0x00000644 +#define RK3328_BCSH_H 0x00000648 +#define RK3328_BCSH_CTRL 0x0000064c +#define RK3328_FRC_LOWER01_0 0x00000678 +#define RK3328_FRC_LOWER01_1 0x0000067c +#define RK3328_FRC_LOWER10_0 0x00000680 +#define RK3328_FRC_LOWER10_1 0x00000684 +#define RK3328_FRC_LOWER11_0 0x00000688 +#define RK3328_FRC_LOWER11_1 0x0000068c +#define RK3328_DBG_POST_REG0 0x000006e8 +#define RK3328_DBG_POST_RESERVED 0x000006ec +#define RK3328_DBG_DATAO 0x000006f0 +#define RK3328_DBG_DATAO_2 0x000006f4 + +/* sdr to hdr */ +#define RK3328_SDR2HDR_CTRL 0x00000700 +#define RK3328_EOTF_OETF_Y0 0x00000704 +#define RK3328_RESERVED0001 0x00000708 +#define RK3328_RESERVED0002 0x0000070c +#define RK3328_EOTF_OETF_Y1 0x00000710 +#define RK3328_EOTF_OETF_Y64 0x0000080c +#define RK3328_OETF_DX_DXPOW1 0x00000810 +#define RK3328_OETF_DX_DXPOW64 0x0000090c +#define RK3328_OETF_XN1 0x00000910 +#define RK3328_OETF_XN63 0x00000a08 + +/* hdr to sdr */ +#define RK3328_HDR2SDR_CTRL 0x00000a10 +#define RK3328_HDR2SDR_SRC_RANGE 0x00000a14 +#define RK3328_HDR2SDR_NORMFACEETF 0x00000a18 +#define RK3328_RESERVED0003 0x00000a1c +#define RK3328_HDR2SDR_DST_RANGE 0x00000a20 +#define RK3328_HDR2SDR_NORMFACCGAMMA 0x00000a24 +#define RK3328_EETF_OETF_Y0 0x00000a28 +#define RK3328_SAT_Y0 0x00000a2c +#define RK3328_EETF_OETF_Y1 0x00000a30 +#define RK3328_SAT_Y1 0x00000ab0 +#define RK3328_SAT_Y8 0x00000acc + +#define RK3328_HWC_LUT_ADDR 0x00000c00 + /* rk3036 register definition */ #define RK3036_SYS_CTRL 0x00 #define RK3036_DSP_CTRL0 0x04 @@ -166,197 +878,4 @@ #define RK3036_HWC_LUT_ADDR 0x800 /* rk3036 register definition end */
-/* rk3399 register definition */ -#define RK3399_REG_CFG_DONE 0x00000 -#define RK3399_VERSION_INFO 0x00004 -#define RK3399_SYS_CTRL 0x00008 -#define RK3399_SYS_CTRL1 0x0000c -#define RK3399_DSP_CTRL0 0x00010 -#define RK3399_DSP_CTRL1 0x00014 -#define RK3399_DSP_BG 0x00018 -#define RK3399_MCU_CTRL 0x0001c -#define RK3399_WB_CTRL0 0x00020 -#define RK3399_WB_CTRL1 0x00024 -#define RK3399_WB_YRGB_MST 0x00028 -#define RK3399_WB_CBR_MST 0x0002c -#define RK3399_WIN0_CTRL0 0x00030 -#define RK3399_WIN0_CTRL1 0x00034 -#define RK3399_WIN0_COLOR_KEY 0x00038 -#define RK3399_WIN0_VIR 0x0003c -#define RK3399_WIN0_YRGB_MST 0x00040 -#define RK3399_WIN0_CBR_MST 0x00044 -#define RK3399_WIN0_ACT_INFO 0x00048 -#define RK3399_WIN0_DSP_INFO 0x0004c -#define RK3399_WIN0_DSP_ST 0x00050 -#define RK3399_WIN0_SCL_FACTOR_YRGB 0x00054 -#define RK3399_WIN0_SCL_FACTOR_CBR 0x00058 -#define RK3399_WIN0_SCL_OFFSET 0x0005c -#define RK3399_WIN0_SRC_ALPHA_CTRL 0x00060 -#define RK3399_WIN0_DST_ALPHA_CTRL 0x00064 -#define RK3399_WIN0_FADING_CTRL 0x00068 -#define RK3399_WIN0_CTRL2 0x0006c -#define RK3399_WIN1_CTRL0 0x00070 -#define RK3399_WIN1_CTRL1 0x00074 -#define RK3399_WIN1_COLOR_KEY 0x00078 -#define RK3399_WIN1_VIR 0x0007c -#define RK3399_WIN1_YRGB_MST 0x00080 -#define RK3399_WIN1_CBR_MST 0x00084 -#define RK3399_WIN1_ACT_INFO 0x00088 -#define RK3399_WIN1_DSP_INFO 0x0008c -#define RK3399_WIN1_DSP_ST 0x00090 -#define RK3399_WIN1_SCL_FACTOR_YRGB 0x00094 -#define RK3399_WIN1_SCL_FACTOR_CBR 0x00098 -#define RK3399_WIN1_SCL_OFFSET 0x0009c -#define RK3399_WIN1_SRC_ALPHA_CTRL 0x000a0 -#define RK3399_WIN1_DST_ALPHA_CTRL 0x000a4 -#define RK3399_WIN1_FADING_CTRL 0x000a8 -#define RK3399_WIN1_CTRL2 0x000ac -#define RK3399_WIN2_CTRL0 0x000b0 -#define RK3399_WIN2_CTRL1 0x000b4 -#define RK3399_WIN2_VIR0_1 0x000b8 -#define RK3399_WIN2_VIR2_3 0x000bc -#define RK3399_WIN2_MST0 0x000c0 -#define RK3399_WIN2_DSP_INFO0 0x000c4 -#define RK3399_WIN2_DSP_ST0 0x000c8 -#define RK3399_WIN2_COLOR_KEY 0x000cc -#define RK3399_WIN2_MST1 0x000d0 -#define RK3399_WIN2_DSP_INFO1 0x000d4 -#define RK3399_WIN2_DSP_ST1 0x000d8 -#define RK3399_WIN2_SRC_ALPHA_CTRL 0x000dc -#define RK3399_WIN2_MST2 0x000e0 -#define RK3399_WIN2_DSP_INFO2 0x000e4 -#define RK3399_WIN2_DSP_ST2 0x000e8 -#define RK3399_WIN2_DST_ALPHA_CTRL 0x000ec -#define RK3399_WIN2_MST3 0x000f0 -#define RK3399_WIN2_DSP_INFO3 0x000f4 -#define RK3399_WIN2_DSP_ST3 0x000f8 -#define RK3399_WIN2_FADING_CTRL 0x000fc -#define RK3399_WIN3_CTRL0 0x00100 -#define RK3399_WIN3_CTRL1 0x00104 -#define RK3399_WIN3_VIR0_1 0x00108 -#define RK3399_WIN3_VIR2_3 0x0010c -#define RK3399_WIN3_MST0 0x00110 -#define RK3399_WIN3_DSP_INFO0 0x00114 -#define RK3399_WIN3_DSP_ST0 0x00118 -#define RK3399_WIN3_COLOR_KEY 0x0011c -#define RK3399_WIN3_MST1 0x00120 -#define RK3399_WIN3_DSP_INFO1 0x00124 -#define RK3399_WIN3_DSP_ST1 0x00128 -#define RK3399_WIN3_SRC_ALPHA_CTRL 0x0012c -#define RK3399_WIN3_MST2 0x00130 -#define RK3399_WIN3_DSP_INFO2 0x00134 -#define RK3399_WIN3_DSP_ST2 0x00138 -#define RK3399_WIN3_DST_ALPHA_CTRL 0x0013c -#define RK3399_WIN3_MST3 0x00140 -#define RK3399_WIN3_DSP_INFO3 0x00144 -#define RK3399_WIN3_DSP_ST3 0x00148 -#define RK3399_WIN3_FADING_CTRL 0x0014c -#define RK3399_HWC_CTRL0 0x00150 -#define RK3399_HWC_CTRL1 0x00154 -#define RK3399_HWC_MST 0x00158 -#define RK3399_HWC_DSP_ST 0x0015c -#define RK3399_HWC_SRC_ALPHA_CTRL 0x00160 -#define RK3399_HWC_DST_ALPHA_CTRL 0x00164 -#define RK3399_HWC_FADING_CTRL 0x00168 -#define RK3399_HWC_RESERVED1 0x0016c -#define RK3399_POST_DSP_HACT_INFO 0x00170 -#define RK3399_POST_DSP_VACT_INFO 0x00174 -#define RK3399_POST_SCL_FACTOR_YRGB 0x00178 -#define RK3399_POST_RESERVED 0x0017c -#define RK3399_POST_SCL_CTRL 0x00180 -#define RK3399_POST_DSP_VACT_INFO_F1 0x00184 -#define RK3399_DSP_HTOTAL_HS_END 0x00188 -#define RK3399_DSP_HACT_ST_END 0x0018c -#define RK3399_DSP_VTOTAL_VS_END 0x00190 -#define RK3399_DSP_VACT_ST_END 0x00194 -#define RK3399_DSP_VS_ST_END_F1 0x00198 -#define RK3399_DSP_VACT_ST_END_F1 0x0019c -#define RK3399_PWM_CTRL 0x001a0 -#define RK3399_PWM_PERIOD_HPR 0x001a4 -#define RK3399_PWM_DUTY_LPR 0x001a8 -#define RK3399_PWM_CNT 0x001ac -#define RK3399_BCSH_COLOR_BAR 0x001b0 -#define RK3399_BCSH_BCS 0x001b4 -#define RK3399_BCSH_H 0x001b8 -#define RK3399_BCSH_CTRL 0x001bc -#define RK3399_CABC_CTRL0 0x001c0 -#define RK3399_CABC_CTRL1 0x001c4 -#define RK3399_CABC_CTRL2 0x001c8 -#define RK3399_CABC_CTRL3 0x001cc -#define RK3399_CABC_GAUSS_LINE0_0 0x001d0 -#define RK3399_CABC_GAUSS_LINE0_1 0x001d4 -#define RK3399_CABC_GAUSS_LINE1_0 0x001d8 -#define RK3399_CABC_GAUSS_LINE1_1 0x001dc -#define RK3399_CABC_GAUSS_LINE2_0 0x001e0 -#define RK3399_CABC_GAUSS_LINE2_1 0x001e4 -#define RK3399_FRC_LOWER01_0 0x001e8 -#define RK3399_FRC_LOWER01_1 0x001ec -#define RK3399_FRC_LOWER10_0 0x001f0 -#define RK3399_FRC_LOWER10_1 0x001f4 -#define RK3399_FRC_LOWER11_0 0x001f8 -#define RK3399_FRC_LOWER11_1 0x001fc -#define RK3399_AFBCD0_CTRL 0x00200 -#define RK3399_AFBCD0_HDR_PTR 0x00204 -#define RK3399_AFBCD0_PIC_SIZE 0x00208 -#define RK3399_AFBCD0_STATUS 0x0020c -#define RK3399_AFBCD1_CTRL 0x00220 -#define RK3399_AFBCD1_HDR_PTR 0x00224 -#define RK3399_AFBCD1_PIC_SIZE 0x00228 -#define RK3399_AFBCD1_STATUS 0x0022c -#define RK3399_AFBCD2_CTRL 0x00240 -#define RK3399_AFBCD2_HDR_PTR 0x00244 -#define RK3399_AFBCD2_PIC_SIZE 0x00248 -#define RK3399_AFBCD2_STATUS 0x0024c -#define RK3399_AFBCD3_CTRL 0x00260 -#define RK3399_AFBCD3_HDR_PTR 0x00264 -#define RK3399_AFBCD3_PIC_SIZE 0x00268 -#define RK3399_AFBCD3_STATUS 0x0026c -#define RK3399_INTR_EN0 0x00280 -#define RK3399_INTR_CLEAR0 0x00284 -#define RK3399_INTR_STATUS0 0x00288 -#define RK3399_INTR_RAW_STATUS0 0x0028c -#define RK3399_INTR_EN1 0x00290 -#define RK3399_INTR_CLEAR1 0x00294 -#define RK3399_INTR_STATUS1 0x00298 -#define RK3399_INTR_RAW_STATUS1 0x0029c -#define RK3399_LINE_FLAG 0x002a0 -#define RK3399_VOP_STATUS 0x002a4 -#define RK3399_BLANKING_VALUE 0x002a8 -#define RK3399_MCU_BYPASS_PORT 0x002ac -#define RK3399_WIN0_DSP_BG 0x002b0 -#define RK3399_WIN1_DSP_BG 0x002b4 -#define RK3399_WIN2_DSP_BG 0x002b8 -#define RK3399_WIN3_DSP_BG 0x002bc -#define RK3399_YUV2YUV_WIN 0x002c0 -#define RK3399_YUV2YUV_POST 0x002c4 -#define RK3399_AUTO_GATING_EN 0x002cc -#define RK3399_WIN0_CSC_COE 0x003a0 -#define RK3399_WIN1_CSC_COE 0x003c0 -#define RK3399_WIN2_CSC_COE 0x003e0 -#define RK3399_WIN3_CSC_COE 0x00400 -#define RK3399_HWC_CSC_COE 0x00420 -#define RK3399_BCSH_R2Y_CSC_COE 0x00440 -#define RK3399_BCSH_Y2R_CSC_COE 0x00460 -#define RK3399_POST_YUV2YUV_Y2R_COE 0x00480 -#define RK3399_POST_YUV2YUV_3X3_COE 0x004a0 -#define RK3399_POST_YUV2YUV_R2Y_COE 0x004c0 -#define RK3399_WIN0_YUV2YUV_Y2R 0x004e0 -#define RK3399_WIN0_YUV2YUV_3X3 0x00500 -#define RK3399_WIN0_YUV2YUV_R2Y 0x00520 -#define RK3399_WIN1_YUV2YUV_Y2R 0x00540 -#define RK3399_WIN1_YUV2YUV_3X3 0x00560 -#define RK3399_WIN1_YUV2YUV_R2Y 0x00580 -#define RK3399_WIN2_YUV2YUV_Y2R 0x005a0 -#define RK3399_WIN2_YUV2YUV_3X3 0x005c0 -#define RK3399_WIN2_YUV2YUV_R2Y 0x005e0 -#define RK3399_WIN3_YUV2YUV_Y2R 0x00600 -#define RK3399_WIN3_YUV2YUV_3X3 0x00620 -#define RK3399_WIN3_YUV2YUV_R2Y 0x00640 -#define RK3399_WIN2_LUT_ADDR 0x01000 -#define RK3399_WIN3_LUT_ADDR 0x01400 -#define RK3399_HWC_LUT_ADDR 0x01800 -#define RK3399_CABC_GAMMA_LUT_ADDR 0x01c00 -#define RK3399_GAMMA_LUT_ADDR 0x02000 -/* rk3399 register definition end */ - #endif /* _ROCKCHIP_VOP_REG_H */
Hi mark,
On 07/26/2017 02:19 PM, Mark yao wrote:
Vop Full framework now has following vops: IP version chipname 3.1 rk3288 3.2 rk3368 3.4 rk3366 3.5 rk3399 big 3.6 rk3399 lit 3.7 rk3228 3.8 rk3328
The above IP version is from H/W define, some of vop support get the IP version from VERSION_INFO register, some are not. hardcode the IP version for each vop to identify them.
major version: used for IP structure, Vop full framework is 3, vop little framework is 2. minor version: on same structure, newer design vop will bigger then old one.
Signed-off-by: Mark Yaomark.yao@rock-chips.com
Reviewed-by: Jeffy Chen jeffy.chen@rock-chips.com
Am Mittwoch, 26. Juli 2017, 14:19:30 CEST schrieb Mark Yao:
Vop Full framework now has following vops: IP version chipname 3.1 rk3288 3.2 rk3368 3.4 rk3366 3.5 rk3399 big 3.6 rk3399 lit 3.7 rk3228 3.8 rk3328
The above IP version is from H/W define, some of vop support get the IP version from VERSION_INFO register, some are not. hardcode the IP version for each vop to identify them.
major version: used for IP structure, Vop full framework is 3, vop little framework is 2. minor version: on same structure, newer design vop will bigger then old one.
Signed-off-by: Mark Yao mark.yao@rock-chips.com
on rk3036 and rk3288 Tested-by: Heiko Stuebner heiko@sntech.de
Heiko
Signed-off-by: Mark Yao mark.yao@rock-chips.com Acked-by: Rob Herring robh@kernel.org --- Changes in v5: - clean document commit title - move changes description out of docummit commit msg
Changes in v2: - rename rk322x to rk3228 - correct some vop registers define
Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt index 9eb3f0a..5d835d9 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt @@ -8,8 +8,12 @@ Required properties: - compatible: value should be one of the following "rockchip,rk3036-vop"; "rockchip,rk3288-vop"; + "rockchip,rk3368-vop"; + "rockchip,rk3366-vop"; "rockchip,rk3399-vop-big"; "rockchip,rk3399-vop-lit"; + "rockchip,rk3228-vop"; + "rockchip,rk3328-vop";
- interrupts: should contain a list of all VOP IP block interrupts in the order: VSYNC, LCD_SYSTEM. The interrupt specifier
Hi Mark,
Am Mittwoch, 26. Juli 2017, 14:19:35 CEST schrieb Mark Yao:
Signed-off-by: Mark Yao mark.yao@rock-chips.com Acked-by: Rob Herring robh@kernel.org
Changes in v5:
- clean document commit title
- move changes description out of docummit commit msg
Changes in v2:
- rename rk322x to rk3228
- correct some vop registers define
Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt index 9eb3f0a..5d835d9 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop.txt @@ -8,8 +8,12 @@ Required properties:
- compatible: value should be one of the following "rockchip,rk3036-vop"; "rockchip,rk3288-vop";
"rockchip,rk3368-vop";"rockchip,rk3366-vop";"rockchip,rk3228-vop";"rockchip,rk3328-vop";
what is your ordering scheme here? As the number of rkXXXX socs will very likely increase in the future ordering alphanumerical might make everything more manageable when the list grows.
So maybe swap rk3368 and rk3366 and move rk3228+rk3328 to sorted positions?
Heiko
It's a hardware bug, all window's overlay channel reset value is same, hardware overlay would be die.
so we must initial difference id for each overlay channel.
The Channel register is supported on all vop will full design. Following is the details for this register VOP_WIN0_CTRL2 bit[7:4] win_rid_win0_cbr axi read id of win0 cbr channel bit[3:0] win_rid_win0_yrgb axi read id of win0 yrgb channel
Signed-off-by: Mark Yao mark.yao@rock-chips.com --- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 2 ++ drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 1 + drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 1 + 3 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 92d098b..e4b3388 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -1452,7 +1452,9 @@ static int vop_initial(struct vop *vop)
for (i = 0; i < vop_data->win_size; i++) { const struct vop_win_data *win = &vop_data->win[i]; + int channel = i * 2 + 1;
+ VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel); VOP_WIN_SET(vop, win, enable, 0); VOP_WIN_SET(vop, win, gate, 1); } diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h index 43d08c8..af1091f 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h @@ -141,6 +141,7 @@ struct vop_win_phy {
struct vop_reg dst_alpha_ctl; struct vop_reg src_alpha_ctl; + struct vop_reg channel; };
struct vop_win_data { diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index bc7b2d0..94de7b9 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -197,6 +197,7 @@ .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16), .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0), .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0), + .channel = VOP_REG(RK3288_WIN0_CTRL2, 0xff, 0), };
static const struct vop_win_phy rk3288_win23_data = {
Hi mark,
On 07/26/2017 02:19 PM, Mark yao wrote:
It's a hardware bug, all window's overlay channel reset value is same, hardware overlay would be die.
so we must initial difference id for each overlay channel.
The Channel register is supported on all vop will full design. Following is the details for this register VOP_WIN0_CTRL2 bit[7:4] win_rid_win0_cbr axi read id of win0 cbr channel bit[3:0] win_rid_win0_yrgb axi read id of win0 yrgb channel
Signed-off-by: Mark Yaomark.yao@rock-chips.com
Reviewed-by: Jeffy Chen jeffy.chen@rock-chips.com
Am Mittwoch, 26. Juli 2017, 14:19:39 CEST schrieb Mark Yao:
It's a hardware bug, all window's overlay channel reset value is same, hardware overlay would be die.
so we must initial difference id for each overlay channel.
The Channel register is supported on all vop will full design. Following is the details for this register VOP_WIN0_CTRL2 bit[7:4] win_rid_win0_cbr axi read id of win0 cbr channel bit[3:0] win_rid_win0_yrgb axi read id of win0 yrgb channel
Signed-off-by: Mark Yao mark.yao@rock-chips.com
rk3036 and rk3288 are not negatively affected by this, so on rk3036 and rk3288 Tested-by: Heiko Stuebner heiko@sntech.de
Hi
Pushed to drm-misc-next.
Thanks Sean Paul, Jeffy Chen's review, Heiko's test and Rob's ack.
Best regards.
On 2017年07月26日 14:18, Mark Yao wrote:
These patches try to make all current rockchip full framework vop works on drm, fill missing vop on full framework. Vop Full framework now has following vops: IP version chipname 3.1 rk3288 3.2 rk3368 3.4 rk3366 3.5 rk3399 big 3.6 rk3399 lit 3.7 rk3228 3.8 rk3328
Group the vop register, it would make register definition clearer and more easily to reuse same group register define for difference vops.
Tested on rk3399 excavator board with kernel 4.13-rc1.
And other chips tested on rockchip kernel 4.4: https://github.com/rockchip-linux/kernel/tree/release-4.4/drivers/gpu/drm/ro...
Changes in v6:
- fix some patches complie error
- fix rk3036 display blank
Changes in v5:
- clean document commit title
- move changes description out of docummit commit msg
Changes in v4:
- rebase to newest torvalds kernel, fix merge conflict
Changes in v3:
- group vop register instead using VOP_REG_VER mechanism
- Explain more on patch commit message
- move write_relaxed flags to vop registers
- fix rk3328 overlay abnormal
Changes in v2:
- rename rk322x to rk3228
- correct some vop registers define
Mark Yao (7): drm/rockchip: vop: initialize registers directly drm/rockchip: vop: move write_relaxed flags to vop register drm/rockchip: vop: move line_flag_num to interrupt registers drm/rockchip: vop: group vop registers drm/rockchip: vop: add a series of vop support dt-bindings: display: rockchip: fill Documents for vop series drm/rockchip: vop: rk3328: fix overlay abnormal
.../bindings/display/rockchip/rockchip-vop.txt | 4 + drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 109 ++- drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 81 +- drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 375 ++++++--- drivers/gpu/drm/rockchip/rockchip_vop_reg.h | 905 ++++++++++++++++----- 5 files changed, 1075 insertions(+), 399 deletions(-)
dri-devel@lists.freedesktop.org
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Heiko Stuebner -
Heiko Stübner
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jeffy -
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Mark yao