I used this branch qcom/arm64-for-5.6-to-be-rebased as suggested by Matthias. This patch needs the clock patches and the clock patches have not yet landed, so
please apply the following series and patches in order a) All patches from https://patchwork.kernel.org/project/linux-clk/list/?series=203517&state... b) Patches 1 and 2 from https://patchwork.kernel.org/project/linux-clk/list/?series=203527&archi... c) All patches from https://patchwork.kernel.org/project/linux-clk/list/?series=221739&archi... d) https://lore.kernel.org/linux-arm-msm/20200124144154.v2.10.I1a4b93fb005791e2... e) This patch "arm64: dts: qcom: sc7180: Add A618 gpu dt blob"
v3: Addressed review comments from previous submits. Also removed the interconnect bindings from this patch and I will submit as a new patch with its dependencies listed. Also I will be sending a new patch for updating the bindings documentation.
v4: Add GX_GDSC power domain binding for GMU
Sharat Masetty (1): arm64: dts: qcom: sc7180: Add A618 gpu dt blob
Taniya Das (2): dt-bindings: clk: qcom: Add support for GPU GX GDSCR clk: qcom: gpucc: Add support for GX GDSC for SC7180
arch/arm64/boot/dts/qcom/sc7180.dtsi | 102 ++++++++++++++++++++++++++ drivers/clk/qcom/gpucc-sc7180.c | 37 ++++++++++ include/dt-bindings/clock/qcom,gpucc-sc7180.h | 3 +- 3 files changed, 141 insertions(+), 1 deletion(-)
-- 1.9.1
From: Taniya Das tdas@codeaurora.org
In the cases where the GPU SW requires to use the GX GDSCR add support for the same.
Signed-off-by: Taniya Das tdas@codeaurora.org --- include/dt-bindings/clock/qcom,gpucc-sc7180.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/clock/qcom,gpucc-sc7180.h b/include/dt-bindings/clock/qcom,gpucc-sc7180.h index 0e4643b..65e706d 100644 --- a/include/dt-bindings/clock/qcom,gpucc-sc7180.h +++ b/include/dt-bindings/clock/qcom,gpucc-sc7180.h @@ -15,7 +15,8 @@ #define GPU_CC_CXO_CLK 6 #define GPU_CC_GMU_CLK_SRC 7
-/* CAM_CC GDSCRs */ +/* GPU_CC GDSCRs */ #define CX_GDSC 0 +#define GX_GDSC 1
#endif
Hi,
On Tue, Feb 4, 2020 at 11:01 PM Sharat Masetty smasetty@codeaurora.org wrote:
From: Taniya Das tdas@codeaurora.org
In the cases where the GPU SW requires to use the GX GDSCR add support for the same.
Signed-off-by: Taniya Das tdas@codeaurora.org
Since you are re-posting Taniya's patch you need to add your own Signed-off-by as per kernel policy.
Other than the SoB issue:
Reviewed-by: Douglas Anderson dianders@chromium.org
From: Taniya Das tdas@codeaurora.org
Most of the time the CPU should not be touching the GX domain on the GPU except for a very special use case when the CPU needs to force the GX headswitch off. Add a dummy enable function for the GX gdsc to simulate success so that the pm_runtime reference counting is correct.
Signed-off-by: Taniya Das tdas@codeaurora.org --- drivers/clk/qcom/gpucc-sc7180.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+)
diff --git a/drivers/clk/qcom/gpucc-sc7180.c b/drivers/clk/qcom/gpucc-sc7180.c index ec61194..3b29f19 100644 --- a/drivers/clk/qcom/gpucc-sc7180.c +++ b/drivers/clk/qcom/gpucc-sc7180.c @@ -172,8 +172,45 @@ enum { .flags = VOTABLE, };
+/* + * On SC7180 the GPU GX domain is *almost* entirely controlled by the GMU + * running in the CX domain so the CPU doesn't need to know anything about the + * GX domain EXCEPT.... + * + * Hardware constraints dictate that the GX be powered down before the CX. If + * the GMU crashes it could leave the GX on. In order to successfully bring back + * the device the CPU needs to disable the GX headswitch. There being no sane + * way to reach in and touch that register from deep inside the GPU driver we + * need to set up the infrastructure to be able to ensure that the GPU can + * ensure that the GX is off during this super special case. We do this by + * defining a GX gdsc with a dummy enable function and a "default" disable + * function. + * + * This allows us to attach with genpd_dev_pm_attach_by_name() in the GPU + * driver. During power up, nothing will happen from the CPU (and the GMU will + * power up normally but during power down this will ensure that the GX domain + * is *really* off - this gives us a semi standard way of doing what we need. + */ +static int gx_gdsc_enable(struct generic_pm_domain *domain) +{ + /* Do nothing but give genpd the impression that we were successful */ + return 0; +} + +static struct gdsc gx_gdsc = { + .gdscr = 0x100c, + .clamp_io_ctrl = 0x1508, + .pd = { + .name = "gpu_gx_gdsc", + .power_on = gx_gdsc_enable, + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = CLAMP_IO, +}; + static struct gdsc *gpu_cc_sc7180_gdscs[] = { [CX_GDSC] = &cx_gdsc, + [GX_GDSC] = &gx_gdsc, };
static struct clk_regmap *gpu_cc_sc7180_clocks[] = {
Hi,
On Tue, Feb 4, 2020 at 11:02 PM Sharat Masetty smasetty@codeaurora.org wrote:
From: Taniya Das tdas@codeaurora.org
Most of the time the CPU should not be touching the GX domain on the GPU except for a very special use case when the CPU needs to force the GX
Really weird word-wrapping? You've also indented your whole commit message?
headswitch off. Add a dummy enable function for the GX gdsc to simulate success so that the pm_runtime reference counting is correct.
Overall the commit message sounds a lot like the message in commit 85a3d920d30a ("clk: qcom: Add a dummy enable function for GX gdsc"). That's fine for the most part, but it makes it sound like you're _only_ adding the dummy enable. In this case you're adding support for the GX domain and _also_ adding a dummy enable. Maybe try:
Most of the time the CPU should not be touching the GX domain on the GPU except for a very special use case when the CPU needs to force the GX headswitch off. Add the GX domain for that use case. As part of this add a dummy enable function for the GX gdsc to simulate success so that the pm_runtime reference counting is correct. This matches what was done in sdm845 in commit 85a3d920d30a ("clk: qcom: Add a dummy enable function for GX gdsc").
Signed-off-by: Taniya Das tdas@codeaurora.org
Since you are re-posting Taniya's patch you need to add your own Signed-off-by as per kernel policy.
drivers/clk/qcom/gpucc-sc7180.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+)
diff --git a/drivers/clk/qcom/gpucc-sc7180.c b/drivers/clk/qcom/gpucc-sc7180.c index ec61194..3b29f19 100644 --- a/drivers/clk/qcom/gpucc-sc7180.c +++ b/drivers/clk/qcom/gpucc-sc7180.c @@ -172,8 +172,45 @@ enum { .flags = VOTABLE, };
+/*
- On SC7180 the GPU GX domain is *almost* entirely controlled by the GMU
- running in the CX domain so the CPU doesn't need to know anything about the
- GX domain EXCEPT....
- Hardware constraints dictate that the GX be powered down before the CX. If
- the GMU crashes it could leave the GX on. In order to successfully bring back
- the device the CPU needs to disable the GX headswitch. There being no sane
- way to reach in and touch that register from deep inside the GPU driver we
- need to set up the infrastructure to be able to ensure that the GPU can
- ensure that the GX is off during this super special case. We do this by
- defining a GX gdsc with a dummy enable function and a "default" disable
- function.
- This allows us to attach with genpd_dev_pm_attach_by_name() in the GPU
- driver. During power up, nothing will happen from the CPU (and the GMU will
- power up normally but during power down this will ensure that the GX domain
- is *really* off - this gives us a semi standard way of doing what we need.
- */
+static int gx_gdsc_enable(struct generic_pm_domain *domain) +{
/* Do nothing but give genpd the impression that we were successful */return 0;+}
+static struct gdsc gx_gdsc = {
.gdscr = 0x100c,.clamp_io_ctrl = 0x1508,.pd = {.name = "gpu_gx_gdsc",
nit: technically name could be "gx_gdsc" to match the name of the struct and #define. Your name is copied from sdm845 and matches the name of the struct and #define from there.
.power_on = gx_gdsc_enable,},.pwrsts = PWRSTS_OFF_ON,.flags = CLAMP_IO,
Compared to sdm845, you have different flags. There we have:
.flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR,
I'm not sure I have enough background knowledge about the hardare to figure this out. Can you confirm that you're different than sdm845 on purpose? Bonus points if you can confirm whether sdm845 is also correct as it is today or should be changed to match what you have?
+};
static struct gdsc *gpu_cc_sc7180_gdscs[] = { [CX_GDSC] = &cx_gdsc,
[GX_GDSC] = &gx_gdsc,};
Assuming that the question on flags is resolved and the commit message updated, feel free to add my Reviewed-by tag.
-Doug
This patch adds the required dt nodes and properties to enabled A618 GPU.
Signed-off-by: Sharat Masetty smasetty@codeaurora.org --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 102 +++++++++++++++++++++++++++++++++++ 1 file changed, 102 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index f3fcc5c..63fff15 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1043,6 +1043,108 @@ }; };
+ gpu: gpu@5000000 { + compatible = "qcom,adreno-618.0", "qcom,adreno"; + #stream-id-cells = <16>; + reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>, + <0 0x05061000 0 0x800>; + reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&adreno_smmu 0>; + operating-points-v2 = <&gpu_opp_table>; + qcom,gmu = <&gmu>; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; + }; + + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + }; + + opp-565000000 { + opp-hz = /bits/ 64 <565000000>; + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + }; + + opp-430000000 { + opp-hz = /bits/ 64 <430000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + }; + + opp-355000000 { + opp-hz = /bits/ 64 <355000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + + opp-267000000 { + opp-hz = /bits/ 64 <267000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + }; + + opp-180000000 { + opp-hz = /bits/ 64 <180000000>; + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; + }; + }; + }; + + adreno_smmu: iommu@5040000 { + compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2"; + reg = <0 0x05040000 0 0x10000>; + #iommu-cells = <1>; + #global-interrupts = <2>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_CFG_AHB_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>; + + clock-names = "bus", "iface", "mem_iface_clk"; + power-domains = <&gpucc CX_GDSC>; + }; + + gmu: gmu@506a000 { + compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; + reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>, + <0 0x0b490000 0 0x10000>; + reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hfi", "gmu"; + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "gmu", "cxo", "axi", "memnoc"; + power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>; + power-domain-names = "cx", "gx"; + iommus = <&adreno_smmu 5>; + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; + }; + }; + }; + gpucc: clock-controller@5090000 { compatible = "qcom,sc7180-gpucc"; reg = <0 0x05090000 0 0x9000>;
Hi,
On Tue, Feb 4, 2020 at 11:02 PM Sharat Masetty smasetty@codeaurora.org wrote:
This patch adds the required dt nodes and properties to enabled A618 GPU.
Signed-off-by: Sharat Masetty smasetty@codeaurora.org
arch/arm64/boot/dts/qcom/sc7180.dtsi | 102 +++++++++++++++++++++++++++++++++++ 1 file changed, 102 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index f3fcc5c..63fff15 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1043,6 +1043,108 @@ }; };
gpu: gpu@5000000 {compatible = "qcom,adreno-618.0", "qcom,adreno";#stream-id-cells = <16>;reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>,<0 0x05061000 0 0x800>;reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;iommus = <&adreno_smmu 0>;operating-points-v2 = <&gpu_opp_table>;qcom,gmu = <&gmu>;gpu_opp_table: opp-table {compatible = "operating-points-v2";opp-800000000 {opp-hz = /bits/ 64 <800000000>;opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;};opp-650000000 {opp-hz = /bits/ 64 <650000000>;opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;};opp-565000000 {opp-hz = /bits/ 64 <565000000>;opp-level = <RPMH_REGULATOR_LEVEL_NOM>;};opp-430000000 {opp-hz = /bits/ 64 <430000000>;opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;};opp-355000000 {opp-hz = /bits/ 64 <355000000>;opp-level = <RPMH_REGULATOR_LEVEL_SVS>;};opp-267000000 {opp-hz = /bits/ 64 <267000000>;opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;};opp-180000000 {opp-hz = /bits/ 64 <180000000>;opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;};};};adreno_smmu: iommu@5040000 {compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2";
As per prior discussion "qcom,sc7180-smmu-v2" needs to be added to the bindings.
reg = <0 0x05040000 0 0x10000>;#iommu-cells = <1>;#global-interrupts = <2>;interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,<GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,<GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,<GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,<GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,<GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,<GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,<GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,<&gcc GCC_GPU_CFG_AHB_CLK>,<&gcc GCC_DDRSS_GPU_AXI_CLK>;clock-names = "bus", "iface", "mem_iface_clk";
As per discussion in v3 [1], "mem_iface_clk" is new and needs to be added to the bindings. Presumably that patch should be posted / Acked by Rob before we land this dts.
Other than relying on un-posted bindings, this looks sane to me and this patch lets me bring the GPU up on my sc7180-based board.
Reviewed-by: Douglas Anderson dianders@chromium.org Tested-by: Douglas Anderson dianders@chromium.org
-Doug
[1] https://lore.kernel.org/r/1e29097cc1cdf18671379f6420f872b0@codeaurora.org
Hi,
On Tue, Feb 4, 2020 at 11:02 PM Sharat Masetty smasetty@codeaurora.org wrote:
power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;
I should note that this is going to be a PITA to land because the patch adding "GX_GDSC" should technically land in the "clk" tree. Without extra work that's going to mean waiting for a full Linux release before Bjorn and Andy can land. It might be worth sticking the hardcoded "1" in for now instead of "GX_GDSC". That's what we often do in cases like this.
-Doug
On Wed 05 Feb 11:24 PST 2020, Doug Anderson wrote:
Hi,
On Tue, Feb 4, 2020 at 11:02 PM Sharat Masetty smasetty@codeaurora.org wrote:
power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;I should note that this is going to be a PITA to land because the patch adding "GX_GDSC" should technically land in the "clk" tree. Without extra work that's going to mean waiting for a full Linux release before Bjorn and Andy can land. It might be worth sticking the hardcoded "1" in for now instead of "GX_GDSC". That's what we often do in cases like this.
I'm fine with the patches using the GX_GDSC define and I will replace it if necessary when applying the patch - but either way we this is dependent on the clock tree picking up the patch that defines the value.
Regards, Bjorn
dri-devel@lists.freedesktop.org
-
Bjorn Andersson -
Doug Anderson -
Sharat Masetty