sun4i_tcon0_mode_set_cpu() currently accepts struct mipi_dsi_device * as its second parameter. This is derived from drm_encoder.

The DSI encoder is tied to the CPU interface mode of the TCON as a special case. In theory, if hardware were available, we could also support normal CPU interface modes. It is better to pass the generic encoder instead of the specialized mipi_dsi_device, and handle the differences inside the function.

Passing the encoder would also enable the function to pass it, or any other data structures related to it, to other functions expecting it. One such example would be dithering support that will be added in a later patch, which looks at properties tied to the connector to determine whether dithering should be enabled or not.

Signed-off-by: Chen-Yu Tsai wens@csie.org --- drivers/gpu/drm/sun4i/sun4i_tcon.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c index 08747fc3ee71..2bd53ef7d4b8 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c @@ -277,9 +277,12 @@ static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon, }

static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon, - struct mipi_dsi_device *device, + struct drm_encoder *encoder, const struct drm_display_mode *mode) { + /* TODO support normal CPU interface modes */ + struct sun6i_dsi *dsi = encoder_to_sun6i_dsi(encoder); + struct mipi_dsi_device *device = dsi->device; u8 bpp = mipi_dsi_pixel_format_to_bpp(device->format); u8 lanes = device->lanes; u32 block_space, start_delay; @@ -606,16 +609,10 @@ void sun4i_tcon_mode_set(struct sun4i_tcon *tcon, const struct drm_encoder *encoder, const struct drm_display_mode *mode) { - struct sun6i_dsi *dsi; - switch (encoder->encoder_type) { case DRM_MODE_ENCODER_DSI: - /* - * This is not really elegant, but it's the "cleaner" - * way I could think of... - */ - dsi = encoder_to_sun6i_dsi(encoder); - sun4i_tcon0_mode_set_cpu(tcon, dsi->device, mode); + /* DSI is tied to special case of CPU interface */ + sun4i_tcon0_mode_set_cpu(tcon, encoder, mode); break; case DRM_MODE_ENCODER_LVDS: sun4i_tcon0_mode_set_lvds(tcon, encoder, mode);

From: Jonathan Liu net147@gmail.com

The hardware supports dithering on TCON channel 0 which is used for LCD panels.

Dithering is a method of approximating a color from a mixture of other colors when the required color isn't available. It reduces color banding artifacts that can be observed when displaying gradients (e.g. grayscale gradients). This may occur when the image that needs to be displayed is 24-bit but the LCD panel is a lower bit depth and does not perform dithering on its own.

Signed-off-by: Jonathan Liu net147@gmail.com [wens@csie.org: check display_info.bpc first; handle LVDS and MIPI DSI] Signed-off-by: Chen-Yu Tsai wens@csie.org ---

Hi Maxime,

The dithering parameters used here are different from the ones you used in your MIPI DSI series. You might want to check if it still works for you.

--- drivers/gpu/drm/sun4i/sun4i_tcon.c | 63 +++++++++++++++++++++++++++++- 1 file changed, 62 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c index 2bd53ef7d4b8..827518f4790e 100644 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c @@ -12,6 +12,7 @@

#include <drm/drmP.h> #include <drm/drm_atomic_helper.h> +#include <drm/drm_connector.h> #include <drm/drm_crtc.h> #include <drm/drm_crtc_helper.h> #include <drm/drm_encoder.h> @@ -276,8 +277,59 @@ static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon, SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay)); }

+static void sun4i_tcon0_mode_set_dithering(struct sun4i_tcon *tcon, + const struct drm_connector *connector) +{ + u32 bus_format = 0; + u32 val = 0; + + /* XXX Would this ever happen? */ + if (!connector) + return; + + /* + * FIXME: Undocumented bits + * + * The whole dithering process and these parameters are not + * explained in the vendor documents or BSP kernel code. + */ + regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PR_REG, 0x11111111); + regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PG_REG, 0x11111111); + regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PB_REG, 0x11111111); + regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LR_REG, 0x11111111); + regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LG_REG, 0x11111111); + regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LB_REG, 0x11111111); + regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL0_REG, 0x01010000); + regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL1_REG, 0x15151111); + regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL2_REG, 0x57575555); + regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL3_REG, 0x7f7f7777); + + /* Do dithering if panel only supports 6 bits per color */ + if (connector->display_info.bpc == 6) + val |= SUN4I_TCON0_FRM_CTL_EN; + + if (connector->display_info.num_bus_formats == 1) + bus_format = connector->display_info.bus_formats[0]; + + /* Check the connection format */ + switch (bus_format) { + case MEDIA_BUS_FMT_RGB565_1X16: + /* R and B components are only 5 bits deep */ + val |= SUN4I_TCON0_FRM_CTL_MODE_R; + val |= SUN4I_TCON0_FRM_CTL_MODE_B; + case MEDIA_BUS_FMT_RGB666_1X18: + case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: + /* Fall through: enable dithering */ + val |= SUN4I_TCON0_FRM_CTL_EN; + break; + } + + /* Write dithering settings */ + regmap_write(tcon->regs, SUN4I_TCON_FRM_CTL_REG, val); +} + static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon, - struct drm_encoder *encoder, + const struct drm_encoder *encoder, const struct drm_display_mode *mode) { /* TODO support normal CPU interface modes */ @@ -293,6 +345,9 @@ static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon,

sun4i_tcon0_mode_set_common(tcon, mode);

+ /* Set dithering if needed */ + sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder)); + regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, SUN4I_TCON0_CTL_IF_MASK, SUN4I_TCON0_CTL_IF_8080); @@ -358,6 +413,9 @@ static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon, tcon->dclk_max_div = 7; sun4i_tcon0_mode_set_common(tcon, mode);

+ /* Set dithering if needed */ + sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder)); + /* Adjust clock delay */ clk_delay = sun4i_tcon_get_clk_delay(mode, 0); regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, @@ -434,6 +492,9 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon, tcon->dclk_max_div = 127; sun4i_tcon0_mode_set_common(tcon, mode);

+ /* Set dithering if needed */ + sun4i_tcon0_mode_set_dithering(tcon, tcon->panel->connector); + /* Adjust clock delay */ clk_delay = sun4i_tcon_get_clk_delay(mode, 0); regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,

This panel is marketed as Banana Pi 7" LCD display. On the back is a sticker denoting the model name S070WV20-CT16.

This is a 7" 800x480 panel connected through a 24-bit RGB interface. However the panel only does 262k colors.

Signed-off-by: Chen-Yu Tsai wens@csie.org --- .../display/panel/bananapi,s070wv20-ct16.txt | 7 ++++++ drivers/gpu/drm/panel/panel-simple.c | 25 +++++++++++++++++++ 2 files changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/bananapi,s070wv20-ct16.txt

diff --git a/Documentation/devicetree/bindings/display/panel/bananapi,s070wv20-ct16.txt b/Documentation/devicetree/bindings/display/panel/bananapi,s070wv20-ct16.txt new file mode 100644 index 000000000000..2ec35ce36e9a --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/bananapi,s070wv20-ct16.txt @@ -0,0 +1,7 @@ +Banana Pi 7" (S070WV20-CT16) TFT LCD Panel + +Required properties: +- compatible: should be "bananapi,s070wv20-ct16" + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index cbf1ab404ee7..9bc037f74d6c 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -745,6 +745,28 @@ static const struct panel_desc avic_tm070ddh03 = { }, };

+static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { + .clock = 30000, + .hdisplay = 800, + .hsync_start = 800 + 40, + .hsync_end = 800 + 40 + 48, + .htotal = 800 + 40 + 48 + 40, + .vdisplay = 480, + .vsync_start = 480 + 13, + .vsync_end = 480 + 13 + 3, + .vtotal = 480 + 13 + 3 + 29, +}; + +static const struct panel_desc bananapi_s070wv20_ct16 = { + .modes = &bananapi_s070wv20_ct16_mode, + .num_modes = 1, + .bpc = 6, + .size = { + .width = 154, + .height = 86, + }, +}; + static const struct drm_display_mode boe_nv101wxmn51_modes[] = { { .clock = 71900, @@ -2112,6 +2134,9 @@ static const struct of_device_id platform_of_match[] = { }, { .compatible = "avic,tm070ddh03", .data = &avic_tm070ddh03, + }, { + .compatible = "bananapi,s070wv20-ct16", + .data = &bananapi_s070wv20_ct16, }, { .compatible = "boe,nv101wxmn51", .data = &boe_nv101wxmn51,

The BPI-M1+ has an FPC connector for connecting an RGB (parallel) or LVDS LCD panel. One of the compatible panels is a 7" 800x480 RGB panel from Bananapi. The backlight can be controlled by driving a PWM signal from the SoC at different duty cycles. The LCD enable pin does not seem to do anything, but it is nevertheless included for completeness. There is also a FT5306 capacitive touchscreen controller.

This should not be confused with the other 7" LCD that is LVDS based and has a resolution of 1024x600.

This patch enables all of the above for the BPI-M1+.

Signed-off-by: Chen-Yu Tsai wens@csie.org --- .../boot/dts/sun7i-a20-bananapi-m1-plus.dts | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+)

diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts index 763cb03033c4..58a923bfa6ef 100644 --- a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts +++ b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts @@ -47,6 +47,7 @@ #include "sunxi-common-regulators.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/pwm/pwm.h>

/ { model = "Banana Pi BPI-M1-Plus"; @@ -71,6 +72,34 @@ }; };

+ lcd_backlight: lcd-backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 20000 PWM_POLARITY_INVERTED>; /* 50 kHz */ + enable-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */ + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + default-brightness-level = <8>; + }; + + lcd_panel: lcd-panel { + compatible = "bananapi,s070wv20-ct16", "simple-panel"; + /* This doesn't do anything for this particular panel */ + enable-gpios = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */ + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + backlight = <&lcd_backlight>; + #address-cells = <1>; + #size-cells = <0>; + + lcd_panel_input: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_out_lcd>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -173,6 +202,20 @@ status = "okay"; };

+&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins_a>; + status = "okay"; + + touchscreen@38 { + compatible = "edt,edt-ft5306", "edt,edt-ft5x06"; + reg = <0x38>; + interrupt-parent = <&pio>; + interrupts = <7 7 IRQ_TYPE_EDGE_FALLING>; /* PH7 */ + reset-gpios = <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */ + }; +}; + &ir0 { pinctrl-names = "default"; pinctrl-0 = <&ir0_rx_pins_a>; @@ -249,6 +292,12 @@ }; };

+&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins_a>; + status = "okay"; +}; + &reg_dcdc2 { regulator-always-on; regulator-min-microvolt = <1000000>; @@ -278,6 +327,18 @@ status = "okay"; };

+&tcon0 { + pinctrl-names = "default"; + pinctrl-0 = <&lcd0_rgb888_pins>; +}; + +&tcon0_out { + tcon0_out_lcd: endpoint@0 { + reg = <0>; + remote-endpoint = <&lcd_panel_input>; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>;