On 2020-06-23 at 11:58:58 -0400, Sean Paul wrote:

From: Sean Paul seanpaul@chromium.org

Add an out label and un-indent hdcp disable in preparation for hdcp_mutex. No functional changes

Signed-off-by: Sean Paul seanpaul@chromium.org

Reviewed-by: Ramalingam C ramalingam.c@intel.com

Link: https://patchwork.freedesktop.org/patch/msgid/20200429195502.39919-9-sean@po... #v6

Changes in v7:

-Split into separate patch (Ramalingam)

drivers/gpu/drm/i915/display/intel_hdcp.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 62cab3aea745..16bf0fbe5f17 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -2113,16 +2113,17 @@ int intel_hdcp_disable(struct intel_connector *connector)

mutex_lock(&hdcp->mutex);

• if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {

• intel_hdcp_update_value(connector,
  

• 			DRM_MODE_CONTENT_PROTECTION_UNDESIRED,
  

• 			false);
  

• if (hdcp->hdcp2_encrypted)
  

• 	ret = _intel_hdcp2_disable(connector);
  

• else if (hdcp->hdcp_encrypted)
  

• 	ret = _intel_hdcp_disable(connector);
  

• }

• if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED)

• goto out;
  
  

• intel_hdcp_update_value(connector,

• 		DRM_MODE_CONTENT_PROTECTION_UNDESIRED, false);
  

• if (hdcp->hdcp2_encrypted)

• ret = _intel_hdcp2_disable(connector);
  

• else if (hdcp->hdcp_encrypted)

• ret = _intel_hdcp_disable(connector);
  

+out: mutex_unlock(&hdcp->mutex); cancel_delayed_work_sync(&hdcp->check_work); return ret; -- Sean Paul, Software Engineer, Google / Chromium OS

On 2020-06-23 at 11:58:59 -0400, Sean Paul wrote:

From: Sean Paul seanpaul@chromium.org

This patch is required for HDCP over MST. If a port is being used for multiple HDCP streams, we don't want to fully disable HDCP on a port if one of them is disabled. Instead, we just disable the HDCP signalling on that particular pipe and exit early. The last pipe to disable HDCP will also bring down HDCP on the port.

In order to achieve this, we need to keep a refcount in intel_digital_port and protect it using a new hdcp_mutex.

Cc: Ramalingam C ramalingam.c@intel.com Signed-off-by: Sean Paul seanpaul@chromium.org Link: https://patchwork.freedesktop.org/patch/msgid/20191203173638.94919-8-sean@po... #v1 Link: https://patchwork.freedesktop.org/patch/msgid/20191212190230.188505-9-sean@p... #v2 Link: https://patchwork.freedesktop.org/patch/msgid/20200117193103.156821-9-sean@p... #v3 Link: https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-9-sean@p... #v4 Link: https://patchwork.freedesktop.org/patch/msgid/20200305201236.152307-9-sean@p... #v5 Link: https://patchwork.freedesktop.org/patch/msgid/20200429195502.39919-9-sean@po... #v6

Changes in v2: -Move the toggle_signalling call into _intel_hdcp_disable so it's called from check_work Changes in v3: -None Changes in v4: -None Changes in v5: -Change WARN_ON to drm_WARN_ON Changes in v6: -None Changes in v7:

-Split minor intel_hdcp_disable refactor into separate patch (Ramalingam)

drivers/gpu/drm/i915/display/intel_ddi.c | 3 ++ .../drm/i915/display/intel_display_types.h | 5 +++ drivers/gpu/drm/i915/display/intel_dp.c | 2 ++ drivers/gpu/drm/i915/display/intel_hdcp.c | 33 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_hdmi.c | 2 ++ 5 files changed, 45 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 4153a0d1e07d..536299f902b9 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4884,6 +4884,9 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));

• mutex_init(&intel_dig_port->hdcp_mutex);
• intel_dig_port->num_hdcp_streams = 0;
• encoder->hotplug = intel_ddi_hotplug; encoder->compute_output_type = intel_ddi_compute_output_type; encoder->compute_config = intel_ddi_compute_config;

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index fc0befd55420..1503403a808b 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1410,6 +1410,11 @@ struct intel_digital_port { enum phy_fia tc_phy_fia; u8 tc_phy_fia_idx;

• /* protects num_hdcp_streams reference count */
• struct mutex hdcp_mutex;
• /* the number of pipes using HDCP signalling out of this port */
• unsigned int num_hdcp_streams;
• void (*write_infoframe)(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, unsigned int type,

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index d0fea51f5dec..d98e45a09c28 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -8276,6 +8276,8 @@ bool intel_dp_init(struct drm_i915_private *dev_priv, intel_encoder = &intel_dig_port->base; encoder = &intel_encoder->base;

• mutex_init(&intel_dig_port->hdcp_mutex);
• if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base, &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS, "DP %c", port_name(port)))

diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 16bf0fbe5f17..5679877c6b4c 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -801,6 +801,19 @@ static int _intel_hdcp_disable(struct intel_connector *connector) drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP is being disabled...\n", connector->base.name, connector->base.base.id);

• /*

• * If there are other connectors on this port using HDCP, don't disable
  

• * it. Instead, toggle the HDCP signalling off on that particular
  

• * connector/pipe and exit.
  

• */
  

• if (intel_dig_port->num_hdcp_streams > 0) {

• ret = hdcp->shim->toggle_signalling(intel_dig_port,
  

• 				    cpu_transcoder, false);
  

Sean,

Toggling for DP SST was empty. For MST also HW spec doesn't say the bit is applicable (This bit is ignored when not in HDMI or DVI modes.)

Is there anywhere you saw this is needed for MST?

Leaving this discussion for mst shim implementation patch 17/17, and considering this function is dummy as it was for DP SST,

Reviewed-by: Ramalingam C ramalingam.c@intel.com

• if (ret)
  

• 	DRM_ERROR("Failed to disable HDCP signalling\n");
  

• return ret;
  

• }
• hdcp->hdcp_encrypted = false; intel_de_write(dev_priv, HDCP_CONF(dev_priv, cpu_transcoder, port), 0); if (intel_de_wait_for_clear(dev_priv,

@@ -880,6 +893,8 @@ static struct intel_connector *intel_hdcp_to_connector(struct intel_hdcp *hdcp) static void intel_hdcp_update_value(struct intel_connector *connector, u64 value, bool update_property) {

• struct drm_device *dev = connector->base.dev;

• struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); struct intel_hdcp *hdcp = &connector->hdcp;

  drm_WARN_ON(connector->base.dev, !mutex_is_locked(&hdcp->mutex));

@@ -887,6 +902,15 @@ static void intel_hdcp_update_value(struct intel_connector *connector, if (hdcp->value == value) return;

• drm_WARN_ON(dev, !mutex_is_locked(&intel_dig_port->hdcp_mutex));
• if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED) {

• if (!drm_WARN_ON(dev, intel_dig_port->num_hdcp_streams == 0))
  

• 	intel_dig_port->num_hdcp_streams--;
  

• } else if (value == DRM_MODE_CONTENT_PROTECTION_ENABLED) {

• intel_dig_port->num_hdcp_streams++;
  

• }
• hdcp->value = value; if (update_property) { drm_connector_get(&connector->base);

@@ -905,6 +929,8 @@ static int intel_hdcp_check_link(struct intel_connector *connector) int ret = 0;

mutex_lock(&hdcp->mutex);

• mutex_lock(&intel_dig_port->hdcp_mutex);

• cpu_transcoder = hdcp->cpu_transcoder;

  /* Check_link valid only when HDCP1.4 is enabled */

@@ -958,6 +984,7 @@ static int intel_hdcp_check_link(struct intel_connector *connector) }

out:

• mutex_unlock(&intel_dig_port->hdcp_mutex); mutex_unlock(&hdcp->mutex); return ret;

} @@ -2057,6 +2084,7 @@ int intel_hdcp_enable(struct intel_connector *connector, enum transcoder cpu_transcoder, u8 content_type) { struct drm_i915_private *dev_priv = to_i915(connector->base.dev);

• struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); struct intel_hdcp *hdcp = &connector->hdcp; unsigned long check_link_interval = DRM_HDCP_CHECK_PERIOD_MS; int ret = -EINVAL;

@@ -2065,6 +2093,7 @@ int intel_hdcp_enable(struct intel_connector *connector, return -ENOENT;

mutex_lock(&hdcp->mutex);

• mutex_lock(&intel_dig_port->hdcp_mutex); drm_WARN_ON(&dev_priv->drm, hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED); hdcp->content_type = content_type;

@@ -2099,12 +2128,14 @@ int intel_hdcp_enable(struct intel_connector *connector, true); }

• mutex_unlock(&intel_dig_port->hdcp_mutex); mutex_unlock(&hdcp->mutex); return ret;

}

int intel_hdcp_disable(struct intel_connector *connector) {

• struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); struct intel_hdcp *hdcp = &connector->hdcp; int ret = 0;

@@ -2112,6 +2143,7 @@ int intel_hdcp_disable(struct intel_connector *connector) return -ENOENT;

mutex_lock(&hdcp->mutex);

• mutex_lock(&intel_dig_port->hdcp_mutex);

  if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) goto out;

@@ -2124,6 +2156,7 @@ int intel_hdcp_disable(struct intel_connector *connector) ret = _intel_hdcp_disable(connector);

out:

• mutex_unlock(&intel_dig_port->hdcp_mutex); mutex_unlock(&hdcp->mutex); cancel_delayed_work_sync(&hdcp->check_work); return ret;

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index ab7bddf0dfdc..a59acfff456e 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -3331,6 +3331,8 @@ void intel_hdmi_init(struct drm_i915_private *dev_priv,

intel_encoder = &intel_dig_port->base;

• mutex_init(&intel_dig_port->hdcp_mutex);
• drm_encoder_init(&dev_priv->drm, &intel_encoder->base, &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS, "HDMI %c", port_name(port));

-- Sean Paul, Software Engineer, Google / Chromium OS

On 2020-06-23 at 11:59:00 -0400, Sean Paul wrote:

From: Sean Paul seanpaul@chromium.org

Although DP_MST fake encoders are not subclassed from digital ports, they are associated with them. Support these encoders.

Signed-off-by: Sean Paul seanpaul@chromium.org

Reviewed-by: Ramalingam C ramalingam.c@intel.com

Link: https://patchwork.freedesktop.org/patch/msgid/20191203173638.94919-9-sean@po... #v1 Link: https://patchwork.freedesktop.org/patch/msgid/20191212190230.188505-10-sean@... #v2 Link: https://patchwork.freedesktop.org/patch/msgid/20200117193103.156821-10-sean@... #v3 Link: https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-10-sean@... #v4 Link: https://patchwork.freedesktop.org/patch/msgid/20200305201236.152307-10-sean@... #v5 Link: https://patchwork.freedesktop.org/patch/msgid/20200429195502.39919-10-sean@p... #v6

Changes in v2: -None Changes in v3: -None Changes in v4: -None Changes in v5: -None Changes in v6: -None Changes in v7:

-None

.../drm/i915/display/intel_display_types.h | 21 ++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 1503403a808b..811085ef3fba 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1525,6 +1525,18 @@ static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder) } }

+static inline bool intel_encoder_is_mst(struct intel_encoder *encoder) +{

• return encoder->type == INTEL_OUTPUT_DP_MST;

+}

+static inline struct intel_dp_mst_encoder * +enc_to_mst(struct intel_encoder *encoder) +{

• return container_of(&encoder->base, struct intel_dp_mst_encoder,

• 	    base.base);
  

+}

static inline struct intel_digital_port * enc_to_dig_port(struct intel_encoder *encoder) { @@ -1533,6 +1545,8 @@ enc_to_dig_port(struct intel_encoder *encoder) if (intel_encoder_is_dig_port(intel_encoder)) return container_of(&encoder->base, struct intel_digital_port, base.base);

• else if (intel_encoder_is_mst(intel_encoder))

• return enc_to_mst(encoder)->primary;
  

  else return NULL;

} @@ -1543,13 +1557,6 @@ intel_attached_dig_port(struct intel_connector *connector) return enc_to_dig_port(intel_attached_encoder(connector)); }

-static inline struct intel_dp_mst_encoder * -enc_to_mst(struct intel_encoder *encoder) -{

• return container_of(&encoder->base, struct intel_dp_mst_encoder,

• 	    base.base);
  

-}

static inline struct intel_dp *enc_to_intel_dp(struct intel_encoder *encoder) { return &enc_to_dig_port(encoder)->dp; -- Sean Paul, Software Engineer, Google / Chromium OS

-----Original Message----- From: Sean Paul sean@poorly.run Sent: Tuesday, June 23, 2020 9:29 PM To: dri-devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org Cc: Li, Juston juston.li@intel.com; C, Ramalingam ramalingam.c@intel.com; ville.syrjala@linux.intel.com; jani.nikula@linux.intel.com; joonas.lahtinen@linux.intel.com; Vivi, Rodrigo rodrigo.vivi@intel.com; daniel.vetter@ffwll.ch; Sean Paul seanpaul@chromium.org Subject: [PATCH v7 11/17] drm/i915: Use ddi_update_pipe in intel_dp_mst

From: Sean Paul seanpaul@chromium.org

In order to act upon content_protection property changes, we'll need to implement the .update_pipe() hook. We can re-use intel_ddi_update_pipe for this

Signed-off-by: Sean Paul seanpaul@chromium.org

Reviewed-by: Ramalingam C ramalingam.c@intel.com

Link: https://patchwork.freedesktop.org/patch/msgid/20191203173638.94919- 10-sean@poorly.run #v1 Link: https://patchwork.freedesktop.org/patch/msgid/20191212190230.188505-11- sean@poorly.run #v2 Link: https://patchwork.freedesktop.org/patch/msgid/20200117193103.156821-11- sean@poorly.run #v3 Link: https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-11- sean@poorly.run #v4 Link: https://patchwork.freedesktop.org/patch/msgid/20200305201236.152307-11- sean@poorly.run #v5 Link: https://patchwork.freedesktop.org/patch/msgid/20200429195502.39919- 11-sean@poorly.run #v6

Changes in v2: -None Changes in v3: -None Changes in v4: -None Changes in v5: -None Changes in v6: -None Changes in v7:

-None

drivers/gpu/drm/i915/display/intel_ddi.c | 11 ++++++----- drivers/gpu/drm/i915/display/intel_dp.h | 6 ++++++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 1 + 3 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 536299f902b9..29f1f552e8d8 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3907,13 +3907,14 @@ static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, intel_panel_update_backlight(state, encoder, crtc_state, conn_state); }

-static void intel_ddi_update_pipe(struct intel_atomic_state *state,

• 		  struct intel_encoder *encoder,
  

• 		  const struct intel_crtc_state *crtc_state,
  

• 		  const struct drm_connector_state
  

*conn_state) +void intel_ddi_update_pipe(struct intel_atomic_state *state,

• 	   struct intel_encoder *encoder,
  

• 	   const struct intel_crtc_state *crtc_state,
  

• 	   const struct drm_connector_state *conn_state)
  

{

• if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

• if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&

•    !intel_encoder_is_mst(encoder))
  

  intel_ddi_update_pipe_dp(state, encoder, crtc_state, conn_state);

diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 0a8950f744f6..6352c7e97e3b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -17,6 +17,7 @@ struct drm_encoder; struct drm_i915_private; struct drm_modeset_acquire_ctx; struct drm_dp_vsc_sdp; +struct intel_atomic_state; struct intel_connector; struct intel_crtc_state; struct intel_digital_port; @@ -128,4 +129,9 @@ static inline unsigned int intel_dp_unused_lane_mask(int lane_count)

u32 intel_dp_mode_to_fec_clock(u32 mode_clock);

+void intel_ddi_update_pipe(struct intel_atomic_state *state,

• 	   struct intel_encoder *encoder,
  

• 	   const struct intel_crtc_state *crtc_state,
  

• 	   const struct drm_connector_state *conn_state);
  

#endif /* __INTEL_DP_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 9308b5920780..0675825dcc20 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -836,6 +836,7 @@ intel_dp_create_fake_mst_encoder(struct intel_digital_port *intel_dig_port, enum intel_encoder->compute_config_late = intel_dp_mst_compute_config_late; intel_encoder->disable = intel_mst_disable_dp; intel_encoder->post_disable = intel_mst_post_disable_dp;

• intel_encoder->update_pipe = intel_ddi_update_pipe; intel_encoder->pre_pll_enable = intel_mst_pre_pll_enable_dp; intel_encoder->pre_enable = intel_mst_pre_enable_dp; intel_encoder->enable = intel_mst_enable_dp;

-- Sean Paul, Software Engineer, Google / Chromium OS

-----Original Message----- From: Sean Paul sean@poorly.run Sent: Tuesday, June 23, 2020 9:29 PM To: dri-devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org Cc: Li, Juston juston.li@intel.com; C, Ramalingam ramalingam.c@intel.com; ville.syrjala@linux.intel.com; jani.nikula@linux.intel.com; joonas.lahtinen@linux.intel.com; Vivi, Rodrigo rodrigo.vivi@intel.com; daniel.vetter@ffwll.ch; Sean Paul seanpaul@chromium.org Subject: [PATCH v7 12/17] drm/i915: Factor out HDCP shim functions from dp for use by dp_mst

From: Sean Paul seanpaul@chromium.org

These functions are all the same for dp and dp_mst, so move them into a dedicated file for both sst and mst to use.

Signed-off-by: Sean Paul seanpaul@chromium.org

Reviewed-by: Ramalingam C ramalingam.c@intel.com

Link: https://patchwork.freedesktop.org/patch/msgid/20191203173638.94919- 11-sean@poorly.run #v1 Link: https://patchwork.freedesktop.org/patch/msgid/20191212190230.188505-12- sean@poorly.run #v2 Link: https://patchwork.freedesktop.org/patch/msgid/20200117193103.156821-12- sean@poorly.run #v3 Link: https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-12- sean@poorly.run #v4 Link: https://patchwork.freedesktop.org/patch/msgid/20200305201236.152307-12- sean@poorly.run #v5 Link: https://patchwork.freedesktop.org/patch/msgid/20200429195502.39919- 12-sean@poorly.run #v6

Changes in v2: -None Changes in v3: -Created intel_dp_hdcp.c for the shared functions to live (Ville) Changes in v4: -Rebased on new drm logging change Changes in v5: -None Changes in v6: -None Changes in v7:

-Rebased patch

drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 606 +----------------- drivers/gpu/drm/i915/display/intel_dp.h | 3 + drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 636 +++++++++++++++++++ 4 files changed, 641 insertions(+), 605 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_dp_hdcp.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 41a27fd5dbc7..cba4ddb95ab1 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -233,6 +233,7 @@ i915-y += \ display/intel_ddi.o \ display/intel_dp.o \ display/intel_dp_aux_backlight.o \

• display/intel_dp_hdcp.o \ display/intel_dp_link_training.o \ display/intel_dp_mst.o \ display/intel_dsi.o \

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index d98e45a09c28..78ce5e41d559 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -38,7 +38,6 @@ #include <drm/drm_crtc.h> #include <drm/drm_dp_helper.h> #include <drm/drm_edid.h> -#include <drm/drm_hdcp.h> #include <drm/drm_probe_helper.h>

#include "i915_debugfs.h" @@ -6396,609 +6395,6 @@ void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) edp_panel_vdd_off_sync(intel_dp); }

-static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout) -{

• long ret;

-#define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count))

• ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C,

• 			       msecs_to_jiffies(timeout));
  

• if (!ret)

• DRM_DEBUG_KMS("Timedout at waiting for CP_IRQ\n");
  

-}

-static -int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,

• 		u8 *an)
  

-{

• struct drm_i915_private *i915 = to_i915(intel_dig_port-

...

base.base.dev);

• u8 aksv[DRM_HDCP_KSV_LEN] = {};
• ssize_t dpcd_ret;
• dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux,

DP_AUX_HDCP_AN,

• 		     an, DRM_HDCP_AN_LEN);
  

• if (dpcd_ret != DRM_HDCP_AN_LEN) {

• drm_dbg_kms(&i915->drm,
  

• 	    "Failed to write An over DP/AUX (%zd)\n",
  

• 	    dpcd_ret);
  

• return dpcd_ret >= 0 ? -EIO : dpcd_ret;
  

• }
• /*

• * Since Aksv is Oh-So-Secret, we can't access it in software. So we
  

• * send an empty buffer of the correct length through the DP helpers. On
  

• * the other side, in the transfer hook, we'll generate a flag based on
  

• * the destination address which will tickle the hardware to output the
  

• * Aksv on our behalf after the header is sent.
  

• */
  

• dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux,

DP_AUX_HDCP_AKSV,

• 		     aksv, DRM_HDCP_KSV_LEN);
  

• if (dpcd_ret != DRM_HDCP_KSV_LEN) {

• drm_dbg_kms(&i915->drm,
  

• 	    "Failed to write Aksv over DP/AUX (%zd)\n",
  

• 	    dpcd_ret);
  

• return dpcd_ret >= 0 ? -EIO : dpcd_ret;
  

• }
• return 0;

-}

-static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,

• 		   u8 *bksv)
  

-{

• struct drm_i915_private *i915 = to_i915(intel_dig_port-

...

base.base.dev);

• ssize_t ret;
• ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,

DP_AUX_HDCP_BKSV, bksv,

• 	       DRM_HDCP_KSV_LEN);
  

• if (ret != DRM_HDCP_KSV_LEN) {

• drm_dbg_kms(&i915->drm,
  

• 	    "Read Bksv from DP/AUX failed (%zd)\n", ret);
  

• return ret >= 0 ? -EIO : ret;
  

• }
• return 0;

-}

-static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,

• 		      u8 *bstatus)
  

-{

• struct drm_i915_private *i915 = to_i915(intel_dig_port-

...

base.base.dev);

• ssize_t ret;
• /*

• * For some reason the HDMI and DP HDCP specs call this register
  

• * definition by different names. In the HDMI spec, it's called BSTATUS,
  

• * but in DP it's called BINFO.
  

• */
  

• ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,

DP_AUX_HDCP_BINFO,

• 	       bstatus, DRM_HDCP_BSTATUS_LEN);
  

• if (ret != DRM_HDCP_BSTATUS_LEN) {

• drm_dbg_kms(&i915->drm,
  

• 	    "Read bstatus from DP/AUX failed (%zd)\n", ret);
  

• return ret >= 0 ? -EIO : ret;
  

• }
• return 0;

-}

-static -int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port,

• 	     u8 *bcaps)
  

-{

• struct drm_i915_private *i915 = to_i915(intel_dig_port-

...

base.base.dev);

• ssize_t ret;
• ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,

DP_AUX_HDCP_BCAPS,

• 	       bcaps, 1);
  

• if (ret != 1) {

• drm_dbg_kms(&i915->drm,
  

• 	    "Read bcaps from DP/AUX failed (%zd)\n", ret);
  

• return ret >= 0 ? -EIO : ret;
  

• }
• return 0;

-}

-static -int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,

• 		   bool *repeater_present)
  

-{

• ssize_t ret;
• u8 bcaps;
• ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
• if (ret)

• return ret;
  

• *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
• return 0;

-}

-static -int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,

• 		u8 *ri_prime)
  

-{

• struct drm_i915_private *i915 = to_i915(intel_dig_port-

...

base.base.dev);

• ssize_t ret;
• ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,

DP_AUX_HDCP_RI_PRIME,

• 	       ri_prime, DRM_HDCP_RI_LEN);
  

• if (ret != DRM_HDCP_RI_LEN) {

• drm_dbg_kms(&i915->drm, "Read Ri' from DP/AUX failed
  

(%zd)\n",

• 	    ret);
  

• return ret >= 0 ? -EIO : ret;
  

• }
• return 0;

-}

-static -int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,

• 		 bool *ksv_ready)
  

-{

• struct drm_i915_private *i915 = to_i915(intel_dig_port-

...

base.base.dev);

• ssize_t ret;
• u8 bstatus;
• ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,

DP_AUX_HDCP_BSTATUS,

• 	       &bstatus, 1);
  

• if (ret != 1) {

• drm_dbg_kms(&i915->drm,
  

• 	    "Read bstatus from DP/AUX failed (%zd)\n", ret);
  

• return ret >= 0 ? -EIO : ret;
  

• }
• *ksv_ready = bstatus & DP_BSTATUS_READY;
• return 0;

-}

-static -int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,

• 		int num_downstream, u8 *ksv_fifo)
  

-{

• struct drm_i915_private *i915 = to_i915(intel_dig_port-

...

base.base.dev);

• ssize_t ret;
• int i;
• /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
• for (i = 0; i < num_downstream; i += 3) {

• size_t len = min(num_downstream - i, 3) *
  

DRM_HDCP_KSV_LEN;

• ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
  

• 		       DP_AUX_HDCP_KSV_FIFO,
  

• 		       ksv_fifo + i * DRM_HDCP_KSV_LEN,
  

• 		       len);
  

• if (ret != len) {
  

• 	drm_dbg_kms(&i915->drm,
  

• 		    "Read ksv[%d] from DP/AUX failed (%zd)\n",
  

• 		    i, ret);
  

• 	return ret >= 0 ? -EIO : ret;
  

• }
  

• }
• return 0;

-}

-static -int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,

• 		    int i, u32 *part)
  

-{

• struct drm_i915_private *i915 = to_i915(intel_dig_port-

...

base.base.dev);

• ssize_t ret;
• if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)

• return -EINVAL;
  

• ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,

• 	       DP_AUX_HDCP_V_PRIME(i), part,
  

• 	       DRM_HDCP_V_PRIME_PART_LEN);
  

• if (ret != DRM_HDCP_V_PRIME_PART_LEN) {

• drm_dbg_kms(&i915->drm,
  

• 	    "Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
  

• return ret >= 0 ? -EIO : ret;
  

• }
• return 0;

-}

-static -int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,

• 		    enum transcoder cpu_transcoder,
  

• 		    bool enable)
  

-{

• /* Not used for single stream DisplayPort setups */
• return 0;

-}

-static -bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port) -{

• struct drm_i915_private *i915 = to_i915(intel_dig_port-

...

base.base.dev);

• ssize_t ret;
• u8 bstatus;
• ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,

DP_AUX_HDCP_BSTATUS,

• 	       &bstatus, 1);
  

• if (ret != 1) {

• drm_dbg_kms(&i915->drm,
  

• 	    "Read bstatus from DP/AUX failed (%zd)\n", ret);
  

• return false;
  

• }
• return !(bstatus & (DP_BSTATUS_LINK_FAILURE |

DP_BSTATUS_REAUTH_REQ)); -}

-static -int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port,

• 	  bool *hdcp_capable)
  

-{

• ssize_t ret;
• u8 bcaps;
• ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
• if (ret)

• return ret;
  

• *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
• return 0;

-}

-struct hdcp2_dp_errata_stream_type {

• u8 msg_id;
• u8 stream_type;

-} __packed;

-struct hdcp2_dp_msg_data {

• u8 msg_id;
• u32 offset;
• bool msg_detectable;
• u32 timeout;
• u32 timeout2; /* Added for non_paired situation */

-};

-static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = {

• { HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0 },
• { HDCP_2_2_AKE_SEND_CERT,

DP_HDCP_2_2_AKE_SEND_CERT_OFFSET,

•  false, HDCP_2_2_CERT_TIMEOUT_MS, 0 },
  

• { HDCP_2_2_AKE_NO_STORED_KM,

DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET,

•  false, 0, 0 },
  

• { HDCP_2_2_AKE_STORED_KM,

DP_HDCP_2_2_AKE_STORED_KM_OFFSET,

•  false, 0, 0 },
  

• { HDCP_2_2_AKE_SEND_HPRIME,

DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET,

•  true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
  

•  HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS },
  

• { HDCP_2_2_AKE_SEND_PAIRING_INFO,

•  DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true,
  

•  HDCP_2_2_PAIRING_TIMEOUT_MS, 0 },
  

• { HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0 },
• { HDCP_2_2_LC_SEND_LPRIME,

DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET,

•  false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0 },
  

• { HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET,

false,

•  0, 0 },
  

• { HDCP_2_2_REP_SEND_RECVID_LIST,

•  DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true,
  

•  HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0 },
  

• { HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET,

false,

•  0, 0 },
  

• { HDCP_2_2_REP_STREAM_MANAGE,

•  DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false,
  

•  0, 0 },
  

• { HDCP_2_2_REP_STREAM_READY,

DP_HDCP_2_2_REP_STREAM_READY_OFFSET,

•  false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0 },
  

-/* local define to shovel this through the write_2_2 interface */ -#define HDCP_2_2_ERRATA_DP_STREAM_TYPE 50

• { HDCP_2_2_ERRATA_DP_STREAM_TYPE,

•  DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false,
  

•  0, 0 },
  

-};

-static int -intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,

• 	      u8 *rx_status)
  

-{

• struct drm_i915_private *i915 = to_i915(intel_dig_port-

...

base.base.dev);

• ssize_t ret;
• ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,

• 	       DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status,
  

• 	       HDCP_2_2_DP_RXSTATUS_LEN);
  

• if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {

• drm_dbg_kms(&i915->drm,
  

• 	    "Read bstatus from DP/AUX failed (%zd)\n", ret);
  

• return ret >= 0 ? -EIO : ret;
  

• }
• return 0;

-}

-static -int hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port,

• 		  u8 msg_id, bool *msg_ready)
  

-{

• u8 rx_status;
• int ret;
• *msg_ready = false;
• ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
• if (ret < 0)

• return ret;
  

• switch (msg_id) {
• case HDCP_2_2_AKE_SEND_HPRIME:

• if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status))
  

• 	*msg_ready = true;
  

• break;
  

• case HDCP_2_2_AKE_SEND_PAIRING_INFO:

• if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status))
  

• 	*msg_ready = true;
  

• break;
  

• case HDCP_2_2_REP_SEND_RECVID_LIST:

• if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
  

• 	*msg_ready = true;
  

• break;
  

• default:

• DRM_ERROR("Unidentified msg_id: %d\n", msg_id);
  

• return -EINVAL;
  

• }
• return 0;

-}

-static ssize_t -intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port,

• 	    const struct hdcp2_dp_msg_data *hdcp2_msg_data)
  

-{

• struct drm_i915_private *i915 = to_i915(intel_dig_port-

...

base.base.dev);

• struct intel_dp *dp = &intel_dig_port->dp;
• struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
• u8 msg_id = hdcp2_msg_data->msg_id;
• int ret, timeout;
• bool msg_ready = false;
• if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired)

• timeout = hdcp2_msg_data->timeout2;
  

• else

• timeout = hdcp2_msg_data->timeout;
  

• /*

• * There is no way to detect the CERT, LPRIME and STREAM_READY
  

• * availability. So Wait for timeout and read the msg.
  

• */
  

• if (!hdcp2_msg_data->msg_detectable) {

• mdelay(timeout);
  

• ret = 0;
  

• } else {

• /*
  

•  * As we want to check the msg availability at timeout, Ignoring
  

•  * the timeout at wait for CP_IRQ.
  

•  */
  

• intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout);
  

• ret = hdcp2_detect_msg_availability(intel_dig_port,
  

• 				    msg_id, &msg_ready);
  

• if (!msg_ready)
  

• 	ret = -ETIMEDOUT;
  

• }
• if (ret)

• drm_dbg_kms(&i915->drm,
  

• 	    "msg_id %d, ret %d, timeout(mSec): %d\n",
  

• 	    hdcp2_msg_data->msg_id, ret, timeout);
  

• return ret;

-}

-static const struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id) - {

• int i;
• for (i = 0; i < ARRAY_SIZE(hdcp2_dp_msg_data); i++)

• if (hdcp2_dp_msg_data[i].msg_id == msg_id)
  

• 	return &hdcp2_dp_msg_data[i];
  

• return NULL;

-}

-static -int intel_dp_hdcp2_write_msg(struct intel_digital_port *intel_dig_port,

• 	     void *buf, size_t size)
  

-{

• struct intel_dp *dp = &intel_dig_port->dp;
• struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
• unsigned int offset;
• u8 *byte = buf;
• ssize_t ret, bytes_to_write, len;
• const struct hdcp2_dp_msg_data *hdcp2_msg_data;
• hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte);
• if (!hdcp2_msg_data)

• return -EINVAL;
  

• offset = hdcp2_msg_data->offset;
• /* No msg_id in DP HDCP2.2 msgs */
• bytes_to_write = size - 1;
• byte++;
• hdcp->cp_irq_count_cached = atomic_read(&hdcp->cp_irq_count);
• while (bytes_to_write) {

• len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ?
  

• 		DP_AUX_MAX_PAYLOAD_BYTES :
  

bytes_to_write;

• ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux,
  

• 			offset, (void *)byte, len);
  

• if (ret < 0)
  

• 	return ret;
  

• bytes_to_write -= ret;
  

• byte += ret;
  

• offset += ret;
  

• }
• return size;

-}

-static -ssize_t get_receiver_id_list_size(struct intel_digital_port *intel_dig_port) -{

• u8 rx_info[HDCP_2_2_RXINFO_LEN];
• u32 dev_cnt;
• ssize_t ret;
• ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,

• 	       DP_HDCP_2_2_REG_RXINFO_OFFSET,
  

• 	       (void *)rx_info, HDCP_2_2_RXINFO_LEN);
  

• if (ret != HDCP_2_2_RXINFO_LEN)

• return ret >= 0 ? -EIO : ret;
  

• dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 |

•    HDCP_2_2_DEV_COUNT_LO(rx_info[1]));
  

• if (dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT)

• dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT;
  

• ret = sizeof(struct hdcp2_rep_send_receiverid_list) -

• HDCP_2_2_RECEIVER_IDS_MAX_LEN +
  

• (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN);
  

• return ret;

-}

-static -int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port,

• 	    u8 msg_id, void *buf, size_t size)
  

-{

• struct drm_i915_private *i915 = to_i915(intel_dig_port-

...

base.base.dev);

• unsigned int offset;
• u8 *byte = buf;
• ssize_t ret, bytes_to_recv, len;
• const struct hdcp2_dp_msg_data *hdcp2_msg_data;
• hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id);
• if (!hdcp2_msg_data)

• return -EINVAL;
  

• offset = hdcp2_msg_data->offset;
• ret = intel_dp_hdcp2_wait_for_msg(intel_dig_port, hdcp2_msg_data);
• if (ret < 0)

• return ret;
  

• if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) {

• ret = get_receiver_id_list_size(intel_dig_port);
  

• if (ret < 0)
  

• 	return ret;
  

• size = ret;
  

• }
• bytes_to_recv = size - 1;
• /* DP adaptation msgs has no msg_id */
• byte++;
• while (bytes_to_recv) {

• len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ?
  

•       DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv;
  

• ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, offset,
  

• 		       (void *)byte, len);
  

• if (ret < 0) {
  

• 	drm_dbg_kms(&i915->drm, "msg_id %d, ret %zd\n",
  

• 		    msg_id, ret);
  

• 	return ret;
  

• }
  

• bytes_to_recv -= ret;
  

• byte += ret;
  

• offset += ret;
  

• }
• byte = buf;
• *byte = msg_id;
• return size;

-}

-static -int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *intel_dig_port,

• 		      bool is_repeater, u8 content_type)
  

-{

• int ret;
• struct hdcp2_dp_errata_stream_type stream_type_msg;
• if (is_repeater)

• return 0;
  

• /*

• * Errata for DP: As Stream type is used for encryption, Receiver
  

• * should be communicated with stream type for the decryption of the
  

• * content.
  

• * Repeater will be communicated with stream type as a part of it's
  

• * auth later in time.
  

• */
  

• stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE;
• stream_type_msg.stream_type = content_type;
• ret = intel_dp_hdcp2_write_msg(intel_dig_port, &stream_type_msg,

• 			sizeof(stream_type_msg));
  

• return ret < 0 ? ret : 0;

-}

-static -int intel_dp_hdcp2_check_link(struct intel_digital_port *intel_dig_port) -{

• u8 rx_status;
• int ret;
• ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
• if (ret)

• return ret;
  

• if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status))

• ret = HDCP_REAUTH_REQUEST;
  

• else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status))

• ret = HDCP_LINK_INTEGRITY_FAILURE;
  

• else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))

• ret = HDCP_TOPOLOGY_CHANGE;
  

• return ret;

-}

-static -int intel_dp_hdcp2_capable(struct intel_digital_port *intel_dig_port,

• 	   bool *capable)
  

-{

• u8 rx_caps[3];
• int ret;
• *capable = false;
• ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,

• 	       DP_HDCP_2_2_REG_RX_CAPS_OFFSET,
  

• 	       rx_caps, HDCP_2_2_RXCAPS_LEN);
  

• if (ret != HDCP_2_2_RXCAPS_LEN)

• return ret >= 0 ? -EIO : ret;
  

• if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL &&

•    HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2]))
  

• *capable = true;
  

• return 0;

-}

-static const struct intel_hdcp_shim intel_dp_hdcp_shim = {

• .write_an_aksv = intel_dp_hdcp_write_an_aksv,
• .read_bksv = intel_dp_hdcp_read_bksv,
• .read_bstatus = intel_dp_hdcp_read_bstatus,
• .repeater_present = intel_dp_hdcp_repeater_present,
• .read_ri_prime = intel_dp_hdcp_read_ri_prime,
• .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
• .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
• .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
• .toggle_signalling = intel_dp_hdcp_toggle_signalling,
• .check_link = intel_dp_hdcp_check_link,
• .hdcp_capable = intel_dp_hdcp_capable,
• .write_2_2_msg = intel_dp_hdcp2_write_msg,
• .read_2_2_msg = intel_dp_hdcp2_read_msg,
• .config_stream_type = intel_dp_hdcp2_config_stream_type,
• .check_2_2_link = intel_dp_hdcp2_check_link,
• .hdcp_2_2_capable = intel_dp_hdcp2_capable,
• .protocol = HDCP_PROTOCOL_DP,

-};

static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); @@ -8232,7 +7628,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, intel_dp_add_properties(intel_dp, connector);

if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {

• int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim);
  

• int ret = intel_dp_init_hdcp(intel_dig_port, intel_connector);
  

  if (ret) drm_dbg_kms(&dev_priv->drm, "HDCP init failed, skipping.\n"); diff --git

a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 6352c7e97e3b..794f25573254 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -134,4 +134,7 @@ void intel_ddi_update_pipe(struct intel_atomic_state *state, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state);

+int intel_dp_init_hdcp(struct intel_digital_port *intel_dig_port,

•        struct intel_connector *intel_connector);
  

#endif /* __INTEL_DP_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c new file mode 100644 index 000000000000..0e06a1066d61 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c @@ -0,0 +1,636 @@ +/* SPDX-License-Identifier: MIT */ +/*

• • Copyright (C) 2020 Google, Inc.
• • Authors:
• • Sean Paul seanpaul@chromium.org
• */

+#include <drm/drm_dp_helper.h> +#include <drm/drm_hdcp.h> +#include <drm/drm_print.h>

+#include "intel_display_types.h" +#include "intel_dp.h" +#include "intel_hdcp.h"

+static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int +timeout) {

• long ret;

+#define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count))

• ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C,

• 			       msecs_to_jiffies(timeout));
  

• if (!ret)

• DRM_DEBUG_KMS("Timedout at waiting for CP_IRQ\n"); }
  

+static +int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,

• 		u8 *an)
  

+{

• struct drm_i915_private *i915 = to_i915(intel_dig_port-

...

base.base.dev);

• u8 aksv[DRM_HDCP_KSV_LEN] = {};
• ssize_t dpcd_ret;
• dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux,

DP_AUX_HDCP_AN,

• 		     an, DRM_HDCP_AN_LEN);
  

• if (dpcd_ret != DRM_HDCP_AN_LEN) {

• drm_dbg_kms(&i915->drm,
  

• 	    "Failed to write An over DP/AUX (%zd)\n",
  

• 	    dpcd_ret);
  

• return dpcd_ret >= 0 ? -EIO : dpcd_ret;
  

• }
• /*

• * Since Aksv is Oh-So-Secret, we can't access it in software. So we
  

• * send an empty buffer of the correct length through the DP helpers. On
  

• * the other side, in the transfer hook, we'll generate a flag based on
  

• * the destination address which will tickle the hardware to output the
  

• * Aksv on our behalf after the header is sent.
  

• */
  

• dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux,

DP_AUX_HDCP_AKSV,

• 		     aksv, DRM_HDCP_KSV_LEN);
  

• if (dpcd_ret != DRM_HDCP_KSV_LEN) {

• drm_dbg_kms(&i915->drm,
  

• 	    "Failed to write Aksv over DP/AUX (%zd)\n",
  

• 	    dpcd_ret);
  

• return dpcd_ret >= 0 ? -EIO : dpcd_ret;
  

• }
• return 0;

+}

+static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,

• 		   u8 *bksv)
  

+{

• struct drm_i915_private *i915 = to_i915(intel_dig_port-

...

base.base.dev);

• ssize_t ret;
• ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,

DP_AUX_HDCP_BKSV, bksv,

• 	       DRM_HDCP_KSV_LEN);
  

• if (ret != DRM_HDCP_KSV_LEN) {

• drm_dbg_kms(&i915->drm,
  

• 	    "Read Bksv from DP/AUX failed (%zd)\n", ret);
  

• return ret >= 0 ? -EIO : ret;
  

• }
• return 0;

+}

+static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,

• 		      u8 *bstatus)
  

+{

• struct drm_i915_private *i915 = to_i915(intel_dig_port-

...

base.base.dev);

• ssize_t ret;
• /*

• * For some reason the HDMI and DP HDCP specs call this register
  

• * definition by different names. In the HDMI spec, it's called BSTATUS,
  

• * but in DP it's called BINFO.
  

• */
  

• ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,

DP_AUX_HDCP_BINFO,

• 	       bstatus, DRM_HDCP_BSTATUS_LEN);
  

• if (ret != DRM_HDCP_BSTATUS_LEN) {

• drm_dbg_kms(&i915->drm,
  

• 	    "Read bstatus from DP/AUX failed (%zd)\n", ret);
  

• return ret >= 0 ? -EIO : ret;
  

• }
• return 0;

+}

+static +int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port,

• 	     u8 *bcaps)
  

+{

• struct drm_i915_private *i915 = to_i915(intel_dig_port-

...

base.base.dev);

• ssize_t ret;
• ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,

DP_AUX_HDCP_BCAPS,

• 	       bcaps, 1);
  

• if (ret != 1) {

• drm_dbg_kms(&i915->drm,
  

• 	    "Read bcaps from DP/AUX failed (%zd)\n", ret);
  

• return ret >= 0 ? -EIO : ret;
  

• }
• return 0;

+}

+static +int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,

• 		   bool *repeater_present)
  

+{

• ssize_t ret;
• u8 bcaps;
• ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
• if (ret)

• return ret;
  

• *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
• return 0;

+}

+static +int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,

• 		u8 *ri_prime)
  

+{

• struct drm_i915_private *i915 = to_i915(intel_dig_port-

...

base.base.dev);

• ssize_t ret;
• ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,

DP_AUX_HDCP_RI_PRIME,

• 	       ri_prime, DRM_HDCP_RI_LEN);
  

• if (ret != DRM_HDCP_RI_LEN) {

• drm_dbg_kms(&i915->drm, "Read Ri' from DP/AUX failed
  

(%zd)\n",

• 	    ret);
  

• return ret >= 0 ? -EIO : ret;
  

• }
• return 0;

+}

+static +int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,

• 		 bool *ksv_ready)
  

+{

• struct drm_i915_private *i915 = to_i915(intel_dig_port-

...

base.base.dev);

• ssize_t ret;
• u8 bstatus;
• ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,

DP_AUX_HDCP_BSTATUS,

• 	       &bstatus, 1);
  

• if (ret != 1) {

• drm_dbg_kms(&i915->drm,
  

• 	    "Read bstatus from DP/AUX failed (%zd)\n", ret);
  

• return ret >= 0 ? -EIO : ret;
  

• }
• *ksv_ready = bstatus & DP_BSTATUS_READY;
• return 0;

+}

+static +int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,

• 		int num_downstream, u8 *ksv_fifo)
  

+{

• struct drm_i915_private *i915 = to_i915(intel_dig_port-

...

base.base.dev);

• ssize_t ret;
• int i;
• /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
• for (i = 0; i < num_downstream; i += 3) {

• size_t len = min(num_downstream - i, 3) *
  

DRM_HDCP_KSV_LEN;

• ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
  

• 		       DP_AUX_HDCP_KSV_FIFO,
  

• 		       ksv_fifo + i * DRM_HDCP_KSV_LEN,
  

• 		       len);
  

• if (ret != len) {
  

• 	drm_dbg_kms(&i915->drm,
  

• 		    "Read ksv[%d] from DP/AUX failed (%zd)\n",
  

• 		    i, ret);
  

• 	return ret >= 0 ? -EIO : ret;
  

• }
  

• }
• return 0;

+}

+static +int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,

• 		    int i, u32 *part)
  

+{

• struct drm_i915_private *i915 = to_i915(intel_dig_port-

...

base.base.dev);

• ssize_t ret;
• if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)

• return -EINVAL;
  

• ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,

• 	       DP_AUX_HDCP_V_PRIME(i), part,
  

• 	       DRM_HDCP_V_PRIME_PART_LEN);
  

• if (ret != DRM_HDCP_V_PRIME_PART_LEN) {

• drm_dbg_kms(&i915->drm,
  

• 	    "Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
  

• return ret >= 0 ? -EIO : ret;
  

• }
• return 0;

+}

+static +int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,

• 		    enum transcoder cpu_transcoder,
  

• 		    bool enable)
  

+{

• /* Not used for single stream DisplayPort setups */
• return 0;

+}

+static +bool intel_dp_hdcp_check_link(struct intel_digital_port +*intel_dig_port) {

• struct drm_i915_private *i915 = to_i915(intel_dig_port-

...

base.base.dev);

• ssize_t ret;
• u8 bstatus;
• ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,

DP_AUX_HDCP_BSTATUS,

• 	       &bstatus, 1);
  

• if (ret != 1) {

• drm_dbg_kms(&i915->drm,
  

• 	    "Read bstatus from DP/AUX failed (%zd)\n", ret);
  

• return false;
  

• }
• return !(bstatus & (DP_BSTATUS_LINK_FAILURE |

DP_BSTATUS_REAUTH_REQ)); +}

+static +int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port,

• 	  bool *hdcp_capable)
  

+{

• ssize_t ret;
• u8 bcaps;
• ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
• if (ret)

• return ret;
  

• *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
• return 0;

+}

+struct hdcp2_dp_errata_stream_type {

• u8 msg_id;
• u8 stream_type;

+} __packed;

+struct hdcp2_dp_msg_data {

• u8 msg_id;
• u32 offset;
• bool msg_detectable;
• u32 timeout;
• u32 timeout2; /* Added for non_paired situation */ };

+static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = {

• { HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0 },
• { HDCP_2_2_AKE_SEND_CERT,

DP_HDCP_2_2_AKE_SEND_CERT_OFFSET,

•  false, HDCP_2_2_CERT_TIMEOUT_MS, 0 },
  

• { HDCP_2_2_AKE_NO_STORED_KM,

DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET,

•  false, 0, 0 },
  

• { HDCP_2_2_AKE_STORED_KM,

DP_HDCP_2_2_AKE_STORED_KM_OFFSET,

•  false, 0, 0 },
  

• { HDCP_2_2_AKE_SEND_HPRIME,

DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET,

•  true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
  

•  HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS },
  

• { HDCP_2_2_AKE_SEND_PAIRING_INFO,

•  DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true,
  

•  HDCP_2_2_PAIRING_TIMEOUT_MS, 0 },
  

• { HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0 },
• { HDCP_2_2_LC_SEND_LPRIME,

DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET,

•  false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0 },
  

• { HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET,

false,

•  0, 0 },
  

• { HDCP_2_2_REP_SEND_RECVID_LIST,

•  DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true,
  

•  HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0 },
  

• { HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET,

false,

•  0, 0 },
  

• { HDCP_2_2_REP_STREAM_MANAGE,

•  DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false,
  

•  0, 0 },
  

• { HDCP_2_2_REP_STREAM_READY,

DP_HDCP_2_2_REP_STREAM_READY_OFFSET,

•  false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0 },
  

+/* local define to shovel this through the write_2_2 interface */ +#define HDCP_2_2_ERRATA_DP_STREAM_TYPE 50

• { HDCP_2_2_ERRATA_DP_STREAM_TYPE,

•  DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false,
  

•  0, 0 },
  

+};

+static int +intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,

• 	      u8 *rx_status)
  

+{

• struct drm_i915_private *i915 = to_i915(intel_dig_port-

...

base.base.dev);

• ssize_t ret;
• ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,

• 	       DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status,
  

• 	       HDCP_2_2_DP_RXSTATUS_LEN);
  

• if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {

• drm_dbg_kms(&i915->drm,
  

• 	    "Read bstatus from DP/AUX failed (%zd)\n", ret);
  

• return ret >= 0 ? -EIO : ret;
  

• }
• return 0;

+}

+static +int hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port,

• 		  u8 msg_id, bool *msg_ready)
  

+{

• u8 rx_status;
• int ret;
• *msg_ready = false;
• ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
• if (ret < 0)

• return ret;
  

• switch (msg_id) {
• case HDCP_2_2_AKE_SEND_HPRIME:

• if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status))
  

• 	*msg_ready = true;
  

• break;
  

• case HDCP_2_2_AKE_SEND_PAIRING_INFO:

• if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status))
  

• 	*msg_ready = true;
  

• break;
  

• case HDCP_2_2_REP_SEND_RECVID_LIST:

• if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
  

• 	*msg_ready = true;
  

• break;
  

• default:

• DRM_ERROR("Unidentified msg_id: %d\n", msg_id);
  

• return -EINVAL;
  

• }
• return 0;

+}

+static ssize_t +intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port,

• 	    const struct hdcp2_dp_msg_data *hdcp2_msg_data)
  

{

• struct drm_i915_private *i915 = to_i915(intel_dig_port-

...

base.base.dev);

• struct intel_dp *dp = &intel_dig_port->dp;
• struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
• u8 msg_id = hdcp2_msg_data->msg_id;
• int ret, timeout;
• bool msg_ready = false;
• if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired)

• timeout = hdcp2_msg_data->timeout2;
  

• else

• timeout = hdcp2_msg_data->timeout;
  

• /*

• * There is no way to detect the CERT, LPRIME and STREAM_READY
  

• * availability. So Wait for timeout and read the msg.
  

• */
  

• if (!hdcp2_msg_data->msg_detectable) {

• mdelay(timeout);
  

• ret = 0;
  

• } else {

• /*
  

•  * As we want to check the msg availability at timeout, Ignoring
  

•  * the timeout at wait for CP_IRQ.
  

•  */
  

• intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout);
  

• ret = hdcp2_detect_msg_availability(intel_dig_port,
  

• 				    msg_id, &msg_ready);
  

• if (!msg_ready)
  

• 	ret = -ETIMEDOUT;
  

• }
• if (ret)

• drm_dbg_kms(&i915->drm,
  

• 	    "msg_id %d, ret %d, timeout(mSec): %d\n",
  

• 	    hdcp2_msg_data->msg_id, ret, timeout);
  

• return ret;

+}

+static const struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id) +{

• int i;
• for (i = 0; i < ARRAY_SIZE(hdcp2_dp_msg_data); i++)

• if (hdcp2_dp_msg_data[i].msg_id == msg_id)
  

• 	return &hdcp2_dp_msg_data[i];
  

• return NULL;

+}

+static +int intel_dp_hdcp2_write_msg(struct intel_digital_port *intel_dig_port,

• 	     void *buf, size_t size)
  

+{

• struct intel_dp *dp = &intel_dig_port->dp;
• struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
• unsigned int offset;
• u8 *byte = buf;
• ssize_t ret, bytes_to_write, len;
• const struct hdcp2_dp_msg_data *hdcp2_msg_data;
• hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte);
• if (!hdcp2_msg_data)

• return -EINVAL;
  

• offset = hdcp2_msg_data->offset;
• /* No msg_id in DP HDCP2.2 msgs */
• bytes_to_write = size - 1;
• byte++;
• hdcp->cp_irq_count_cached = atomic_read(&hdcp->cp_irq_count);
• while (bytes_to_write) {

• len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ?
  

• 		DP_AUX_MAX_PAYLOAD_BYTES :
  

bytes_to_write;

• ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux,
  

• 			offset, (void *)byte, len);
  

• if (ret < 0)
  

• 	return ret;
  

• bytes_to_write -= ret;
  

• byte += ret;
  

• offset += ret;
  

• }
• return size;

+}

+static +ssize_t get_receiver_id_list_size(struct intel_digital_port +*intel_dig_port) {

• u8 rx_info[HDCP_2_2_RXINFO_LEN];
• u32 dev_cnt;
• ssize_t ret;
• ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,

• 	       DP_HDCP_2_2_REG_RXINFO_OFFSET,
  

• 	       (void *)rx_info, HDCP_2_2_RXINFO_LEN);
  

• if (ret != HDCP_2_2_RXINFO_LEN)

• return ret >= 0 ? -EIO : ret;
  

• dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 |

•    HDCP_2_2_DEV_COUNT_LO(rx_info[1]));
  

• if (dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT)

• dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT;
  

• ret = sizeof(struct hdcp2_rep_send_receiverid_list) -

• HDCP_2_2_RECEIVER_IDS_MAX_LEN +
  

• (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN);
  

• return ret;

+}

+static +int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port,

• 	    u8 msg_id, void *buf, size_t size) {
  

• struct drm_i915_private *i915 = to_i915(intel_dig_port-

...

base.base.dev);

• unsigned int offset;
• u8 *byte = buf;
• ssize_t ret, bytes_to_recv, len;
• const struct hdcp2_dp_msg_data *hdcp2_msg_data;
• hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id);
• if (!hdcp2_msg_data)

• return -EINVAL;
  

• offset = hdcp2_msg_data->offset;
• ret = intel_dp_hdcp2_wait_for_msg(intel_dig_port, hdcp2_msg_data);
• if (ret < 0)

• return ret;
  

• if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) {

• ret = get_receiver_id_list_size(intel_dig_port);
  

• if (ret < 0)
  

• 	return ret;
  

• size = ret;
  

• }
• bytes_to_recv = size - 1;
• /* DP adaptation msgs has no msg_id */
• byte++;
• while (bytes_to_recv) {

• len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ?
  

•       DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv;
  

• ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, offset,
  

• 		       (void *)byte, len);
  

• if (ret < 0) {
  

• 	drm_dbg_kms(&i915->drm, "msg_id %d, ret %zd\n",
  

• 		    msg_id, ret);
  

• 	return ret;
  

• }
  

• bytes_to_recv -= ret;
  

• byte += ret;
  

• offset += ret;
  

• }
• byte = buf;
• *byte = msg_id;
• return size;

+}

+static +int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *intel_dig_port,

• 		      bool is_repeater, u8 content_type) {
  

• int ret;
• struct hdcp2_dp_errata_stream_type stream_type_msg;
• if (is_repeater)

• return 0;
  

• /*

• * Errata for DP: As Stream type is used for encryption, Receiver
  

• * should be communicated with stream type for the decryption of the
  

• * content.
  

• * Repeater will be communicated with stream type as a part of it's
  

• * auth later in time.
  

• */
  

• stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE;
• stream_type_msg.stream_type = content_type;
• ret = intel_dp_hdcp2_write_msg(intel_dig_port, &stream_type_msg,

• 			sizeof(stream_type_msg));
  

• return ret < 0 ? ret : 0;

+}

+static +int intel_dp_hdcp2_check_link(struct intel_digital_port +*intel_dig_port) {

• u8 rx_status;
• int ret;
• ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
• if (ret)

• return ret;
  

• if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status))

• ret = HDCP_REAUTH_REQUEST;
  

• else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status))

• ret = HDCP_LINK_INTEGRITY_FAILURE;
  

• else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))

• ret = HDCP_TOPOLOGY_CHANGE;
  

• return ret;

+}

+static +int intel_dp_hdcp2_capable(struct intel_digital_port *intel_dig_port,

• 	   bool *capable)
  

+{

• u8 rx_caps[3];
• int ret;
• *capable = false;
• ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,

• 	       DP_HDCP_2_2_REG_RX_CAPS_OFFSET,
  

• 	       rx_caps, HDCP_2_2_RXCAPS_LEN);
  

• if (ret != HDCP_2_2_RXCAPS_LEN)

• return ret >= 0 ? -EIO : ret;
  

• if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL &&

•    HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2]))
  

• *capable = true;
  

• return 0;

+}

+static const struct intel_hdcp_shim intel_dp_hdcp_shim = {

• .write_an_aksv = intel_dp_hdcp_write_an_aksv,
• .read_bksv = intel_dp_hdcp_read_bksv,
• .read_bstatus = intel_dp_hdcp_read_bstatus,
• .repeater_present = intel_dp_hdcp_repeater_present,
• .read_ri_prime = intel_dp_hdcp_read_ri_prime,
• .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
• .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
• .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
• .toggle_signalling = intel_dp_hdcp_toggle_signalling,
• .check_link = intel_dp_hdcp_check_link,
• .hdcp_capable = intel_dp_hdcp_capable,
• .write_2_2_msg = intel_dp_hdcp2_write_msg,
• .read_2_2_msg = intel_dp_hdcp2_read_msg,
• .config_stream_type = intel_dp_hdcp2_config_stream_type,
• .check_2_2_link = intel_dp_hdcp2_check_link,
• .hdcp_2_2_capable = intel_dp_hdcp2_capable,
• .protocol = HDCP_PROTOCOL_DP,

+};

+int intel_dp_init_hdcp(struct intel_digital_port *intel_dig_port,

•        struct intel_connector *intel_connector) {
  

• struct drm_device *dev = intel_connector->base.dev;
• struct drm_i915_private *dev_priv = to_i915(dev);
• struct intel_encoder *intel_encoder = &intel_dig_port->base;
• enum port port = intel_encoder->port;
• struct intel_dp *intel_dp = &intel_dig_port->dp;
• if (!is_hdcp_supported(dev_priv, port))

• return 0;
  

• if (!intel_dp_is_edp(intel_dp))

• return intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim);
  

• return 0;

+}

Sean Paul, Software Engineer, Google / Chromium OS

On 2020-06-23 at 21:29:03 +0530, Sean Paul wrote:

From: Sean Paul seanpaul@chromium.org

This patch plumbs port through hdcp init instead of relying on intel_attached_encoder() to return a non-NULL encoder which won't work for MST connectors.

Looks good to me, Reviewed-by: Anshuman Gupta anshuman.gupta@intel.com

Cc: Ville Syrjälä ville.syrjala@linux.intel.com Signed-off-by: Sean Paul seanpaul@chromium.org Link: https://patchwork.freedesktop.org/patch/msgid/20200305201236.152307-13-sean@... #v5 Link: https://patchwork.freedesktop.org/patch/msgid/20200429195502.39919-13-sean@p... #v6

Changes in v5: -Added to the set Changes in v6: -None Changes in v7:

-None

drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 3 ++- drivers/gpu/drm/i915/display/intel_hdcp.c | 11 ++++++----- drivers/gpu/drm/i915/display/intel_hdcp.h | 2 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +- 4 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c index 0e06a1066d61..e26a45f880cb 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c @@ -630,7 +630,8 @@ int intel_dp_init_hdcp(struct intel_digital_port *intel_dig_port, return 0;

if (!intel_dp_is_edp(intel_dp))

• return intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim);
  

• return intel_hdcp_init(intel_connector, port,
  

• 		       &intel_dp_hdcp_shim);
  
  

  return 0;

} diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 5679877c6b4c..d79d4142aea7 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -1955,6 +1955,7 @@ static enum mei_fw_tc intel_get_mei_fw_tc(enum transcoder cpu_transcoder) }

static int initialize_hdcp_port_data(struct intel_connector *connector,

• 		     enum port port,
  	     const struct intel_hdcp_shim *shim)
  

{ struct drm_i915_private *dev_priv = to_i915(connector->base.dev); @@ -1962,8 +1963,7 @@ static int initialize_hdcp_port_data(struct intel_connector *connector, struct hdcp_port_data *data = &hdcp->port_data;

if (INTEL_GEN(dev_priv) < 12)

• data->fw_ddi =
  

• 	intel_get_mei_fw_ddi_index(intel_attached_encoder(connector)->port);
  

• data->fw_ddi = intel_get_mei_fw_ddi_index(port);
  

  else /*
  • As per ME FW API expectation, for GEN 12+, fw_ddi is filled

@@ -2033,14 +2033,14 @@ void intel_hdcp_component_init(struct drm_i915_private *dev_priv) } }

-static void intel_hdcp2_init(struct intel_connector *connector, +static void intel_hdcp2_init(struct intel_connector *connector, enum port port, const struct intel_hdcp_shim *shim) { struct drm_i915_private *i915 = to_i915(connector->base.dev); struct intel_hdcp *hdcp = &connector->hdcp; int ret;

• ret = initialize_hdcp_port_data(connector, shim);

• ret = initialize_hdcp_port_data(connector, port, shim); if (ret) { drm_dbg_kms(&i915->drm, "Mei hdcp data init failed\n"); return;

@@ -2050,6 +2050,7 @@ static void intel_hdcp2_init(struct intel_connector *connector, }

int intel_hdcp_init(struct intel_connector *connector,

•     enum port port,
  

  const struct intel_hdcp_shim *shim)

{ struct drm_i915_private *dev_priv = to_i915(connector->base.dev); @@ -2060,7 +2061,7 @@ int intel_hdcp_init(struct intel_connector *connector, return -EINVAL;

if (is_hdcp2_supported(dev_priv))

• intel_hdcp2_init(connector, shim);
  

• intel_hdcp2_init(connector, port, shim);
  
  

  ret = drm_connector_attach_content_protection_property(&connector->base,

diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h b/drivers/gpu/drm/i915/display/intel_hdcp.h index 86bbaec120cc..1bbf5b67ed0a 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.h +++ b/drivers/gpu/drm/i915/display/intel_hdcp.h @@ -22,7 +22,7 @@ enum transcoder; void intel_hdcp_atomic_check(struct drm_connector *connector, struct drm_connector_state *old_state, struct drm_connector_state *new_state); -int intel_hdcp_init(struct intel_connector *connector, +int intel_hdcp_init(struct intel_connector *connector, enum port port, const struct intel_hdcp_shim *hdcp_shim); int intel_hdcp_enable(struct intel_connector *connector, enum transcoder cpu_transcoder, u8 content_type); diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index a59acfff456e..ca71ee3dd1c7 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -3260,7 +3260,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, intel_hdmi->attached_connector = intel_connector;

if (is_hdcp_supported(dev_priv, port)) {

• int ret = intel_hdcp_init(intel_connector,
  

• int ret = intel_hdcp_init(intel_connector, port,
  		  &intel_hdmi_hdcp_shim);
  

  if (ret) drm_dbg_kms(&dev_priv->drm,

-- Sean Paul, Software Engineer, Google / Chromium OS

---

Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-----Original Message----- From: Sean Paul sean@poorly.run Sent: Tuesday, June 23, 2020 9:29 PM To: dri-devel@lists.freedesktop.org; intel-gfx@lists.freedesktop.org Cc: Li, Juston juston.li@intel.com; C, Ramalingam ramalingam.c@intel.com; ville.syrjala@linux.intel.com; jani.nikula@linux.intel.com; joonas.lahtinen@linux.intel.com; Vivi, Rodrigo rodrigo.vivi@intel.com; daniel.vetter@ffwll.ch; Sean Paul seanpaul@chromium.org Subject: [PATCH v7 14/17] drm/i915: Add connector to hdcp_shim->check_link()

From: Sean Paul seanpaul@chromium.org

Currently we derive the connector from digital port in check_link(). For MST, this isn't sufficient since the digital port passed into the function can have multiple connectors downstream. This patch adds connector to the check_link() arguments so we have it when we need it.

Signed-off-by: Sean Paul seanpaul@chromium.org

Reviewed-by: Ramalingam C ramalingam.c@intel.com

Link: https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-13- sean@poorly.run #v4 Link: https://patchwork.freedesktop.org/patch/msgid/20200305201236.152307-14- sean@poorly.run #v5 Link: https://patchwork.freedesktop.org/patch/msgid/20200429195502.39919- 14-sean@poorly.run #v6

Changes in v4: -Added to the set Changes in v5: -None Changes in v6: -None Changes in v7:

-None

drivers/gpu/drm/i915/display/intel_display_types.h | 3 ++- drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 3 ++- drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +- drivers/gpu/drm/i915/display/intel_hdmi.c | 5 ++--- 4 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 811085ef3fba..94211b8fc159 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -318,7 +318,8 @@ struct intel_hdcp_shim { bool enable);

/* Ensures the link is still protected */

• bool (*check_link)(struct intel_digital_port *intel_dig_port);

• bool (*check_link)(struct intel_digital_port *intel_dig_port,

• 	   struct intel_connector *connector);
  
  

  /* Detects panel's hdcp capability. This is optional for HDMI. */ int (*hdcp_capable)(struct intel_digital_port *intel_dig_port, diff --git

a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c index e26a45f880cb..43446a6cae8d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c @@ -223,7 +223,8 @@ int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, }

static -bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port) +bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port,

• 	      struct intel_connector *connector)
  

{ struct drm_i915_private *i915 = to_i915(intel_dig_port-

...

base.base.dev);

ssize_t ret; diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index d79d4142aea7..6bd0e4616ee1 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -953,7 +953,7 @@ static int intel_hdcp_check_link(struct intel_connector *connector) goto out; }

• if (hdcp->shim->check_link(intel_dig_port)) {

• if (hdcp->shim->check_link(intel_dig_port, connector)) { if (hdcp->value !=

DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { intel_hdcp_update_value(connector,

DRM_MODE_CONTENT_PROTECTION_ENABLED, true); diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index ca71ee3dd1c7..b12f1af0611d 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -1546,11 +1546,10 @@ int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, }

static -bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port) +bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port,

• 		struct intel_connector *connector)
  

{ struct drm_i915_private *i915 = to_i915(intel_dig_port-

...

base.base.dev);

• struct intel_connector *connector =

• intel_dig_port->hdmi.attached_connector;
  

  enum port port = intel_dig_port->base.port; enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; int ret;

-- Sean Paul, Software Engineer, Google / Chromium OS

On 2020-06-23 at 21:29:05 +0530, Sean Paul wrote: Hi Sean, I am new to DP MST stuff, I am looking to DP MST spec DP v1.2a. I have looked the entire series, i will take up this opportunity to review the series from HDCP over DP MST POV. I think theoretically this series should work or Gen12 as well, as DP MST streams are getting encrypted by QUERY_STREAM_ENCRYPTION_STATUS reply tranaction msg (generating Stream State Signature L’). I will test this on Gen12 H/W with DP MST support and will provide my inputs.

Meanwhile while going through DP MST v1.2a specs(Page 262) came to know about a DP irq vector LINK_SERVICE_IRQ_VECTOR_ESI0 (02005h), Bit 2 : STREAM_STATUS_CHANGED. When this bit set to ‘1’ indicates the source must re-check the Stream Status with the QUERY_STREAM_ENCRYPTION_STATUS message. Currently i feel this irq support is missing, do we require to support above IRQ vector for DP MST stream encryption.

Thanks, Anshuman Gupta.

From: Sean Paul seanpaul@chromium.org

Used to query whether an MST stream is encrypted or not.

Signed-off-by: Sean Paul seanpaul@chromium.org

Link: https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-14-sean@... #v4 Link: https://patchwork.freedesktop.org/patch/msgid/20200305201236.152307-15-sean@... #v5 Link: https://patchwork.freedesktop.org/patch/msgid/20200429195502.39919-15-sean@p... #v6

Changes in v4: -Added to the set Changes in v5: -None Changes in v6: -Use FIELD_PREP to generate request buffer bitfields (Lyude) -Add mst selftest and dump/decode_sideband_req for QSES (Lyude) Changes in v7:

-None

drivers/gpu/drm/drm_dp_mst_topology.c | 142 ++++++++++++++++++ .../drm/selftests/test-drm_dp_mst_helper.c | 17 +++ include/drm/drm_dp_helper.h | 3 + include/drm/drm_dp_mst_helper.h | 44 ++++++ 4 files changed, 206 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index b2f5a84b4cfb..fc68478eaeb4 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c @@ -20,11 +20,13 @@

• OF THIS SOFTWARE.

*/

+#include <linux/bitfield.h> #include <linux/delay.h> #include <linux/errno.h> #include <linux/i2c.h> #include <linux/init.h> #include <linux/kernel.h> +#include <linux/random.h> #include <linux/sched.h> #include <linux/seq_file.h> #include <linux/iopoll.h> @@ -419,6 +421,22 @@ drm_dp_encode_sideband_req(const struct drm_dp_sideband_msg_req_body *req, memcpy(&buf[idx], req->u.i2c_write.bytes, req->u.i2c_write.num_bytes); idx += req->u.i2c_write.num_bytes; break;

• case DP_QUERY_STREAM_ENC_STATUS: {

• const struct drm_dp_query_stream_enc_status *msg;
  

• msg = &req->u.enc_status;
  

• buf[idx] = msg->stream_id;
  

• idx++;
  

• memcpy(&buf[idx], msg->client_id, sizeof(msg->client_id));
  

• idx += sizeof(msg->client_id);
  

• buf[idx] = 0;
  

• buf[idx] |= FIELD_PREP(GENMASK(1, 0), msg->stream_event);
  

• buf[idx] |= msg->valid_stream_event ? BIT(2) : 0;
  

• buf[idx] |= FIELD_PREP(GENMASK(4, 3), msg->stream_behavior);
  

• buf[idx] |= msg->valid_stream_behavior ? BIT(5) : 0;
  

• idx++;
  

• }
  

• break;
  

  } raw->cur_len = idx;

} @@ -547,6 +565,20 @@ drm_dp_decode_sideband_req(const struct drm_dp_sideband_msg_tx *raw, return -ENOMEM; } break;

• case DP_QUERY_STREAM_ENC_STATUS:

• req->u.enc_status.stream_id = buf[idx++];
  

• for (i = 0; i < sizeof(req->u.enc_status.client_id); i++)
  

• 	req->u.enc_status.client_id[i] = buf[idx++];
  

• req->u.enc_status.stream_event = FIELD_GET(GENMASK(1, 0),
  

• 					   buf[idx]);
  

• req->u.enc_status.valid_stream_event = FIELD_GET(BIT(2),
  

• 					 	 buf[idx]);
  

• req->u.enc_status.stream_behavior = FIELD_GET(GENMASK(4, 3),
  

• 					      buf[idx]);
  

• req->u.enc_status.valid_stream_behavior = FIELD_GET(BIT(5),
  

• 						    buf[idx]);
  

• break;
  

  }

  return 0;

@@ -625,6 +657,16 @@ drm_dp_dump_sideband_msg_req_body(const struct drm_dp_sideband_msg_req_body *req req->u.i2c_write.num_bytes, req->u.i2c_write.num_bytes, req->u.i2c_write.bytes); break;

• case DP_QUERY_STREAM_ENC_STATUS:

• P("stream_id=%u client_id=%*ph stream_event=%x "
  

•   "valid_event=%d stream_behavior=%x valid_behavior=%d",
  

•   req->u.enc_status.stream_id,
  

•   (int)ARRAY_SIZE(req->u.enc_status.client_id),
  

•   req->u.enc_status.client_id, req->u.enc_status.stream_event,
  

•   req->u.enc_status.valid_stream_event,
  

•   req->u.enc_status.stream_behavior,
  

•   req->u.enc_status.valid_stream_behavior);
  

• break;
  

  default: P("???\n"); break;

@@ -925,6 +967,34 @@ static bool drm_dp_sideband_parse_power_updown_phy_ack(struct drm_dp_sideband_ms return true; }

+static bool +drm_dp_sideband_parse_query_stream_enc_status(

• 		struct drm_dp_sideband_msg_rx *raw,
  

• 		struct drm_dp_sideband_msg_reply_body *repmsg)
  

+{

• struct drm_dp_query_stream_enc_status_ack_reply *reply;
• reply = &repmsg->u.enc_status;
• reply->stream_id = raw->msg[3];
• reply->reply_signed = raw->msg[2] & BIT(0);
• reply->hdcp_1x_device_present = raw->msg[2] & BIT(3);
• reply->hdcp_2x_device_present = raw->msg[2] & BIT(4);
• reply->query_capable_device_present = raw->msg[2] & BIT(5);
• reply->legacy_device_present = raw->msg[2] & BIT(6);
• reply->unauthorizable_device_present = raw->msg[2] & BIT(7);
• reply->auth_completed = !!(raw->msg[1] & BIT(3));
• reply->encryption_enabled = !!(raw->msg[1] & BIT(4));
• reply->repeater_present = !!(raw->msg[1] & BIT(5));
• reply->state = (raw->msg[1] & GENMASK(7, 6)) >> 6;
• return true;

+}

static bool drm_dp_sideband_parse_reply(struct drm_dp_sideband_msg_rx *raw, struct drm_dp_sideband_msg_reply_body *msg) { @@ -959,6 +1029,8 @@ static bool drm_dp_sideband_parse_reply(struct drm_dp_sideband_msg_rx *raw, return drm_dp_sideband_parse_power_updown_phy_ack(raw, msg); case DP_CLEAR_PAYLOAD_ID_TABLE: return true; /* since there's nothing to parse */

• case DP_QUERY_STREAM_ENC_STATUS:

• return drm_dp_sideband_parse_query_stream_enc_status(raw, msg);
  

  default: DRM_ERROR("Got unknown reply 0x%02x (%s)\n", msg->req_type, drm_dp_mst_req_type_str(msg->req_type));

@@ -1109,6 +1181,25 @@ static void build_power_updown_phy(struct drm_dp_sideband_msg_tx *msg, msg->path_msg = true; }

+static int +build_query_stream_enc_status(struct drm_dp_sideband_msg_tx *msg, u8 stream_id,

• 	      u8 *q_id)
  

+{

• struct drm_dp_sideband_msg_req_body req;
• req.req_type = DP_QUERY_STREAM_ENC_STATUS;
• req.u.enc_status.stream_id = stream_id;
• memcpy(req.u.enc_status.client_id, q_id,

•       sizeof(req.u.enc_status.client_id));
  

• req.u.enc_status.stream_event = 0;
• req.u.enc_status.valid_stream_event = false;
• req.u.enc_status.stream_behavior = 0;
• req.u.enc_status.valid_stream_behavior = false;
• drm_dp_encode_sideband_req(&req, msg);
• return 0;

+}

static int drm_dp_mst_assign_payload_id(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_vcpi *vcpi) { @@ -3137,6 +3228,57 @@ int drm_dp_send_power_updown_phy(struct drm_dp_mst_topology_mgr *mgr, } EXPORT_SYMBOL(drm_dp_send_power_updown_phy);

+int drm_dp_send_query_stream_enc_status(struct drm_dp_mst_topology_mgr *mgr,

• struct drm_dp_mst_port *port,
  

• struct drm_dp_query_stream_enc_status_ack_reply *status)
  

+{

• struct drm_dp_sideband_msg_tx *txmsg;
• u8 nonce[7];
• int len, ret;
• txmsg = kzalloc(sizeof(*txmsg), GFP_KERNEL);
• if (!txmsg)

• return -ENOMEM;
  

• port = drm_dp_mst_topology_get_port_validated(mgr, port);
• if (!port) {

• ret = -EINVAL;
  

• goto out_get_port;
  

• }
• get_random_bytes(nonce, sizeof(nonce));
• /*

• * "Source device targets the QUERY_STREAM_ENCRYPTION_STATUS message
  

• *  transaction at the MST Branch device directly connected to the
  

• *  Source"
  

• */
  

• txmsg->dst = mgr->mst_primary;
• len = build_query_stream_enc_status(txmsg, port->vcpi.vcpi, nonce);
• drm_dp_queue_down_tx(mgr, txmsg);
• ret = drm_dp_mst_wait_tx_reply(mgr->mst_primary, txmsg);
• if (ret < 0) {

• goto out;
  

• } else if (txmsg->reply.reply_type == DP_SIDEBAND_REPLY_NAK) {

• DRM_DEBUG_KMS("query encryption status nak received\n");
  

• ret = -ENXIO;
  

• goto out;
  

• }
• ret = 0;
• memcpy(status, &txmsg->reply.u.enc_status, sizeof(*status));

+out:

• drm_dp_mst_topology_put_port(port);

+out_get_port:

• kfree(txmsg);
• return ret;

+} +EXPORT_SYMBOL(drm_dp_send_query_stream_enc_status);

static int drm_dp_create_payload_step1(struct drm_dp_mst_topology_mgr *mgr, int id, struct drm_dp_payload *payload) diff --git a/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c b/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c index bd990d178765..1d696ec001cf 100644 --- a/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c +++ b/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c @@ -5,6 +5,8 @@

#define PREFIX_STR "[drm_dp_mst_helper]"

+#include <linux/random.h>

#include <drm/drm_dp_mst_helper.h> #include <drm/drm_print.h>

@@ -237,6 +239,21 @@ int igt_dp_mst_sideband_msg_req_decode(void *unused) in.u.i2c_write.bytes = data; DO_TEST();

• in.req_type = DP_QUERY_STREAM_ENC_STATUS;
• in.u.enc_status.stream_id = 1;
• DO_TEST();
• get_random_bytes(in.u.enc_status.client_id,

• 	 sizeof(in.u.enc_status.client_id));
  

• DO_TEST();
• in.u.enc_status.stream_event = 3;
• DO_TEST();
• in.u.enc_status.valid_stream_event = 0;
• DO_TEST();
• in.u.enc_status.stream_behavior = 3;
• DO_TEST();
• in.u.enc_status.valid_stream_behavior = 1;
• DO_TEST();

#undef DO_TEST return 0; } diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index e47dc22ebf50..e2d2df5e869e 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -1108,6 +1108,9 @@ #define DP_POWER_DOWN_PHY 0x25 #define DP_SINK_EVENT_NOTIFY 0x30 #define DP_QUERY_STREAM_ENC_STATUS 0x38 +#define DP_QUERY_STREAM_ENC_STATUS_STATE_NO_EXIST 0 +#define DP_QUERY_STREAM_ENC_STATUS_STATE_INACTIVE 1 +#define DP_QUERY_STREAM_ENC_STATUS_STATE_ACTIVE 2

/* DP 1.2 MST sideband reply types */ #define DP_SIDEBAND_REPLY_ACK 0x00 diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h index 8b9eb4db3381..371eef8798ad 100644 --- a/include/drm/drm_dp_mst_helper.h +++ b/include/drm/drm_dp_mst_helper.h @@ -313,6 +313,34 @@ struct drm_dp_remote_i2c_write_ack_reply { u8 port_number; };

+struct drm_dp_query_stream_enc_status_ack_reply {

• /* Bit[23:16]- Stream Id */
• u8 stream_id;
• /* Bit[15]- Signed */
• bool reply_signed;
• /* Bit[10:8]- Stream Output Sink Type */
• bool unauthorizable_device_present;
• bool legacy_device_present;
• bool query_capable_device_present;
• /* Bit[12:11]- Stream Output CP Type */
• bool hdcp_1x_device_present;
• bool hdcp_2x_device_present;
• /* Bit[4]- Stream Authentication */
• bool auth_completed;
• /* Bit[3]- Stream Encryption */
• bool encryption_enabled;
• /* Bit[2]- Stream Repeater Function Present */
• bool repeater_present;
• /* Bit[1:0]- Stream State */
• u8 state;

+};

#define DRM_DP_MAX_SDP_STREAMS 16 struct drm_dp_allocate_payload { @@ -374,6 +402,15 @@ struct drm_dp_remote_i2c_write { u8 *bytes; };

+struct drm_dp_query_stream_enc_status {

• u8 stream_id;
• u8 client_id[7]; /* 56-bit nonce */
• u8 stream_event;
• bool valid_stream_event;
• u8 stream_behavior;
• u8 valid_stream_behavior;

+};

/* this covers ENUM_RESOURCES, POWER_DOWN_PHY, POWER_UP_PHY */ struct drm_dp_port_number_req { u8 port_number; @@ -422,6 +459,8 @@ struct drm_dp_sideband_msg_req_body {

struct drm_dp_remote_i2c_read i2c_read;
struct drm_dp_remote_i2c_write i2c_write;

• struct drm_dp_query_stream_enc_status enc_status;
  

  } u;

};

@@ -444,6 +483,8 @@ struct drm_dp_sideband_msg_reply_body { struct drm_dp_remote_i2c_read_ack_reply remote_i2c_read_ack; struct drm_dp_remote_i2c_read_nak_reply remote_i2c_read_nack; struct drm_dp_remote_i2c_write_ack_reply remote_i2c_write_ack;

• struct drm_dp_query_stream_enc_status_ack_reply enc_status;
  

  } u;

};

@@ -808,6 +849,9 @@ drm_dp_atomic_release_vcpi_slots(struct drm_atomic_state *state, struct drm_dp_mst_port *port); int drm_dp_send_power_updown_phy(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, bool power_up); +int drm_dp_send_query_stream_enc_status(struct drm_dp_mst_topology_mgr *mgr,

• struct drm_dp_mst_port *port,
  

• struct drm_dp_query_stream_enc_status_ack_reply *status);
  

int __must_check drm_dp_mst_atomic_check(struct drm_atomic_state *state);

void drm_dp_mst_get_port_malloc(struct drm_dp_mst_port *port);

Sean Paul, Software Engineer, Google / Chromium OS

---

Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

On 2020-06-30 at 12:48:34 -0400, Sean Paul wrote:

On Tue, Jun 30, 2020 at 10:21 AM Anshuman Gupta anshuman.gupta@intel.com wrote:

...

On 2020-06-23 at 21:29:05 +0530, Sean Paul wrote: Hi Sean, I am new to DP MST stuff, I am looking to DP MST spec DP v1.2a. I have looked the entire series, i will take up this opportunity to review the series from HDCP over DP MST POV. I think theoretically this series should work or Gen12 as well, as DP MST streams are getting encrypted by QUERY_STREAM_ENCRYPTION_STATUS reply tranaction msg (generating Stream State Signature L’). I will test this on Gen12 H/W with DP MST support and will provide my inputs.

Meanwhile while going through DP MST v1.2a specs(Page 262) came to know about a DP irq vector LINK_SERVICE_IRQ_VECTOR_ESI0 (02005h), Bit 2 : STREAM_STATUS_CHANGED. When this bit set to ‘1’ indicates the source must re-check the Stream Status with the QUERY_STREAM_ENCRYPTION_STATUS message. Currently i feel this irq support is missing, do we require to support above IRQ vector for DP MST stream encryption.

Hi Anshuman, Thank you for your comments.

QUERY_STREAM_ENCRYPTION_STATUS is not necessary for HDCP 1.x, I added this as a safety check to ensure that the streams were being encrypted. As such, the existing integrity checks in place for DP are sufficient to satisfy spec. When HDCP 2.2 support is added for MST, handling QSES will need to be addressed to meet spec. Note also that we're not validating the QSES signature for the same reason.

Thanks sean for the explanation, overall patch looks good to me but i have couple of doubt see below.

Sean

...

Thanks, Anshuman Gupta.

...

From: Sean Paul seanpaul@chromium.org

Used to query whether an MST stream is encrypted or not.

Signed-off-by: Sean Paul seanpaul@chromium.org

Link: https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-14-sean@... #v4 Link: https://patchwork.freedesktop.org/patch/msgid/20200305201236.152307-15-sean@... #v5 Link: https://patchwork.freedesktop.org/patch/msgid/20200429195502.39919-15-sean@p... #v6

Changes in v4: -Added to the set Changes in v5: -None Changes in v6: -Use FIELD_PREP to generate request buffer bitfields (Lyude) -Add mst selftest and dump/decode_sideband_req for QSES (Lyude) Changes in v7:

-None

drivers/gpu/drm/drm_dp_mst_topology.c | 142 ++++++++++++++++++ .../drm/selftests/test-drm_dp_mst_helper.c | 17 +++ include/drm/drm_dp_helper.h | 3 + include/drm/drm_dp_mst_helper.h | 44 ++++++ 4 files changed, 206 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index b2f5a84b4cfb..fc68478eaeb4 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c @@ -20,11 +20,13 @@

• OF THIS SOFTWARE.

*/

+#include <linux/bitfield.h> #include <linux/delay.h> #include <linux/errno.h> #include <linux/i2c.h> #include <linux/init.h> #include <linux/kernel.h> +#include <linux/random.h> #include <linux/sched.h> #include <linux/seq_file.h> #include <linux/iopoll.h> @@ -419,6 +421,22 @@ drm_dp_encode_sideband_req(const struct drm_dp_sideband_msg_req_body *req, memcpy(&buf[idx], req->u.i2c_write.bytes, req->u.i2c_write.num_bytes); idx += req->u.i2c_write.num_bytes; break;

• case DP_QUERY_STREAM_ENC_STATUS: {
  

•         const struct drm_dp_query_stream_enc_status *msg;
  

•         msg = &req->u.enc_status;
  

•         buf[idx] = msg->stream_id;
  

•         idx++;
  

•         memcpy(&buf[idx], msg->client_id, sizeof(msg->client_id));
  

•         idx += sizeof(msg->client_id);
  

•         buf[idx] = 0;
  

•         buf[idx] |= FIELD_PREP(GENMASK(1, 0), msg->stream_event);
  

•         buf[idx] |= msg->valid_stream_event ? BIT(2) : 0;
  

•         buf[idx] |= FIELD_PREP(GENMASK(4, 3), msg->stream_behavior);
  

•         buf[idx] |= msg->valid_stream_behavior ? BIT(5) : 0;
  

•         idx++;
  

•         }
  

•         break;
  }
  raw->cur_len = idx;
  

} @@ -547,6 +565,20 @@ drm_dp_decode_sideband_req(const struct drm_dp_sideband_msg_tx *raw, return -ENOMEM; } break;

• case DP_QUERY_STREAM_ENC_STATUS:
  

•         req->u.enc_status.stream_id = buf[idx++];
  

•         for (i = 0; i < sizeof(req->u.enc_status.client_id); i++)
  

•                 req->u.enc_status.client_id[i] = buf[idx++];
  

•         req->u.enc_status.stream_event = FIELD_GET(GENMASK(1, 0),
  

•                                                    buf[idx]);
  

•         req->u.enc_status.valid_stream_event = FIELD_GET(BIT(2),
  

•                                                          buf[idx]);
  

•         req->u.enc_status.stream_behavior = FIELD_GET(GENMASK(4, 3),
  

•                                                       buf[idx]);
  

•         req->u.enc_status.valid_stream_behavior = FIELD_GET(BIT(5),
  

•                                                             buf[idx]);
  

•         break;
  }
  
  return 0;
  

@@ -625,6 +657,16 @@ drm_dp_dump_sideband_msg_req_body(const struct drm_dp_sideband_msg_req_body *req req->u.i2c_write.num_bytes, req->u.i2c_write.num_bytes, req->u.i2c_write.bytes); break;

• case DP_QUERY_STREAM_ENC_STATUS:
  

•         P("stream_id=%u client_id=%*ph stream_event=%x "
  

•           "valid_event=%d stream_behavior=%x valid_behavior=%d",
  

•           req->u.enc_status.stream_id,
  

•           (int)ARRAY_SIZE(req->u.enc_status.client_id),
  

•           req->u.enc_status.client_id, req->u.enc_status.stream_event,
  

•           req->u.enc_status.valid_stream_event,
  

•           req->u.enc_status.stream_behavior,
  

•           req->u.enc_status.valid_stream_behavior);
  

•         break;
  default:
          P("???\n");
          break;
  

@@ -925,6 +967,34 @@ static bool drm_dp_sideband_parse_power_updown_phy_ack(struct drm_dp_sideband_ms return true; }

+static bool +drm_dp_sideband_parse_query_stream_enc_status(

•                         struct drm_dp_sideband_msg_rx *raw,
  

•                         struct drm_dp_sideband_msg_reply_body *repmsg)
  

+{

• struct drm_dp_query_stream_enc_status_ack_reply *reply;
  

• reply = &repmsg->u.enc_status;
  

• reply->stream_id = raw->msg[3];
  

It seems msg[0] is not part of reply data, could you help me with pointers, where msg is formatted.

...

...

• reply->reply_signed = raw->msg[2] & BIT(0);
  

• reply->hdcp_1x_device_present = raw->msg[2] & BIT(3);
  

• reply->hdcp_2x_device_present = raw->msg[2] & BIT(4);
  

• reply->query_capable_device_present = raw->msg[2] & BIT(5);
  

• reply->legacy_device_present = raw->msg[2] & BIT(6);
  

• reply->unauthorizable_device_present = raw->msg[2] & BIT(7);
  

• reply->auth_completed = !!(raw->msg[1] & BIT(3));
  

• reply->encryption_enabled = !!(raw->msg[1] & BIT(4));
  

• reply->repeater_present = !!(raw->msg[1] & BIT(5));
  

• reply->state = (raw->msg[1] & GENMASK(7, 6)) >> 6;
  

• return true;
  

+}

static bool drm_dp_sideband_parse_reply(struct drm_dp_sideband_msg_rx *raw, struct drm_dp_sideband_msg_reply_body *msg) { @@ -959,6 +1029,8 @@ static bool drm_dp_sideband_parse_reply(struct drm_dp_sideband_msg_rx *raw, return drm_dp_sideband_parse_power_updown_phy_ack(raw, msg); case DP_CLEAR_PAYLOAD_ID_TABLE: return true; /* since there's nothing to parse */

• case DP_QUERY_STREAM_ENC_STATUS:
  

•         return drm_dp_sideband_parse_query_stream_enc_status(raw, msg);
  default:
          DRM_ERROR("Got unknown reply 0x%02x (%s)\n", msg->req_type,
                    drm_dp_mst_req_type_str(msg->req_type));
  

@@ -1109,6 +1181,25 @@ static void build_power_updown_phy(struct drm_dp_sideband_msg_tx *msg, msg->path_msg = true; }

+static int +build_query_stream_enc_status(struct drm_dp_sideband_msg_tx *msg, u8 stream_id,

•                       u8 *q_id)
  

+{

• struct drm_dp_sideband_msg_req_body req;
  

• req.req_type = DP_QUERY_STREAM_ENC_STATUS;
  

• req.u.enc_status.stream_id = stream_id;
  

• memcpy(req.u.enc_status.client_id, q_id,
  

•        sizeof(req.u.enc_status.client_id));
  

• req.u.enc_status.stream_event = 0;
  

• req.u.enc_status.valid_stream_event = false;
  

• req.u.enc_status.stream_behavior = 0;
  

• req.u.enc_status.valid_stream_behavior = false;
  

• drm_dp_encode_sideband_req(&req, msg);
  

• return 0;
  

+}

static int drm_dp_mst_assign_payload_id(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_vcpi *vcpi) { @@ -3137,6 +3228,57 @@ int drm_dp_send_power_updown_phy(struct drm_dp_mst_topology_mgr *mgr, } EXPORT_SYMBOL(drm_dp_send_power_updown_phy);

+int drm_dp_send_query_stream_enc_status(struct drm_dp_mst_topology_mgr *mgr,

•         struct drm_dp_mst_port *port,
  

•         struct drm_dp_query_stream_enc_status_ack_reply *status)
  

+{

• struct drm_dp_sideband_msg_tx *txmsg;
  

• u8 nonce[7];
  

• int len, ret;
  

• txmsg = kzalloc(sizeof(*txmsg), GFP_KERNEL);
  

• if (!txmsg)
  

•         return -ENOMEM;
  

• port = drm_dp_mst_topology_get_port_validated(mgr, port);
  

• if (!port) {
  

•         ret = -EINVAL;
  

•         goto out_get_port;
  

• }
  

• get_random_bytes(nonce, sizeof(nonce));
  

• /*
  

•  * "Source device targets the QUERY_STREAM_ENCRYPTION_STATUS message
  

•  *  transaction at the MST Branch device directly connected to the
  

•  *  Source"
  

•  */
  

• txmsg->dst = mgr->mst_primary;
  

• len = build_query_stream_enc_status(txmsg, port->vcpi.vcpi, nonce);
  

• drm_dp_queue_down_tx(mgr, txmsg);
  

• ret = drm_dp_mst_wait_tx_reply(mgr->mst_primary, txmsg);
  

• if (ret < 0) {
  

•         goto out;
  

• } else if (txmsg->reply.reply_type == DP_SIDEBAND_REPLY_NAK) {
  

•         DRM_DEBUG_KMS("query encryption status nak received\n");
  

•         ret = -ENXIO;
  

•         goto out;
  

• }
  

• ret = 0;
  

• memcpy(status, &txmsg->reply.u.enc_status, sizeof(*status));
  

+out:

• drm_dp_mst_topology_put_port(port);
  

+out_get_port:

• kfree(txmsg);
  

• return ret;
  

+} +EXPORT_SYMBOL(drm_dp_send_query_stream_enc_status);

static int drm_dp_create_payload_step1(struct drm_dp_mst_topology_mgr *mgr, int id, struct drm_dp_payload *payload) diff --git a/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c b/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c index bd990d178765..1d696ec001cf 100644 --- a/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c +++ b/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c @@ -5,6 +5,8 @@

#define PREFIX_STR "[drm_dp_mst_helper]"

+#include <linux/random.h>

#include <drm/drm_dp_mst_helper.h> #include <drm/drm_print.h>

@@ -237,6 +239,21 @@ int igt_dp_mst_sideband_msg_req_decode(void *unused) in.u.i2c_write.bytes = data; DO_TEST();

• in.req_type = DP_QUERY_STREAM_ENC_STATUS;
  

• in.u.enc_status.stream_id = 1;
  

• DO_TEST();
  

• get_random_bytes(in.u.enc_status.client_id,
  

•                  sizeof(in.u.enc_status.client_id));
  

• DO_TEST();
  

• in.u.enc_status.stream_event = 3;
  

• DO_TEST();
  

• in.u.enc_status.valid_stream_event = 0;
  

• DO_TEST();
  

• in.u.enc_status.stream_behavior = 3;
  

• DO_TEST();
  

• in.u.enc_status.valid_stream_behavior = 1;
  

• DO_TEST();
  

#undef DO_TEST return 0; } diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index e47dc22ebf50..e2d2df5e869e 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -1108,6 +1108,9 @@ #define DP_POWER_DOWN_PHY 0x25 #define DP_SINK_EVENT_NOTIFY 0x30 #define DP_QUERY_STREAM_ENC_STATUS 0x38 +#define DP_QUERY_STREAM_ENC_STATUS_STATE_NO_EXIST 0 +#define DP_QUERY_STREAM_ENC_STATUS_STATE_INACTIVE 1 +#define DP_QUERY_STREAM_ENC_STATUS_STATE_ACTIVE 2

/* DP 1.2 MST sideband reply types */ #define DP_SIDEBAND_REPLY_ACK 0x00 diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h index 8b9eb4db3381..371eef8798ad 100644 --- a/include/drm/drm_dp_mst_helper.h +++ b/include/drm/drm_dp_mst_helper.h @@ -313,6 +313,34 @@ struct drm_dp_remote_i2c_write_ack_reply { u8 port_number; };

+struct drm_dp_query_stream_enc_status_ack_reply {

• /* Bit[23:16]- Stream Id */
  

• u8 stream_id;
  

• /* Bit[15]- Signed */
  

• bool reply_signed;
  

• /* Bit[10:8]- Stream Output Sink Type */
  

• bool unauthorizable_device_present;
  

• bool legacy_device_present;
  

• bool query_capable_device_present;
  

• /* Bit[12:11]- Stream Output CP Type */
  

• bool hdcp_1x_device_present;
  

• bool hdcp_2x_device_present;
  

• /* Bit[4]- Stream Authentication */
  

• bool auth_completed;
  

• /* Bit[3]- Stream Encryption */
  

• bool encryption_enabled;
  

• /* Bit[2]- Stream Repeater Function Present */
  

• bool repeater_present;
  

• /* Bit[1:0]- Stream State */
  

• u8 state;
  

reply msg also has 20 byte of signature L' (HDCP 1.4), AFAIU it has lefted out for HDCP 2.2 implementation, which is of 32 bytes for HDCP 2.2. Please correct me if i am wrong here. Thanks, Anshuman Gupta.

...

...

+};

#define DRM_DP_MAX_SDP_STREAMS 16 struct drm_dp_allocate_payload { @@ -374,6 +402,15 @@ struct drm_dp_remote_i2c_write { u8 *bytes; };

+struct drm_dp_query_stream_enc_status {

• u8 stream_id;
  

• u8 client_id[7];        /* 56-bit nonce */
  

• u8 stream_event;
  

• bool valid_stream_event;
  

• u8 stream_behavior;
  

• u8 valid_stream_behavior;
  

+};

/* this covers ENUM_RESOURCES, POWER_DOWN_PHY, POWER_UP_PHY */ struct drm_dp_port_number_req { u8 port_number; @@ -422,6 +459,8 @@ struct drm_dp_sideband_msg_req_body {

          struct drm_dp_remote_i2c_read i2c_read;
          struct drm_dp_remote_i2c_write i2c_write;

•         struct drm_dp_query_stream_enc_status enc_status;
  } u;
  

};

@@ -444,6 +483,8 @@ struct drm_dp_sideband_msg_reply_body { struct drm_dp_remote_i2c_read_ack_reply remote_i2c_read_ack; struct drm_dp_remote_i2c_read_nak_reply remote_i2c_read_nack; struct drm_dp_remote_i2c_write_ack_reply remote_i2c_write_ack;

•         struct drm_dp_query_stream_enc_status_ack_reply enc_status;
  } u;
  

};

@@ -808,6 +849,9 @@ drm_dp_atomic_release_vcpi_slots(struct drm_atomic_state *state, struct drm_dp_mst_port *port); int drm_dp_send_power_updown_phy(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, bool power_up); +int drm_dp_send_query_stream_enc_status(struct drm_dp_mst_topology_mgr *mgr,

•         struct drm_dp_mst_port *port,
  

•         struct drm_dp_query_stream_enc_status_ack_reply *status);
  

int __must_check drm_dp_mst_atomic_check(struct drm_atomic_state *state);

void drm_dp_mst_get_port_malloc(struct drm_dp_mst_port *port);

Sean Paul, Software Engineer, Google / Chromium OS

---

Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

On Thu, Jul 9, 2020 at 9:09 AM Anshuman Gupta anshuman.gupta@intel.com wrote:

On 2020-07-02 at 20:07:36 +0530, Anshuman Gupta wrote:

...

On 2020-06-30 at 12:48:34 -0400, Sean Paul wrote:

...

On Tue, Jun 30, 2020 at 10:21 AM Anshuman Gupta anshuman.gupta@intel.com wrote:

...

On 2020-06-23 at 21:29:05 +0530, Sean Paul wrote: Hi Sean, I am new to DP MST stuff, I am looking to DP MST spec DP v1.2a. I have looked the entire series, i will take up this opportunity to review the series from HDCP over DP MST POV. I think theoretically this series should work or Gen12 as well, as DP MST streams are getting encrypted by QUERY_STREAM_ENCRYPTION_STATUS reply tranaction msg (generating Stream State Signature L’). I will test this on Gen12 H/W with DP MST support and will provide my inputs.

Meanwhile while going through DP MST v1.2a specs(Page 262) came to know about a DP irq vector LINK_SERVICE_IRQ_VECTOR_ESI0 (02005h), Bit 2 : STREAM_STATUS_CHANGED. When this bit set to ‘1’ indicates the source must re-check the Stream Status with the QUERY_STREAM_ENCRYPTION_STATUS message. Currently i feel this irq support is missing, do we require to support above IRQ vector for DP MST stream encryption.

Hi Anshuman, Thank you for your comments.

QUERY_STREAM_ENCRYPTION_STATUS is not necessary for HDCP 1.x, I added this as a safety check to ensure that the streams were being encrypted. As such, the existing integrity checks in place for DP are sufficient to satisfy spec. When HDCP 2.2 support is added for MST, handling QSES will need to be addressed to meet spec. Note also that we're not validating the QSES signature for the same reason.

Thanks sean for the explanation, overall patch looks good to me but i have couple of doubt see below.

...

Sean

...

Thanks, Anshuman Gupta.

...

From: Sean Paul seanpaul@chromium.org

Used to query whether an MST stream is encrypted or not.

Signed-off-by: Sean Paul seanpaul@chromium.org

Link: https://patchwork.freedesktop.org/patch/msgid/20200218220242.107265-14-sean@... #v4 Link: https://patchwork.freedesktop.org/patch/msgid/20200305201236.152307-15-sean@... #v5 Link: https://patchwork.freedesktop.org/patch/msgid/20200429195502.39919-15-sean@p... #v6

Changes in v4: -Added to the set Changes in v5: -None Changes in v6: -Use FIELD_PREP to generate request buffer bitfields (Lyude) -Add mst selftest and dump/decode_sideband_req for QSES (Lyude) Changes in v7:

-None

drivers/gpu/drm/drm_dp_mst_topology.c | 142 ++++++++++++++++++ .../drm/selftests/test-drm_dp_mst_helper.c | 17 +++ include/drm/drm_dp_helper.h | 3 + include/drm/drm_dp_mst_helper.h | 44 ++++++ 4 files changed, 206 insertions(+)

diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index b2f5a84b4cfb..fc68478eaeb4 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c @@ -20,11 +20,13 @@

• OF THIS SOFTWARE.

*/

+#include <linux/bitfield.h> #include <linux/delay.h> #include <linux/errno.h> #include <linux/i2c.h> #include <linux/init.h> #include <linux/kernel.h> +#include <linux/random.h> #include <linux/sched.h> #include <linux/seq_file.h> #include <linux/iopoll.h> @@ -419,6 +421,22 @@ drm_dp_encode_sideband_req(const struct drm_dp_sideband_msg_req_body *req, memcpy(&buf[idx], req->u.i2c_write.bytes, req->u.i2c_write.num_bytes); idx += req->u.i2c_write.num_bytes; break;

• case DP_QUERY_STREAM_ENC_STATUS: {
  

•         const struct drm_dp_query_stream_enc_status *msg;
  

•         msg = &req->u.enc_status;
  

•         buf[idx] = msg->stream_id;
  

•         idx++;
  

•         memcpy(&buf[idx], msg->client_id, sizeof(msg->client_id));
  

•         idx += sizeof(msg->client_id);
  

•         buf[idx] = 0;
  

•         buf[idx] |= FIELD_PREP(GENMASK(1, 0), msg->stream_event);
  

•         buf[idx] |= msg->valid_stream_event ? BIT(2) : 0;
  

•         buf[idx] |= FIELD_PREP(GENMASK(4, 3), msg->stream_behavior);
  

•         buf[idx] |= msg->valid_stream_behavior ? BIT(5) : 0;
  

•         idx++;
  

•         }
  

•         break;
  }
  raw->cur_len = idx;
  

} @@ -547,6 +565,20 @@ drm_dp_decode_sideband_req(const struct drm_dp_sideband_msg_tx *raw, return -ENOMEM; } break;

• case DP_QUERY_STREAM_ENC_STATUS:
  

•         req->u.enc_status.stream_id = buf[idx++];
  

•         for (i = 0; i < sizeof(req->u.enc_status.client_id); i++)
  

•                 req->u.enc_status.client_id[i] = buf[idx++];
  

•         req->u.enc_status.stream_event = FIELD_GET(GENMASK(1, 0),
  

•                                                    buf[idx]);
  

•         req->u.enc_status.valid_stream_event = FIELD_GET(BIT(2),
  

•                                                          buf[idx]);
  

•         req->u.enc_status.stream_behavior = FIELD_GET(GENMASK(4, 3),
  

•                                                       buf[idx]);
  

•         req->u.enc_status.valid_stream_behavior = FIELD_GET(BIT(5),
  

•                                                             buf[idx]);
  

•         break;
  }
  
  return 0;
  

@@ -625,6 +657,16 @@ drm_dp_dump_sideband_msg_req_body(const struct drm_dp_sideband_msg_req_body *req req->u.i2c_write.num_bytes, req->u.i2c_write.num_bytes, req->u.i2c_write.bytes); break;

• case DP_QUERY_STREAM_ENC_STATUS:
  

•         P("stream_id=%u client_id=%*ph stream_event=%x "
  

•           "valid_event=%d stream_behavior=%x valid_behavior=%d",
  

•           req->u.enc_status.stream_id,
  

•           (int)ARRAY_SIZE(req->u.enc_status.client_id),
  

•           req->u.enc_status.client_id, req->u.enc_status.stream_event,
  

•           req->u.enc_status.valid_stream_event,
  

•           req->u.enc_status.stream_behavior,
  

•           req->u.enc_status.valid_stream_behavior);
  

•         break;
  default:
          P("???\n");
          break;
  

@@ -925,6 +967,34 @@ static bool drm_dp_sideband_parse_power_updown_phy_ack(struct drm_dp_sideband_ms return true; }

+static bool +drm_dp_sideband_parse_query_stream_enc_status(

•                         struct drm_dp_sideband_msg_rx *raw,
  

•                         struct drm_dp_sideband_msg_reply_body *repmsg)
  

+{

• struct drm_dp_query_stream_enc_status_ack_reply *reply;
  

• reply = &repmsg->u.enc_status;
  

• reply->stream_id = raw->msg[3];
  

It seems msg[0] is not part of reply data, could you help me with pointers, where msg is formatted.

...

...

...

• reply->reply_signed = raw->msg[2] & BIT(0);
  

This whole patch looks good to me i could have given RB but i am having some concerns regarding parsing of bits here. reply_signed is 15th bit of reply message i.e MSB of msg[2] here. it seems bit parsing is in reverse order in all places.

...

...

...

...

• reply->hdcp_1x_device_present = raw->msg[2] & BIT(3);
  

• reply->hdcp_2x_device_present = raw->msg[2] & BIT(4);
  

But these two bits are not parse as reverse order, these are parse as similar in DP specs, hdcp_1x 11th bit (bit 3 of msg[2]), hdcp_2x 12th bit (bit 4 of msg[2]). Please correct me if i am wrong here.

I'm not really sure what to make of this field since when I connect a display which only supports HDCP 1.x (no HDCP 2.x), I get:

msg[2][4:3] = 01b

I've reproduced this with multiple hubs. I don't have an HDCP 2.x display, so I can't reproduce to see if the other bit lights up under those conditions.

We're not using these fields at the moment, so I suppose I can switch them around and leave a comment in case someone notices weirdness.

Sean

Thanks, Anshuman Gupta.

...

...

...

...

• reply->query_capable_device_present = raw->msg[2] & BIT(5);
  

• reply->legacy_device_present = raw->msg[2] & BIT(6);
  

• reply->unauthorizable_device_present = raw->msg[2] & BIT(7);
  

• reply->auth_completed = !!(raw->msg[1] & BIT(3));
  

...

...

...

...

• reply->encryption_enabled = !!(raw->msg[1] & BIT(4));
  

• reply->repeater_present = !!(raw->msg[1] & BIT(5));
  

• reply->state = (raw->msg[1] & GENMASK(7, 6)) >> 6;
  

• return true;
  

+}

static bool drm_dp_sideband_parse_reply(struct drm_dp_sideband_msg_rx *raw, struct drm_dp_sideband_msg_reply_body *msg) { @@ -959,6 +1029,8 @@ static bool drm_dp_sideband_parse_reply(struct drm_dp_sideband_msg_rx *raw, return drm_dp_sideband_parse_power_updown_phy_ack(raw, msg); case DP_CLEAR_PAYLOAD_ID_TABLE: return true; /* since there's nothing to parse */

• case DP_QUERY_STREAM_ENC_STATUS:
  

•         return drm_dp_sideband_parse_query_stream_enc_status(raw, msg);
  default:
          DRM_ERROR("Got unknown reply 0x%02x (%s)\n", msg->req_type,
                    drm_dp_mst_req_type_str(msg->req_type));
  

@@ -1109,6 +1181,25 @@ static void build_power_updown_phy(struct drm_dp_sideband_msg_tx *msg, msg->path_msg = true; }

+static int +build_query_stream_enc_status(struct drm_dp_sideband_msg_tx *msg, u8 stream_id,

•                       u8 *q_id)
  

+{

• struct drm_dp_sideband_msg_req_body req;
  

• req.req_type = DP_QUERY_STREAM_ENC_STATUS;
  

• req.u.enc_status.stream_id = stream_id;
  

• memcpy(req.u.enc_status.client_id, q_id,
  

•        sizeof(req.u.enc_status.client_id));
  

• req.u.enc_status.stream_event = 0;
  

• req.u.enc_status.valid_stream_event = false;
  

• req.u.enc_status.stream_behavior = 0;
  

• req.u.enc_status.valid_stream_behavior = false;
  

• drm_dp_encode_sideband_req(&req, msg);
  

• return 0;
  

+}

static int drm_dp_mst_assign_payload_id(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_vcpi *vcpi) { @@ -3137,6 +3228,57 @@ int drm_dp_send_power_updown_phy(struct drm_dp_mst_topology_mgr *mgr, } EXPORT_SYMBOL(drm_dp_send_power_updown_phy);

+int drm_dp_send_query_stream_enc_status(struct drm_dp_mst_topology_mgr *mgr,

•         struct drm_dp_mst_port *port,
  

•         struct drm_dp_query_stream_enc_status_ack_reply *status)
  

+{

• struct drm_dp_sideband_msg_tx *txmsg;
  

• u8 nonce[7];
  

• int len, ret;
  

• txmsg = kzalloc(sizeof(*txmsg), GFP_KERNEL);
  

• if (!txmsg)
  

•         return -ENOMEM;
  

• port = drm_dp_mst_topology_get_port_validated(mgr, port);
  

• if (!port) {
  

•         ret = -EINVAL;
  

•         goto out_get_port;
  

• }
  

• get_random_bytes(nonce, sizeof(nonce));
  

• /*
  

•  * "Source device targets the QUERY_STREAM_ENCRYPTION_STATUS message
  

•  *  transaction at the MST Branch device directly connected to the
  

•  *  Source"
  

•  */
  

• txmsg->dst = mgr->mst_primary;
  

• len = build_query_stream_enc_status(txmsg, port->vcpi.vcpi, nonce);
  

• drm_dp_queue_down_tx(mgr, txmsg);
  

• ret = drm_dp_mst_wait_tx_reply(mgr->mst_primary, txmsg);
  

• if (ret < 0) {
  

•         goto out;
  

• } else if (txmsg->reply.reply_type == DP_SIDEBAND_REPLY_NAK) {
  

•         DRM_DEBUG_KMS("query encryption status nak received\n");
  

•         ret = -ENXIO;
  

•         goto out;
  

• }
  

• ret = 0;
  

• memcpy(status, &txmsg->reply.u.enc_status, sizeof(*status));
  

+out:

• drm_dp_mst_topology_put_port(port);
  

+out_get_port:

• kfree(txmsg);
  

• return ret;
  

+} +EXPORT_SYMBOL(drm_dp_send_query_stream_enc_status);

static int drm_dp_create_payload_step1(struct drm_dp_mst_topology_mgr *mgr, int id, struct drm_dp_payload *payload) diff --git a/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c b/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c index bd990d178765..1d696ec001cf 100644 --- a/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c +++ b/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c @@ -5,6 +5,8 @@

#define PREFIX_STR "[drm_dp_mst_helper]"

+#include <linux/random.h>

#include <drm/drm_dp_mst_helper.h> #include <drm/drm_print.h>

@@ -237,6 +239,21 @@ int igt_dp_mst_sideband_msg_req_decode(void *unused) in.u.i2c_write.bytes = data; DO_TEST();

• in.req_type = DP_QUERY_STREAM_ENC_STATUS;
  

• in.u.enc_status.stream_id = 1;
  

• DO_TEST();
  

• get_random_bytes(in.u.enc_status.client_id,
  

•                  sizeof(in.u.enc_status.client_id));
  

• DO_TEST();
  

• in.u.enc_status.stream_event = 3;
  

• DO_TEST();
  

• in.u.enc_status.valid_stream_event = 0;
  

• DO_TEST();
  

• in.u.enc_status.stream_behavior = 3;
  

• DO_TEST();
  

• in.u.enc_status.valid_stream_behavior = 1;
  

• DO_TEST();
  

#undef DO_TEST return 0; } diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index e47dc22ebf50..e2d2df5e869e 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -1108,6 +1108,9 @@ #define DP_POWER_DOWN_PHY 0x25 #define DP_SINK_EVENT_NOTIFY 0x30 #define DP_QUERY_STREAM_ENC_STATUS 0x38 +#define DP_QUERY_STREAM_ENC_STATUS_STATE_NO_EXIST 0 +#define DP_QUERY_STREAM_ENC_STATUS_STATE_INACTIVE 1 +#define DP_QUERY_STREAM_ENC_STATUS_STATE_ACTIVE 2

/* DP 1.2 MST sideband reply types */ #define DP_SIDEBAND_REPLY_ACK 0x00 diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h index 8b9eb4db3381..371eef8798ad 100644 --- a/include/drm/drm_dp_mst_helper.h +++ b/include/drm/drm_dp_mst_helper.h @@ -313,6 +313,34 @@ struct drm_dp_remote_i2c_write_ack_reply { u8 port_number; };

+struct drm_dp_query_stream_enc_status_ack_reply {

• /* Bit[23:16]- Stream Id */
  

• u8 stream_id;
  

• /* Bit[15]- Signed */
  

• bool reply_signed;
  

• /* Bit[10:8]- Stream Output Sink Type */
  

• bool unauthorizable_device_present;
  

• bool legacy_device_present;
  

• bool query_capable_device_present;
  

• /* Bit[12:11]- Stream Output CP Type */
  

• bool hdcp_1x_device_present;
  

• bool hdcp_2x_device_present;
  

• /* Bit[4]- Stream Authentication */
  

• bool auth_completed;
  

• /* Bit[3]- Stream Encryption */
  

• bool encryption_enabled;
  

• /* Bit[2]- Stream Repeater Function Present */
  

• bool repeater_present;
  

• /* Bit[1:0]- Stream State */
  

• u8 state;
  

reply msg also has 20 byte of signature L' (HDCP 1.4), AFAIU it has lefted out for HDCP 2.2 implementation, which is of 32 bytes for HDCP 2.2. Please correct me if i am wrong here. Thanks, Anshuman Gupta.

...

...

...

+};

#define DRM_DP_MAX_SDP_STREAMS 16 struct drm_dp_allocate_payload { @@ -374,6 +402,15 @@ struct drm_dp_remote_i2c_write { u8 *bytes; };

+struct drm_dp_query_stream_enc_status {

• u8 stream_id;
  

• u8 client_id[7];        /* 56-bit nonce */
  

• u8 stream_event;
  

• bool valid_stream_event;
  

• u8 stream_behavior;
  

• u8 valid_stream_behavior;
  

+};

/* this covers ENUM_RESOURCES, POWER_DOWN_PHY, POWER_UP_PHY */ struct drm_dp_port_number_req { u8 port_number; @@ -422,6 +459,8 @@ struct drm_dp_sideband_msg_req_body {

          struct drm_dp_remote_i2c_read i2c_read;
          struct drm_dp_remote_i2c_write i2c_write;

•         struct drm_dp_query_stream_enc_status enc_status;
  } u;
  

};

@@ -444,6 +483,8 @@ struct drm_dp_sideband_msg_reply_body { struct drm_dp_remote_i2c_read_ack_reply remote_i2c_read_ack; struct drm_dp_remote_i2c_read_nak_reply remote_i2c_read_nack; struct drm_dp_remote_i2c_write_ack_reply remote_i2c_write_ack;

•         struct drm_dp_query_stream_enc_status_ack_reply enc_status;
  } u;
  

};

@@ -808,6 +849,9 @@ drm_dp_atomic_release_vcpi_slots(struct drm_atomic_state *state, struct drm_dp_mst_port *port); int drm_dp_send_power_updown_phy(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, bool power_up); +int drm_dp_send_query_stream_enc_status(struct drm_dp_mst_topology_mgr *mgr,

•         struct drm_dp_mst_port *port,
  

•         struct drm_dp_query_stream_enc_status_ack_reply *status);
  

int __must_check drm_dp_mst_atomic_check(struct drm_atomic_state *state);

void drm_dp_mst_get_port_malloc(struct drm_dp_mst_port *port);

Sean Paul, Software Engineer, Google / Chromium OS

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