Add support for exynos5420 hdmi subsystem. It adds compatible strings for exynos5420 and Changes the drivers as per IP modifications.
This set is based on drm-next branch of Inki Dae's tree at http://git.kernel.org/cgit/linux/kernel/git/daeinki/drm-exynos.git.
Rahul Sharma (9): drm/exynos: use SoC name to identify hdmi version drm/exynos: rename compatible strings for hdmi subsystem drm/exynos: add support for exynos5420 hdmi drm/exynos: add support for exynos5420 hdmiphy drm/exynos: add support for exynos5420 mixer drm/exynos: fix interlace resolutions for exynos5420 drm/exynos: use of_get_named_gpio to get hdmi hpd gpio ARM/dts: add phy property to exynos5250 hdmi dt node ARM/dts: update device tree binding documentation for hdmi susbsystem
.../devicetree/bindings/video/exynos_hdmi.txt | 25 +- .../devicetree/bindings/video/exynos_hdmiddc.txt | 4 +- .../devicetree/bindings/video/exynos_hdmiphy.txt | 12 +- .../devicetree/bindings/video/exynos_mixer.txt | 14 +- arch/arm/boot/dts/cros5250-common.dtsi | 4 +- arch/arm/boot/dts/exynos5250-smdk5250.dts | 7 +- arch/arm/boot/dts/exynos5250.dtsi | 4 +- drivers/gpu/drm/exynos/exynos_ddc.c | 2 +- drivers/gpu/drm/exynos/exynos_hdmi.c | 544 ++++++++++++++------ drivers/gpu/drm/exynos/exynos_hdmiphy.c | 2 +- drivers/gpu/drm/exynos/exynos_mixer.c | 61 ++- drivers/gpu/drm/exynos/regs-hdmi.h | 78 +-- drivers/gpu/drm/exynos/regs-mixer.h | 7 + 13 files changed, 526 insertions(+), 238 deletions(-)
Exynos hdmi IP version is named after hdmi specification version i.e. 1.3 and 1.4. This versioning mechanism is not sufficient to handle the diversity in the hdmi/phy IPs which are present across the exynos SoC family.
This patch changes the hdmi version to the name of the SoC in which the IP was introduced for the first time. Same version is applicable to all subsequent SoCs having the same IP version.
Exynos4210 has 1.3 HDMI, i2c mapped phy with configuration set. Exynos5250 has 1.4 HDMI, i2c mapped phy with configuration set. Exynos5420 has 1.4 HDMI, Platform Bus mapped phy with configuration set.
Based on the HDMI IP version we cannot decide to pick Exynos5250 phy conf and use i2c for data transfer or Exynos5420 phy confs and platform bus calls for communication.
Signed-off-by: Rahul Sharma rahul.sharma@samsung.com --- drivers/gpu/drm/exynos/exynos_hdmi.c | 249 +++++++++++++++++----------------- drivers/gpu/drm/exynos/regs-hdmi.h | 78 +++++------ 2 files changed, 164 insertions(+), 163 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c index 75a6bf3..9384ffc 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c @@ -73,9 +73,9 @@ enum HDMI_PACKET_TYPE { HDMI_PACKET_TYPE_AUI = HDMI_PACKET_TYPE_INFOFRAME + 4 };
-enum hdmi_type { - HDMI_TYPE13, - HDMI_TYPE14, +enum hdmi_version { + HDMI_VER_EXYNOS4210, + HDMI_VER_EXYNOS4212, };
struct hdmi_resources { @@ -109,7 +109,7 @@ struct hdmi_tg_regs { u8 tg_3d[1]; };
-struct hdmi_v13_core_regs { +struct hdmi_4210_core_regs { u8 h_blank[2]; u8 v_blank[3]; u8 h_v_line[3]; @@ -122,7 +122,7 @@ struct hdmi_v13_core_regs { u8 v_sync_gen3[3]; };
-struct hdmi_v14_core_regs { +struct hdmi_4212_core_regs { u8 h_blank[2]; u8 v2_blank[2]; u8 v1_blank[2]; @@ -161,13 +161,13 @@ struct hdmi_v14_core_regs { u8 vact_space_6[2]; };
-struct hdmi_v13_conf { - struct hdmi_v13_core_regs core; +struct hdmi_4210_conf { + struct hdmi_4210_core_regs core; struct hdmi_tg_regs tg; };
-struct hdmi_v14_conf { - struct hdmi_v14_core_regs core; +struct hdmi_4212_conf { + struct hdmi_4212_core_regs core; struct hdmi_tg_regs tg; };
@@ -175,8 +175,8 @@ struct hdmi_conf_regs { int pixel_clock; int cea_video_id; union { - struct hdmi_v13_conf v13_conf; - struct hdmi_v14_conf v14_conf; + struct hdmi_4210_conf v4210_conf; + struct hdmi_4212_conf v4212_conf; } conf; };
@@ -203,7 +203,7 @@ struct hdmi_context {
int hpd_gpio;
- enum hdmi_type type; + enum hdmi_version version; };
struct hdmiphy_config { @@ -212,7 +212,7 @@ struct hdmiphy_config { };
/* list of phy config settings */ -static const struct hdmiphy_config hdmiphy_v13_configs[] = { +static const struct hdmiphy_config hdmiphy_4210_configs[] = { { .pixel_clock = 27000000, .conf = { @@ -260,7 +260,7 @@ static const struct hdmiphy_config hdmiphy_v13_configs[] = { }, };
-static const struct hdmiphy_config hdmiphy_v14_configs[] = { +static const struct hdmiphy_config hdmiphy_4212_configs[] = { { .pixel_clock = 25200000, .conf = { @@ -413,7 +413,7 @@ static inline void hdmi_phy_pow_ctrl_reg_writemask(struct hdmi_context *hdata, writel(value, hdata->phy_pow_ctrl_reg); }
-static void hdmi_v13_regs_dump(struct hdmi_context *hdata, char *prefix) +static void hdmi_4210_regs_dump(struct hdmi_context *hdata, char *prefix) { #define DUMPREG(reg_id) \ DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \ @@ -422,50 +422,50 @@ static void hdmi_v13_regs_dump(struct hdmi_context *hdata, char *prefix) DUMPREG(HDMI_INTC_FLAG); DUMPREG(HDMI_INTC_CON); DUMPREG(HDMI_HPD_STATUS); - DUMPREG(HDMI_V13_PHY_RSTOUT); - DUMPREG(HDMI_V13_PHY_VPLL); - DUMPREG(HDMI_V13_PHY_CMU); - DUMPREG(HDMI_V13_CORE_RSTOUT); + DUMPREG(HDMI_4210_PHY_RSTOUT); + DUMPREG(HDMI_4210_PHY_VPLL); + DUMPREG(HDMI_4210_PHY_CMU); + DUMPREG(HDMI_4210_CORE_RSTOUT);
DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix); DUMPREG(HDMI_CON_0); DUMPREG(HDMI_CON_1); DUMPREG(HDMI_CON_2); DUMPREG(HDMI_SYS_STATUS); - DUMPREG(HDMI_V13_PHY_STATUS); + DUMPREG(HDMI_4210_PHY_STATUS); DUMPREG(HDMI_STATUS_EN); DUMPREG(HDMI_HPD); DUMPREG(HDMI_MODE_SEL); - DUMPREG(HDMI_V13_HPD_GEN); - DUMPREG(HDMI_V13_DC_CONTROL); - DUMPREG(HDMI_V13_VIDEO_PATTERN_GEN); + DUMPREG(HDMI_4210_HPD_GEN); + DUMPREG(HDMI_4210_DC_CONTROL); + DUMPREG(HDMI_4210_VIDEO_PATTERN_GEN);
DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix); DUMPREG(HDMI_H_BLANK_0); DUMPREG(HDMI_H_BLANK_1); - DUMPREG(HDMI_V13_V_BLANK_0); - DUMPREG(HDMI_V13_V_BLANK_1); - DUMPREG(HDMI_V13_V_BLANK_2); - DUMPREG(HDMI_V13_H_V_LINE_0); - DUMPREG(HDMI_V13_H_V_LINE_1); - DUMPREG(HDMI_V13_H_V_LINE_2); + DUMPREG(HDMI_4210_V_BLANK_0); + DUMPREG(HDMI_4210_V_BLANK_1); + DUMPREG(HDMI_4210_V_BLANK_2); + DUMPREG(HDMI_4210_H_V_LINE_0); + DUMPREG(HDMI_4210_H_V_LINE_1); + DUMPREG(HDMI_4210_H_V_LINE_2); DUMPREG(HDMI_VSYNC_POL); DUMPREG(HDMI_INT_PRO_MODE); - DUMPREG(HDMI_V13_V_BLANK_F_0); - DUMPREG(HDMI_V13_V_BLANK_F_1); - DUMPREG(HDMI_V13_V_BLANK_F_2); - DUMPREG(HDMI_V13_H_SYNC_GEN_0); - DUMPREG(HDMI_V13_H_SYNC_GEN_1); - DUMPREG(HDMI_V13_H_SYNC_GEN_2); - DUMPREG(HDMI_V13_V_SYNC_GEN_1_0); - DUMPREG(HDMI_V13_V_SYNC_GEN_1_1); - DUMPREG(HDMI_V13_V_SYNC_GEN_1_2); - DUMPREG(HDMI_V13_V_SYNC_GEN_2_0); - DUMPREG(HDMI_V13_V_SYNC_GEN_2_1); - DUMPREG(HDMI_V13_V_SYNC_GEN_2_2); - DUMPREG(HDMI_V13_V_SYNC_GEN_3_0); - DUMPREG(HDMI_V13_V_SYNC_GEN_3_1); - DUMPREG(HDMI_V13_V_SYNC_GEN_3_2); + DUMPREG(HDMI_4210_V_BLANK_F_0); + DUMPREG(HDMI_4210_V_BLANK_F_1); + DUMPREG(HDMI_4210_V_BLANK_F_2); + DUMPREG(HDMI_4210_H_SYNC_GEN_0); + DUMPREG(HDMI_4210_H_SYNC_GEN_1); + DUMPREG(HDMI_4210_H_SYNC_GEN_2); + DUMPREG(HDMI_4210_V_SYNC_GEN_1_0); + DUMPREG(HDMI_4210_V_SYNC_GEN_1_1); + DUMPREG(HDMI_4210_V_SYNC_GEN_1_2); + DUMPREG(HDMI_4210_V_SYNC_GEN_2_0); + DUMPREG(HDMI_4210_V_SYNC_GEN_2_1); + DUMPREG(HDMI_4210_V_SYNC_GEN_2_2); + DUMPREG(HDMI_4210_V_SYNC_GEN_3_0); + DUMPREG(HDMI_4210_V_SYNC_GEN_3_1); + DUMPREG(HDMI_4210_V_SYNC_GEN_3_2);
DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix); DUMPREG(HDMI_TG_CMD); @@ -500,7 +500,7 @@ static void hdmi_v13_regs_dump(struct hdmi_context *hdata, char *prefix) #undef DUMPREG }
-static void hdmi_v14_regs_dump(struct hdmi_context *hdata, char *prefix) +static void hdmi_4212_regs_dump(struct hdmi_context *hdata, char *prefix) { int i;
@@ -669,10 +669,10 @@ static void hdmi_v14_regs_dump(struct hdmi_context *hdata, char *prefix)
static void hdmi_regs_dump(struct hdmi_context *hdata, char *prefix) { - if (hdata->type == HDMI_TYPE13) - hdmi_v13_regs_dump(hdata, prefix); + if (hdata->version == HDMI_VER_EXYNOS4210) + hdmi_4210_regs_dump(hdata, prefix); else - hdmi_v14_regs_dump(hdata, prefix); + hdmi_4212_regs_dump(hdata, prefix); }
static u8 hdmi_chksum(struct hdmi_context *hdata, @@ -789,12 +789,12 @@ static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock)
DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
- if (hdata->type == HDMI_TYPE13) { - confs = hdmiphy_v13_configs; - count = ARRAY_SIZE(hdmiphy_v13_configs); - } else if (hdata->type == HDMI_TYPE14) { - confs = hdmiphy_v14_configs; - count = ARRAY_SIZE(hdmiphy_v14_configs); + if (hdata->version == HDMI_VER_EXYNOS4210) { + confs = hdmiphy_4210_configs; + count = ARRAY_SIZE(hdmiphy_4210_configs); + } else if (hdata->version == HDMI_VER_EXYNOS4212) { + confs = hdmiphy_4212_configs; + count = ARRAY_SIZE(hdmiphy_4212_configs); } else return -EINVAL;
@@ -882,8 +882,8 @@ static void hdmi_reg_acr(struct hdmi_context *hdata, u8 *acr) hdmi_reg_writeb(hdata, HDMI_ACR_CTS1, acr[2]); hdmi_reg_writeb(hdata, HDMI_ACR_CTS2, acr[1]);
- if (hdata->type == HDMI_TYPE13) - hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 4); + if (hdata->version == HDMI_VER_EXYNOS4210) + hdmi_reg_writeb(hdata, HDMI_4210_ACR_CON, 4); else hdmi_reg_writeb(hdata, HDMI_ACR_CON, 4); } @@ -986,8 +986,8 @@ static void hdmi_conf_reset(struct hdmi_context *hdata) { u32 reg;
- if (hdata->type == HDMI_TYPE13) - reg = HDMI_V13_CORE_RSTOUT; + if (hdata->version == HDMI_VER_EXYNOS4210) + reg = HDMI_4210_CORE_RSTOUT; else reg = HDMI_CORE_RSTOUT;
@@ -1020,21 +1020,21 @@ static void hdmi_conf_init(struct hdmi_context *hdata) HDMI_VID_PREAMBLE_DIS | HDMI_GUARD_BAND_DIS); }
- if (hdata->type == HDMI_TYPE13) { + if (hdata->version == HDMI_VER_EXYNOS4210) { /* choose bluescreen (fecal) color */ - hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_0, 0x12); - hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_1, 0x34); - hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_2, 0x56); + hdmi_reg_writeb(hdata, HDMI_4210_BLUE_SCREEN_0, 0x12); + hdmi_reg_writeb(hdata, HDMI_4210_BLUE_SCREEN_1, 0x34); + hdmi_reg_writeb(hdata, HDMI_4210_BLUE_SCREEN_2, 0x56);
/* enable AVI packet every vsync, fixes purple line problem */ - hdmi_reg_writeb(hdata, HDMI_V13_AVI_CON, 0x02); + hdmi_reg_writeb(hdata, HDMI_4210_AVI_CON, 0x02); /* force RGB, look to CEA-861-D, table 7 for more detail */ - hdmi_reg_writeb(hdata, HDMI_V13_AVI_BYTE(0), 0 << 5); + hdmi_reg_writeb(hdata, HDMI_4210_AVI_BYTE(0), 0 << 5); hdmi_reg_writemask(hdata, HDMI_CON_1, 0x10 << 5, 0x11 << 5);
- hdmi_reg_writeb(hdata, HDMI_V13_SPD_CON, 0x02); - hdmi_reg_writeb(hdata, HDMI_V13_AUI_CON, 0x02); - hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 0x04); + hdmi_reg_writeb(hdata, HDMI_4210_SPD_CON, 0x02); + hdmi_reg_writeb(hdata, HDMI_4210_AUI_CON, 0x02); + hdmi_reg_writeb(hdata, HDMI_4210_ACR_CON, 0x04); } else { infoframe.type = HDMI_PACKET_TYPE_AVI; infoframe.ver = HDMI_AVI_VERSION; @@ -1051,39 +1051,39 @@ static void hdmi_conf_init(struct hdmi_context *hdata) } }
-static void hdmi_v13_mode_apply(struct hdmi_context *hdata) +static void hdmi_4210_mode_apply(struct hdmi_context *hdata) { - const struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v13_conf.tg; - const struct hdmi_v13_core_regs *core = - &hdata->mode_conf.conf.v13_conf.core; + const struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v4210_conf.tg; + const struct hdmi_4210_core_regs *core = + &hdata->mode_conf.conf.v4210_conf.core; int tries;
/* setting core registers */ hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]); hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]); - hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_0, core->v_blank[0]); - hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_1, core->v_blank[1]); - hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_2, core->v_blank[2]); - hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_0, core->h_v_line[0]); - hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_1, core->h_v_line[1]); - hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_2, core->h_v_line[2]); + hdmi_reg_writeb(hdata, HDMI_4210_V_BLANK_0, core->v_blank[0]); + hdmi_reg_writeb(hdata, HDMI_4210_V_BLANK_1, core->v_blank[1]); + hdmi_reg_writeb(hdata, HDMI_4210_V_BLANK_2, core->v_blank[2]); + hdmi_reg_writeb(hdata, HDMI_4210_H_V_LINE_0, core->h_v_line[0]); + hdmi_reg_writeb(hdata, HDMI_4210_H_V_LINE_1, core->h_v_line[1]); + hdmi_reg_writeb(hdata, HDMI_4210_H_V_LINE_2, core->h_v_line[2]); hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]); hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]); - hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_0, core->v_blank_f[0]); - hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_1, core->v_blank_f[1]); - hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_2, core->v_blank_f[2]); - hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_0, core->h_sync_gen[0]); - hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_1, core->h_sync_gen[1]); - hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_2, core->h_sync_gen[2]); - hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_0, core->v_sync_gen1[0]); - hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_1, core->v_sync_gen1[1]); - hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_2, core->v_sync_gen1[2]); - hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_0, core->v_sync_gen2[0]); - hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_1, core->v_sync_gen2[1]); - hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_2, core->v_sync_gen2[2]); - hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_0, core->v_sync_gen3[0]); - hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_1, core->v_sync_gen3[1]); - hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_2, core->v_sync_gen3[2]); + hdmi_reg_writeb(hdata, HDMI_4210_V_BLANK_F_0, core->v_blank_f[0]); + hdmi_reg_writeb(hdata, HDMI_4210_V_BLANK_F_1, core->v_blank_f[1]); + hdmi_reg_writeb(hdata, HDMI_4210_V_BLANK_F_2, core->v_blank_f[2]); + hdmi_reg_writeb(hdata, HDMI_4210_H_SYNC_GEN_0, core->h_sync_gen[0]); + hdmi_reg_writeb(hdata, HDMI_4210_H_SYNC_GEN_1, core->h_sync_gen[1]); + hdmi_reg_writeb(hdata, HDMI_4210_H_SYNC_GEN_2, core->h_sync_gen[2]); + hdmi_reg_writeb(hdata, HDMI_4210_V_SYNC_GEN_1_0, core->v_sync_gen1[0]); + hdmi_reg_writeb(hdata, HDMI_4210_V_SYNC_GEN_1_1, core->v_sync_gen1[1]); + hdmi_reg_writeb(hdata, HDMI_4210_V_SYNC_GEN_1_2, core->v_sync_gen1[2]); + hdmi_reg_writeb(hdata, HDMI_4210_V_SYNC_GEN_2_0, core->v_sync_gen2[0]); + hdmi_reg_writeb(hdata, HDMI_4210_V_SYNC_GEN_2_1, core->v_sync_gen2[1]); + hdmi_reg_writeb(hdata, HDMI_4210_V_SYNC_GEN_2_2, core->v_sync_gen2[2]); + hdmi_reg_writeb(hdata, HDMI_4210_V_SYNC_GEN_3_0, core->v_sync_gen3[0]); + hdmi_reg_writeb(hdata, HDMI_4210_V_SYNC_GEN_3_1, core->v_sync_gen3[1]); + hdmi_reg_writeb(hdata, HDMI_4210_V_SYNC_GEN_3_2, core->v_sync_gen3[2]); /* Timing generator registers */ hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz[0]); hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz[1]); @@ -1116,7 +1116,7 @@ static void hdmi_v13_mode_apply(struct hdmi_context *hdata)
/* waiting for HDMIPHY's PLL to get to steady state */ for (tries = 100; tries; --tries) { - u32 val = hdmi_reg_read(hdata, HDMI_V13_PHY_STATUS); + u32 val = hdmi_reg_read(hdata, HDMI_4210_PHY_STATUS); if (val & HDMI_PHY_STATUS_READY) break; usleep_range(1000, 2000); @@ -1140,11 +1140,11 @@ static void hdmi_v13_mode_apply(struct hdmi_context *hdata) hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN); }
-static void hdmi_v14_mode_apply(struct hdmi_context *hdata) +static void hdmi_4212_mode_apply(struct hdmi_context *hdata) { - const struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v14_conf.tg; - const struct hdmi_v14_core_regs *core = - &hdata->mode_conf.conf.v14_conf.core; + const struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v4212_conf.tg; + const struct hdmi_4212_core_regs *core = + &hdata->mode_conf.conf.v4212_conf.core; int tries;
/* setting core registers */ @@ -1309,10 +1309,10 @@ static void hdmi_v14_mode_apply(struct hdmi_context *hdata)
static void hdmi_mode_apply(struct hdmi_context *hdata) { - if (hdata->type == HDMI_TYPE13) - hdmi_v13_mode_apply(hdata); + if (hdata->version == HDMI_VER_EXYNOS4210) + hdmi_4210_mode_apply(hdata); else - hdmi_v14_mode_apply(hdata); + hdmi_4212_mode_apply(hdata); }
static void hdmiphy_conf_reset(struct hdmi_context *hdata) @@ -1331,8 +1331,8 @@ static void hdmiphy_conf_reset(struct hdmi_context *hdata) if (hdata->hdmiphy_port) i2c_master_send(hdata->hdmiphy_port, buffer, 2);
- if (hdata->type == HDMI_TYPE13) - reg = HDMI_V13_PHY_RSTOUT; + if (hdata->version == HDMI_VER_EXYNOS4210) + reg = HDMI_4210_PHY_RSTOUT; else reg = HDMI_PHY_RSTOUT;
@@ -1347,7 +1347,7 @@ static void hdmiphy_poweron(struct hdmi_context *hdata) { DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
- if (hdata->type == HDMI_TYPE14) + if (hdata->version != HDMI_VER_EXYNOS4210) hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, 0, HDMI_PHY_POWER_OFF_EN); } @@ -1356,7 +1356,7 @@ static void hdmiphy_poweroff(struct hdmi_context *hdata) { DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
- if (hdata->type == HDMI_TYPE14) + if (hdata->version != HDMI_VER_EXYNOS4210) hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, ~0, HDMI_PHY_POWER_OFF_EN); } @@ -1382,10 +1382,10 @@ static void hdmiphy_conf_apply(struct hdmi_context *hdata) return; }
- if (hdata->type == HDMI_TYPE13) - hdmiphy_data = hdmiphy_v13_configs[i].conf; + if (hdata->version == HDMI_VER_EXYNOS4210) + hdmiphy_data = hdmiphy_4210_configs[i].conf; else - hdmiphy_data = hdmiphy_v14_configs[i].conf; + hdmiphy_data = hdmiphy_4212_configs[i].conf;
memcpy(buffer, hdmiphy_data, 32); ret = i2c_master_send(hdata->hdmiphy_port, buffer, 32); @@ -1446,11 +1446,12 @@ static void hdmi_set_reg(u8 *reg_pair, int num_bytes, u32 value) reg_pair[i] = (value >> (8 * i)) & 0xff; }
-static void hdmi_v13_mode_set(struct hdmi_context *hdata, +static void hdmi_4210_mode_set(struct hdmi_context *hdata, struct drm_display_mode *m) { - struct hdmi_v13_core_regs *core = &hdata->mode_conf.conf.v13_conf.core; - struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v13_conf.tg; + struct hdmi_4210_core_regs *core = + &hdata->mode_conf.conf.v4210_conf.core; + struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v4210_conf.tg; unsigned int val;
hdata->mode_conf.cea_video_id = @@ -1542,12 +1543,12 @@ static void hdmi_v13_mode_set(struct hdmi_context *hdata, hdmi_set_reg(tg->tg_3d, 1, 0x0); /* Not used */ }
-static void hdmi_v14_mode_set(struct hdmi_context *hdata, +static void hdmi_4212_mode_set(struct hdmi_context *hdata, struct drm_display_mode *m) { - struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v14_conf.tg; - struct hdmi_v14_core_regs *core = - &hdata->mode_conf.conf.v14_conf.core; + struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v4212_conf.tg; + struct hdmi_4212_core_regs *core = + &hdata->mode_conf.conf.v4212_conf.core;
hdata->mode_conf.cea_video_id = drm_match_cea_mode((struct drm_display_mode *)m); @@ -1661,10 +1662,10 @@ static void hdmi_mode_set(void *ctx, struct drm_display_mode *mode) m->vrefresh, (m->flags & DRM_MODE_FLAG_INTERLACE) ? "INTERLACED" : "PROGERESSIVE");
- if (hdata->type == HDMI_TYPE13) - hdmi_v13_mode_set(hdata, mode); + if (hdata->version == HDMI_VER_EXYNOS4210) + hdmi_4210_mode_set(hdata, mode); else - hdmi_v14_mode_set(hdata, mode); + hdmi_4212_mode_set(hdata, mode); }
static void hdmi_get_max_resol(void *ctx, unsigned int *width, @@ -1962,16 +1963,16 @@ static int drm_hdmi_dt_parse_phy_pow_control(struct hdmi_context *hdata) static struct platform_device_id hdmi_driver_types[] = { { .name = "s5pv210-hdmi", - .driver_data = HDMI_TYPE13, + .driver_data = HDMI_VER_EXYNOS4210, }, { .name = "exynos4-hdmi", - .driver_data = HDMI_TYPE13, + .driver_data = HDMI_VER_EXYNOS4210, }, { .name = "exynos4-hdmi14", - .driver_data = HDMI_TYPE14, + .driver_data = HDMI_VER_EXYNOS4212, }, { .name = "exynos5-hdmi", - .driver_data = HDMI_TYPE14, + .driver_data = HDMI_VER_EXYNOS4212, }, { /* end node */ } @@ -1981,7 +1982,7 @@ static struct platform_device_id hdmi_driver_types[] = { static struct of_device_id hdmi_match_types[] = { { .compatible = "samsung,exynos5-hdmi", - .data = (void *)HDMI_TYPE14, + .data = (void *)HDMI_VER_EXYNOS4212, }, { /* end node */ } @@ -2041,9 +2042,9 @@ static int hdmi_probe(struct platform_device *pdev) dev->of_node); if (match == NULL) return -ENODEV; - hdata->type = (enum hdmi_type)match->data; + hdata->version = (enum hdmi_version)match->data; } else { - hdata->type = (enum hdmi_type)platform_get_device_id + hdata->version = (enum hdmi_version)platform_get_device_id (pdev)->driver_data; }
diff --git a/drivers/gpu/drm/exynos/regs-hdmi.h b/drivers/gpu/drm/exynos/regs-hdmi.h index 8d9ca25..e169847 100644 --- a/drivers/gpu/drm/exynos/regs-hdmi.h +++ b/drivers/gpu/drm/exynos/regs-hdmi.h @@ -19,7 +19,7 @@ * Register part */
-/* HDMI Version 1.3 & Common */ +/* HDMI Registers in Exynos4210 & Common to other soc */ #define HDMI_CTRL_BASE(x) ((x) + 0x00000000) #define HDMI_CORE_BASE(x) ((x) + 0x00010000) #define HDMI_I2S_BASE(x) ((x) + 0x00040000) @@ -29,57 +29,57 @@ #define HDMI_INTC_CON HDMI_CTRL_BASE(0x0000) #define HDMI_INTC_FLAG HDMI_CTRL_BASE(0x0004) #define HDMI_HPD_STATUS HDMI_CTRL_BASE(0x000C) -#define HDMI_V13_PHY_RSTOUT HDMI_CTRL_BASE(0x0014) -#define HDMI_V13_PHY_VPLL HDMI_CTRL_BASE(0x0018) -#define HDMI_V13_PHY_CMU HDMI_CTRL_BASE(0x001C) -#define HDMI_V13_CORE_RSTOUT HDMI_CTRL_BASE(0x0020) +#define HDMI_4210_PHY_RSTOUT HDMI_CTRL_BASE(0x0014) +#define HDMI_4210_PHY_VPLL HDMI_CTRL_BASE(0x0018) +#define HDMI_4210_PHY_CMU HDMI_CTRL_BASE(0x001C) +#define HDMI_4210_CORE_RSTOUT HDMI_CTRL_BASE(0x0020)
/* Core registers */ #define HDMI_CON_0 HDMI_CORE_BASE(0x0000) #define HDMI_CON_1 HDMI_CORE_BASE(0x0004) #define HDMI_CON_2 HDMI_CORE_BASE(0x0008) #define HDMI_SYS_STATUS HDMI_CORE_BASE(0x0010) -#define HDMI_V13_PHY_STATUS HDMI_CORE_BASE(0x0014) +#define HDMI_4210_PHY_STATUS HDMI_CORE_BASE(0x0014) #define HDMI_STATUS_EN HDMI_CORE_BASE(0x0020) #define HDMI_HPD HDMI_CORE_BASE(0x0030) #define HDMI_MODE_SEL HDMI_CORE_BASE(0x0040) #define HDMI_ENC_EN HDMI_CORE_BASE(0x0044) -#define HDMI_V13_BLUE_SCREEN_0 HDMI_CORE_BASE(0x0050) -#define HDMI_V13_BLUE_SCREEN_1 HDMI_CORE_BASE(0x0054) -#define HDMI_V13_BLUE_SCREEN_2 HDMI_CORE_BASE(0x0058) +#define HDMI_4210_BLUE_SCREEN_0 HDMI_CORE_BASE(0x0050) +#define HDMI_4210_BLUE_SCREEN_1 HDMI_CORE_BASE(0x0054) +#define HDMI_4210_BLUE_SCREEN_2 HDMI_CORE_BASE(0x0058) #define HDMI_H_BLANK_0 HDMI_CORE_BASE(0x00A0) #define HDMI_H_BLANK_1 HDMI_CORE_BASE(0x00A4) -#define HDMI_V13_V_BLANK_0 HDMI_CORE_BASE(0x00B0) -#define HDMI_V13_V_BLANK_1 HDMI_CORE_BASE(0x00B4) -#define HDMI_V13_V_BLANK_2 HDMI_CORE_BASE(0x00B8) -#define HDMI_V13_H_V_LINE_0 HDMI_CORE_BASE(0x00C0) -#define HDMI_V13_H_V_LINE_1 HDMI_CORE_BASE(0x00C4) -#define HDMI_V13_H_V_LINE_2 HDMI_CORE_BASE(0x00C8) +#define HDMI_4210_V_BLANK_0 HDMI_CORE_BASE(0x00B0) +#define HDMI_4210_V_BLANK_1 HDMI_CORE_BASE(0x00B4) +#define HDMI_4210_V_BLANK_2 HDMI_CORE_BASE(0x00B8) +#define HDMI_4210_H_V_LINE_0 HDMI_CORE_BASE(0x00C0) +#define HDMI_4210_H_V_LINE_1 HDMI_CORE_BASE(0x00C4) +#define HDMI_4210_H_V_LINE_2 HDMI_CORE_BASE(0x00C8) #define HDMI_VSYNC_POL HDMI_CORE_BASE(0x00E4) #define HDMI_INT_PRO_MODE HDMI_CORE_BASE(0x00E8) -#define HDMI_V13_V_BLANK_F_0 HDMI_CORE_BASE(0x0110) -#define HDMI_V13_V_BLANK_F_1 HDMI_CORE_BASE(0x0114) -#define HDMI_V13_V_BLANK_F_2 HDMI_CORE_BASE(0x0118) -#define HDMI_V13_H_SYNC_GEN_0 HDMI_CORE_BASE(0x0120) -#define HDMI_V13_H_SYNC_GEN_1 HDMI_CORE_BASE(0x0124) -#define HDMI_V13_H_SYNC_GEN_2 HDMI_CORE_BASE(0x0128) -#define HDMI_V13_V_SYNC_GEN_1_0 HDMI_CORE_BASE(0x0130) -#define HDMI_V13_V_SYNC_GEN_1_1 HDMI_CORE_BASE(0x0134) -#define HDMI_V13_V_SYNC_GEN_1_2 HDMI_CORE_BASE(0x0138) -#define HDMI_V13_V_SYNC_GEN_2_0 HDMI_CORE_BASE(0x0140) -#define HDMI_V13_V_SYNC_GEN_2_1 HDMI_CORE_BASE(0x0144) -#define HDMI_V13_V_SYNC_GEN_2_2 HDMI_CORE_BASE(0x0148) -#define HDMI_V13_V_SYNC_GEN_3_0 HDMI_CORE_BASE(0x0150) -#define HDMI_V13_V_SYNC_GEN_3_1 HDMI_CORE_BASE(0x0154) -#define HDMI_V13_V_SYNC_GEN_3_2 HDMI_CORE_BASE(0x0158) -#define HDMI_V13_ACR_CON HDMI_CORE_BASE(0x0180) -#define HDMI_V13_AVI_CON HDMI_CORE_BASE(0x0300) -#define HDMI_V13_AVI_BYTE(n) HDMI_CORE_BASE(0x0320 + 4 * (n)) -#define HDMI_V13_DC_CONTROL HDMI_CORE_BASE(0x05C0) -#define HDMI_V13_VIDEO_PATTERN_GEN HDMI_CORE_BASE(0x05C4) -#define HDMI_V13_HPD_GEN HDMI_CORE_BASE(0x05C8) -#define HDMI_V13_AUI_CON HDMI_CORE_BASE(0x0360) -#define HDMI_V13_SPD_CON HDMI_CORE_BASE(0x0400) +#define HDMI_4210_V_BLANK_F_0 HDMI_CORE_BASE(0x0110) +#define HDMI_4210_V_BLANK_F_1 HDMI_CORE_BASE(0x0114) +#define HDMI_4210_V_BLANK_F_2 HDMI_CORE_BASE(0x0118) +#define HDMI_4210_H_SYNC_GEN_0 HDMI_CORE_BASE(0x0120) +#define HDMI_4210_H_SYNC_GEN_1 HDMI_CORE_BASE(0x0124) +#define HDMI_4210_H_SYNC_GEN_2 HDMI_CORE_BASE(0x0128) +#define HDMI_4210_V_SYNC_GEN_1_0 HDMI_CORE_BASE(0x0130) +#define HDMI_4210_V_SYNC_GEN_1_1 HDMI_CORE_BASE(0x0134) +#define HDMI_4210_V_SYNC_GEN_1_2 HDMI_CORE_BASE(0x0138) +#define HDMI_4210_V_SYNC_GEN_2_0 HDMI_CORE_BASE(0x0140) +#define HDMI_4210_V_SYNC_GEN_2_1 HDMI_CORE_BASE(0x0144) +#define HDMI_4210_V_SYNC_GEN_2_2 HDMI_CORE_BASE(0x0148) +#define HDMI_4210_V_SYNC_GEN_3_0 HDMI_CORE_BASE(0x0150) +#define HDMI_4210_V_SYNC_GEN_3_1 HDMI_CORE_BASE(0x0154) +#define HDMI_4210_V_SYNC_GEN_3_2 HDMI_CORE_BASE(0x0158) +#define HDMI_4210_ACR_CON HDMI_CORE_BASE(0x0180) +#define HDMI_4210_AVI_CON HDMI_CORE_BASE(0x0300) +#define HDMI_4210_AVI_BYTE(n) HDMI_CORE_BASE(0x0320 + 4 * (n)) +#define HDMI_4210_DC_CONTROL HDMI_CORE_BASE(0x05C0) +#define HDMI_4210_VIDEO_PATTERN_GEN HDMI_CORE_BASE(0x05C4) +#define HDMI_4210_HPD_GEN HDMI_CORE_BASE(0x05C8) +#define HDMI_4210_AUI_CON HDMI_CORE_BASE(0x0360) +#define HDMI_4210_SPD_CON HDMI_CORE_BASE(0x0400)
/* Timing generator registers */ #define HDMI_TG_CMD HDMI_TG_BASE(0x0000) @@ -155,7 +155,7 @@ #define HDMI_FIELD_EN (1 << 1)
-/* HDMI Version 1.4 */ +/* HDMI Registers in Exynos4212 */ /* Control registers */ /* #define HDMI_INTC_CON HDMI_CTRL_BASE(0x0000) */ /* #define HDMI_INTC_FLAG HDMI_CTRL_BASE(0x0004) */
Hello Rahul,
On 2013년 06월 11일 23:11, Rahul Sharma wrote:
Exynos hdmi IP version is named after hdmi specification version i.e. 1.3 and 1.4. This versioning mechanism is not sufficient to handle the diversity in the hdmi/phy IPs which are present across the exynos SoC family.
This patch changes the hdmi version to the name of the SoC in which the IP was introduced for the first time. Same version is applicable to all subsequent SoCs having the same IP version.
Exynos4210 has 1.3 HDMI, i2c mapped phy with configuration set. Exynos5250 has 1.4 HDMI, i2c mapped phy with configuration set. Exynos5420 has 1.4 HDMI, Platform Bus mapped phy with configuration set.
Based on the HDMI IP version we cannot decide to pick Exynos5250 phy conf and use i2c for data transfer or Exynos5420 phy confs and platform bus calls for communication.
Considering your other patch to divide hdmi and hdmiphy, how do you think using hdmiphy version parsed from hdmiphy dt binding from phy code instead of using hdmi version for both hdmi and hdmiphy? If that, this SoC identifying hdmi version is not necessary because there is no change at least in hdmi side.
And IMO, it seems easy to merge hdmiphy related patch first before merging patch for exynos5420.
Signed-off-by: Rahul Sharma rahul.sharma@samsung.com
drivers/gpu/drm/exynos/exynos_hdmi.c | 249 +++++++++++++++++----------------- drivers/gpu/drm/exynos/regs-hdmi.h | 78 +++++------ 2 files changed, 164 insertions(+), 163 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c index 75a6bf3..9384ffc 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c @@ -73,9 +73,9 @@ enum HDMI_PACKET_TYPE { HDMI_PACKET_TYPE_AUI = HDMI_PACKET_TYPE_INFOFRAME + 4 };
-enum hdmi_type {
- HDMI_TYPE13,
- HDMI_TYPE14,
+enum hdmi_version {
- HDMI_VER_EXYNOS4210,
- HDMI_VER_EXYNOS4212,
};
<snip>
Thanks Seung-Woo,
On Fri, Jun 14, 2013 at 12:23 PM, 김승우 sw0312.kim@samsung.com wrote:
Hello Rahul,
On 2013년 06월 11일 23:11, Rahul Sharma wrote:
Exynos hdmi IP version is named after hdmi specification version i.e. 1.3 and 1.4. This versioning mechanism is not sufficient to handle the diversity in the hdmi/phy IPs which are present across the exynos SoC family.
This patch changes the hdmi version to the name of the SoC in which the IP was introduced for the first time. Same version is applicable to all subsequent SoCs having the same IP version.
Exynos4210 has 1.3 HDMI, i2c mapped phy with configuration set. Exynos5250 has 1.4 HDMI, i2c mapped phy with configuration set. Exynos5420 has 1.4 HDMI, Platform Bus mapped phy with configuration set.
Based on the HDMI IP version we cannot decide to pick Exynos5250 phy conf and use i2c for data transfer or Exynos5420 phy confs and platform bus calls for communication.
Considering your other patch to divide hdmi and hdmiphy, how do you think using hdmiphy version parsed from hdmiphy dt binding from phy code instead of using hdmi version for both hdmi and hdmiphy? If that, this SoC identifying hdmi version is not necessary because there is no change at least in hdmi side.
And IMO, it seems easy to merge hdmiphy related patch first before merging patch for exynos5420.
You are right. If we isolate hdmiphy first from hdmi IP driver, we dont need this patch. I will revive the hdmiphy separation patch and get that merge first.
regards, Rahul Sharma.
Signed-off-by: Rahul Sharma rahul.sharma@samsung.com
drivers/gpu/drm/exynos/exynos_hdmi.c | 249 +++++++++++++++++----------------- drivers/gpu/drm/exynos/regs-hdmi.h | 78 +++++------ 2 files changed, 164 insertions(+), 163 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c index 75a6bf3..9384ffc 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c @@ -73,9 +73,9 @@ enum HDMI_PACKET_TYPE { HDMI_PACKET_TYPE_AUI = HDMI_PACKET_TYPE_INFOFRAME + 4 };
-enum hdmi_type {
HDMI_TYPE13,HDMI_TYPE14,+enum hdmi_version {
HDMI_VER_EXYNOS4210,HDMI_VER_EXYNOS4212,};
<snip>
-- Seung-Woo Kim Samsung Software R&D Center --
-- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
This patch renames the combatible strings for hdmi, mixer, ddc and hdmiphy. It follows the convention of using compatible string which represent the SoC in which the IP was added for the first time.
Signed-off-by: Rahul Sharma rahul.sharma@samsung.com --- Documentation/devicetree/bindings/video/exynos_hdmi.txt | 6 ++++-- Documentation/devicetree/bindings/video/exynos_hdmiddc.txt | 4 ++-- Documentation/devicetree/bindings/video/exynos_hdmiphy.txt | 4 ++-- Documentation/devicetree/bindings/video/exynos_mixer.txt | 7 +++++-- arch/arm/boot/dts/cros5250-common.dtsi | 4 ++-- arch/arm/boot/dts/exynos5250-smdk5250.dts | 4 ++-- arch/arm/boot/dts/exynos5250.dtsi | 4 ++-- drivers/gpu/drm/exynos/exynos_ddc.c | 2 +- drivers/gpu/drm/exynos/exynos_hdmi.c | 2 +- drivers/gpu/drm/exynos/exynos_hdmiphy.c | 2 +- drivers/gpu/drm/exynos/exynos_mixer.c | 12 ++++++------ 11 files changed, 28 insertions(+), 23 deletions(-)
diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt b/Documentation/devicetree/bindings/video/exynos_hdmi.txt index 589edee..2ac01ca 100644 --- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt +++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt @@ -1,7 +1,9 @@ Device-Tree bindings for drm hdmi driver
Required properties: -- compatible: value should be "samsung,exynos5-hdmi". +- compatible: value should be one among the following: + 1) "samsung,exynos4210-hdmi" + 2) "samsung,exynos4212-hdmi" - reg: physical base address of the hdmi and length of memory mapped region. - interrupts: interrupt number to the cpu. @@ -15,7 +17,7 @@ Required properties: Example:
hdmi { - compatible = "samsung,exynos5-hdmi"; + compatible = "samsung,exynos4212-hdmi"; reg = <0x14530000 0x100000>; interrupts = <0 95 0>; hpd-gpio = <&gpx3 7 0xf 1 3>; diff --git a/Documentation/devicetree/bindings/video/exynos_hdmiddc.txt b/Documentation/devicetree/bindings/video/exynos_hdmiddc.txt index fa166d9..c1bd2ea 100644 --- a/Documentation/devicetree/bindings/video/exynos_hdmiddc.txt +++ b/Documentation/devicetree/bindings/video/exynos_hdmiddc.txt @@ -1,12 +1,12 @@ Device-Tree bindings for hdmiddc driver
Required properties: -- compatible: value should be "samsung,exynos5-hdmiddc". +- compatible: value should be "samsung,exynos4210-hdmiddc". - reg: I2C address of the hdmiddc device.
Example:
hdmiddc { - compatible = "samsung,exynos5-hdmiddc"; + compatible = "samsung,exynos4210-hdmiddc"; reg = <0x50>; }; diff --git a/Documentation/devicetree/bindings/video/exynos_hdmiphy.txt b/Documentation/devicetree/bindings/video/exynos_hdmiphy.txt index 858f4f9..fb688a6 100644 --- a/Documentation/devicetree/bindings/video/exynos_hdmiphy.txt +++ b/Documentation/devicetree/bindings/video/exynos_hdmiphy.txt @@ -1,12 +1,12 @@ Device-Tree bindings for hdmiphy driver
Required properties: -- compatible: value should be "samsung,exynos5-hdmiphy". +- compatible: value should be "samsung,exynos4210-hdmiphy". - reg: I2C address of the hdmiphy device.
Example:
hdmiphy { - compatible = "samsung,exynos5-hdmiphy"; + compatible = "samsung,exynos4210-hdmiphy"; reg = <0x38>; }; diff --git a/Documentation/devicetree/bindings/video/exynos_mixer.txt b/Documentation/devicetree/bindings/video/exynos_mixer.txt index 9b2ea03..a8b063f 100644 --- a/Documentation/devicetree/bindings/video/exynos_mixer.txt +++ b/Documentation/devicetree/bindings/video/exynos_mixer.txt @@ -1,7 +1,10 @@ Device-Tree bindings for mixer driver
Required properties: -- compatible: value should be "samsung,exynos5-mixer". +- compatible: value should be: + 1) "samsung,exynos4210-mixer" + 2) "samsung,exynos5250-mixer" + - reg: physical base address of the mixer and length of memory mapped region. - interrupts: interrupt number to the cpu. @@ -9,7 +12,7 @@ Required properties: Example:
mixer { - compatible = "samsung,exynos5-mixer"; + compatible = "samsung,exynos5250-mixer"; reg = <0x14450000 0x10000>; interrupts = <0 94 0>; }; diff --git a/arch/arm/boot/dts/cros5250-common.dtsi b/arch/arm/boot/dts/cros5250-common.dtsi index 3f0239e..0a319c3 100644 --- a/arch/arm/boot/dts/cros5250-common.dtsi +++ b/arch/arm/boot/dts/cros5250-common.dtsi @@ -190,7 +190,7 @@ samsung,i2c-max-bus-freq = <66000>;
hdmiddc@50 { - compatible = "samsung,exynos5-hdmiddc"; + compatible = "samsung,exynos4210-hdmiddc"; reg = <0x50>; }; }; @@ -224,7 +224,7 @@ samsung,i2c-max-bus-freq = <378000>;
hdmiphy@38 { - compatible = "samsung,exynos5-hdmiphy"; + compatible = "samsung,exynos4210-hdmiphy"; reg = <0x38>; }; }; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 3e0c792..0ec6856 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -72,7 +72,7 @@ samsung,i2c-max-bus-freq = <66000>;
hdmiddc@50 { - compatible = "samsung,exynos5-hdmiddc"; + compatible = "samsung,exynos4210-hdmiddc"; reg = <0x50>; }; }; @@ -102,7 +102,7 @@ samsung,i2c-max-bus-freq = <66000>;
hdmiphy@38 { - compatible = "samsung,exynos5-hdmiphy"; + compatible = "samsung,exynos4210-hdmiphy"; reg = <0x38>; }; }; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 5549236..0157fec 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -601,7 +601,7 @@ };
hdmi { - compatible = "samsung,exynos5-hdmi"; + compatible = "samsung,exynos4212-hdmi"; reg = <0x14530000 0x70000>; interrupts = <0 95 0>; clocks = <&clock 344>, <&clock 136>, <&clock 137>, @@ -617,7 +617,7 @@ };
mixer { - compatible = "samsung,exynos5-mixer"; + compatible = "samsung,exynos5250-mixer"; reg = <0x14450000 0x10000>; interrupts = <0 94 0>; clocks = <&clock 343>, <&clock 136>; diff --git a/drivers/gpu/drm/exynos/exynos_ddc.c b/drivers/gpu/drm/exynos/exynos_ddc.c index 4e9b5ba..1a0cca1 100644 --- a/drivers/gpu/drm/exynos/exynos_ddc.c +++ b/drivers/gpu/drm/exynos/exynos_ddc.c @@ -51,7 +51,7 @@ static struct i2c_device_id ddc_idtable[] = { #ifdef CONFIG_OF static struct of_device_id hdmiddc_match_types[] = { { - .compatible = "samsung,exynos5-hdmiddc", + .compatible = "samsung,exynos4210-hdmiddc", }, { /* end node */ } diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c index 9384ffc..a7f7ab3 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c @@ -1981,7 +1981,7 @@ static struct platform_device_id hdmi_driver_types[] = { #ifdef CONFIG_OF static struct of_device_id hdmi_match_types[] = { { - .compatible = "samsung,exynos5-hdmi", + .compatible = "samsung,exynos4212-hdmi", .data = (void *)HDMI_VER_EXYNOS4212, }, { /* end node */ diff --git a/drivers/gpu/drm/exynos/exynos_hdmiphy.c b/drivers/gpu/drm/exynos/exynos_hdmiphy.c index ea49d13..60dbe6c 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmiphy.c +++ b/drivers/gpu/drm/exynos/exynos_hdmiphy.c @@ -49,7 +49,7 @@ static const struct i2c_device_id hdmiphy_id[] = { #ifdef CONFIG_OF static struct of_device_id hdmiphy_match_types[] = { { - .compatible = "samsung,exynos5-hdmiphy", + .compatible = "samsung,exynos4210-hdmiphy", }, { /* end node */ } diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c index 978894e..58dfd3f 100644 --- a/drivers/gpu/drm/exynos/exynos_mixer.c +++ b/drivers/gpu/drm/exynos/exynos_mixer.c @@ -1127,12 +1127,12 @@ static int vp_resources_init(struct exynos_drm_hdmi_context *ctx, return 0; }
-static struct mixer_drv_data exynos5_mxr_drv_data = { +static struct mixer_drv_data exynos5250_mxr_drv_data = { .version = MXR_VER_16_0_33_0, .is_vp_enabled = 0, };
-static struct mixer_drv_data exynos4_mxr_drv_data = { +static struct mixer_drv_data exynos4210_mxr_drv_data = { .version = MXR_VER_0_0_0_16, .is_vp_enabled = 1, }; @@ -1140,10 +1140,10 @@ static struct mixer_drv_data exynos4_mxr_drv_data = { static struct platform_device_id mixer_driver_types[] = { { .name = "s5p-mixer", - .driver_data = (unsigned long)&exynos4_mxr_drv_data, + .driver_data = (unsigned long)&exynos4210_mxr_drv_data, }, { .name = "exynos5-mixer", - .driver_data = (unsigned long)&exynos5_mxr_drv_data, + .driver_data = (unsigned long)&exynos5250_mxr_drv_data, }, { /* end node */ } @@ -1151,8 +1151,8 @@ static struct platform_device_id mixer_driver_types[] = {
static struct of_device_id mixer_match_types[] = { { - .compatible = "samsung,exynos5-mixer", - .data = &exynos5_mxr_drv_data, + .compatible = "samsung,exynos5250-mixer", + .data = &exynos5250_mxr_drv_data, }, { /* end node */ }
Add support for exynos5420 hdmi IP.
Signed-off-by: Rahul Sharma rahul.sharma@samsung.com --- drivers/gpu/drm/exynos/exynos_hdmi.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c index a7f7ab3..0c94e54 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c @@ -76,6 +76,7 @@ enum HDMI_PACKET_TYPE { enum hdmi_version { HDMI_VER_EXYNOS4210, HDMI_VER_EXYNOS4212, + HDMI_VER_EXYNOS5420, };
struct hdmi_resources { @@ -1984,6 +1985,9 @@ static struct of_device_id hdmi_match_types[] = { .compatible = "samsung,exynos4212-hdmi", .data = (void *)HDMI_VER_EXYNOS4212, }, { + .compatible = "samsung,exynos5420-hdmi", + .data = (void *)HDMI_VER_EXYNOS5420, + }, { /* end node */ } };
Add support for exynos5420 hdmiphy which is mapped to the platform bus. hdmi dt node has a property with name "phy" which holds the phandle for hdmiphy node. hdmi driver uses this phandle to check the compatible type of the phy. If it is compatible with exynos5420, it needs to be treated as a platform bus mapped device, else i2c device.
Signed-off-by: Rahul Sharma rahul.sharma@samsung.com --- drivers/gpu/drm/exynos/exynos_hdmi.c | 274 ++++++++++++++++++++++++++++++---- 1 file changed, 243 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c index 0c94e54..423bdc6 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c @@ -191,6 +191,7 @@ struct hdmi_context {
void __iomem *regs; void __iomem *phy_pow_ctrl_reg; + void __iomem *regs_hdmiphy; void *parent_ctx; int irq;
@@ -381,6 +382,136 @@ static const struct hdmiphy_config hdmiphy_4212_configs[] = { }, };
+static const struct hdmiphy_config hdmiphy_5420_configs[] = { + { + .pixel_clock = 25200000, + .conf = { + 0x01, 0x52, 0x3F, 0x55, 0x40, 0x01, 0x00, 0xC8, + 0x82, 0xC8, 0xBD, 0xD8, 0x45, 0xA0, 0xAC, 0x80, + 0x06, 0x80, 0x01, 0x84, 0x05, 0x02, 0x24, 0x86, + 0x54, 0xF4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, + }, + }, + { + .pixel_clock = 27000000, + .conf = { + 0x01, 0xD1, 0x22, 0x51, 0x40, 0x08, 0xFC, 0xE0, + 0x98, 0xE8, 0xCB, 0xD8, 0x45, 0xA0, 0xAC, 0x80, + 0x06, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x86, + 0x54, 0xE4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, + }, + }, + { + .pixel_clock = 27027000, + .conf = { + 0x01, 0xD1, 0x2D, 0x72, 0x40, 0x64, 0x12, 0xC8, + 0x43, 0xE8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80, + 0x06, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x86, + 0x54, 0xE3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, + }, + }, + { + .pixel_clock = 36000000, + .conf = { + 0x01, 0x51, 0x2D, 0x55, 0x40, 0x40, 0x00, 0xC8, + 0x02, 0xC8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80, + 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x86, + 0x54, 0xAB, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, + + }, + }, + { + .pixel_clock = 40000000, + .conf = { + 0x01, 0xD1, 0x21, 0x31, 0x40, 0x3C, 0x28, 0xC8, + 0x87, 0xE8, 0xC8, 0xD8, 0x45, 0xA0, 0xAC, 0x80, + 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x86, + 0x54, 0x9A, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, + }, + }, + { + .pixel_clock = 65000000, + .conf = { + 0x01, 0xD1, 0x36, 0x34, 0x40, 0x0C, 0x04, 0xC8, + 0x82, 0xE8, 0x45, 0xD9, 0x45, 0xA0, 0xAC, 0x80, + 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x86, + 0x54, 0xBD, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, + }, + }, + { + .pixel_clock = 71000000, + .conf = { + 0x01, 0xD1, 0x3B, 0x35, 0x40, 0x0C, 0x04, 0xC8, + 0x85, 0xE8, 0x63, 0xD9, 0x45, 0xA0, 0xAC, 0x80, + 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x86, + 0x54, 0x57, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, + }, + }, + { + .pixel_clock = 74176000, + .conf = { + 0x01, 0xD1, 0x1F, 0x10, 0x40, 0x5B, 0xEF, 0xC8, + 0x81, 0xE8, 0xB9, 0xD8, 0x45, 0xA0, 0xAC, 0x80, + 0x56, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x86, + 0x54, 0xA6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, + }, + }, + { + .pixel_clock = 74250000, + .conf = { + 0x01, 0xD1, 0x1F, 0x10, 0x40, 0x40, 0xF8, 0xC8, + 0x81, 0xE8, 0xBA, 0xD8, 0x45, 0xA0, 0xAC, 0x80, + 0x56, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x86, + 0x54, 0xA5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, + }, + }, + { + .pixel_clock = 83500000, + .conf = { + 0x01, 0xD1, 0x23, 0x11, 0x40, 0x0C, 0xFB, 0xC8, + 0x85, 0xE8, 0xD1, 0xD8, 0x45, 0xA0, 0xAC, 0x80, + 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x86, + 0x54, 0x4A, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, + }, + }, + { + .pixel_clock = 106500000, + .conf = { + 0x01, 0xD1, 0x2C, 0x12, 0x40, 0x0C, 0x09, 0xC8, + 0x84, 0xE8, 0x0A, 0xD9, 0x45, 0xA0, 0xAC, 0x80, + 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x86, + 0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, + }, + }, + { + .pixel_clock = 108000000, + .conf = { + 0x01, 0x51, 0x2D, 0x15, 0x40, 0x01, 0x00, 0xC8, + 0x82, 0xC8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80, + 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x86, + 0x54, 0xC7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80, + }, + }, + { + .pixel_clock = 146250000, + .conf = { + 0x01, 0xD1, 0x3D, 0x15, 0x40, 0x18, 0xFD, 0xC8, + 0x83, 0xE8, 0x6E, 0xD9, 0x45, 0xA0, 0xAC, 0x80, + 0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x86, + 0x54, 0x54, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, + }, + }, + { + .pixel_clock = 148500000, + .conf = { + 0x01, 0xD1, 0x1F, 0x00, 0x40, 0x40, 0xF8, 0xC8, + 0x81, 0xE8, 0xBA, 0xD8, 0x45, 0xA0, 0xAC, 0x80, + 0x66, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x86, + 0x54, 0x4B, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80, + }, + }, +}; + struct hdmi_infoframe { enum HDMI_PACKET_TYPE type; u8 ver; @@ -414,6 +545,70 @@ static inline void hdmi_phy_pow_ctrl_reg_writemask(struct hdmi_context *hdata, writel(value, hdata->phy_pow_ctrl_reg); }
+static int hdmiphy_reg_writeb(struct hdmi_context *hdata, + u32 reg_offset, u8 value) +{ + if (hdata->hdmiphy_port) { + u8 buffer[2]; + int ret; + + buffer[0] = reg_offset; + buffer[1] = value; + + ret = i2c_master_send(hdata->hdmiphy_port, buffer, 2); + if (ret == 2) + return 0; + return ret; + } else { + writeb(value, hdata->regs_hdmiphy + (reg_offset<<2)); + return 0; + } +} + +static int hdmiphy_reg_write_buf(struct hdmi_context *hdata, + u32 reg_offset, const u8 *buf, u32 len) +{ + if ((reg_offset + len) > 32) + return -EINVAL; + + if (hdata->hdmiphy_port) { + int ret; + + ret = i2c_master_send(hdata->hdmiphy_port, buf, len); + if (ret == len) + return 0; + return ret; + } else { + int i; + for (i = 0; i < len; i++) + writeb(buf[i], hdata->regs_hdmiphy + + ((reg_offset + i)<<2)); + return 0; + } +} + +static int hdmiphy_reg_read_buf(struct hdmi_context *hdata, + u32 reg_offset, u8 *buf, u32 len) +{ + if ((reg_offset + len) > 32) + return -EINVAL; + + if (hdata->hdmiphy_port) { + int ret; + + ret = i2c_master_recv(hdata->hdmiphy_port, buf, len); + if (ret == len) + return 0; + return ret; + } else { + int i; + for (i = 0; i < len; i++) + buf[i] = readb(hdata->regs_hdmiphy + + ((reg_offset + i)<<2)); + return 0; + } +} + static void hdmi_4210_regs_dump(struct hdmi_context *hdata, char *prefix) { #define DUMPREG(reg_id) \ @@ -796,6 +991,9 @@ static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock) } else if (hdata->version == HDMI_VER_EXYNOS4212) { confs = hdmiphy_4212_configs; count = ARRAY_SIZE(hdmiphy_4212_configs); + } else if (hdata->version == HDMI_VER_EXYNOS5420) { + confs = hdmiphy_5420_configs; + count = ARRAY_SIZE(hdmiphy_5420_configs); } else return -EINVAL;
@@ -1318,19 +1516,13 @@ static void hdmi_mode_apply(struct hdmi_context *hdata)
static void hdmiphy_conf_reset(struct hdmi_context *hdata) { - u8 buffer[2]; u32 reg;
clk_disable_unprepare(hdata->res.sclk_hdmi); clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_pixel); clk_prepare_enable(hdata->res.sclk_hdmi);
- /* operation mode */ - buffer[0] = 0x1f; - buffer[1] = 0x00; - - if (hdata->hdmiphy_port) - i2c_master_send(hdata->hdmiphy_port, buffer, 2); + hdmiphy_reg_writeb(hdata, 0x1f, 0x00);
if (hdata->version == HDMI_VER_EXYNOS4210) reg = HDMI_4210_PHY_RSTOUT; @@ -1366,16 +1558,10 @@ static void hdmiphy_conf_apply(struct hdmi_context *hdata) { const u8 *hdmiphy_data; u8 buffer[32]; - u8 operation[2]; u8 read_buffer[32] = {0, }; int ret; int i;
- if (!hdata->hdmiphy_port) { - DRM_ERROR("hdmiphy is not attached\n"); - return; - } - /* pixel clock */ i = hdmi_find_phy_conf(hdata, hdata->mode_conf.pixel_clock); if (i < 0) { @@ -1383,31 +1569,32 @@ static void hdmiphy_conf_apply(struct hdmi_context *hdata) return; }
- if (hdata->version == HDMI_VER_EXYNOS4210) + if (hdata->version == HDMI_VER_EXYNOS4210) { hdmiphy_data = hdmiphy_4210_configs[i].conf; - else + } else if (hdata->version == HDMI_VER_EXYNOS4212) { hdmiphy_data = hdmiphy_4212_configs[i].conf; + } else if (hdata->version == HDMI_VER_EXYNOS5420) { + hdmiphy_data = hdmiphy_5420_configs[i].conf; + } else { + DRM_ERROR("invalid hdmi version.\n"); + return; + }
- memcpy(buffer, hdmiphy_data, 32); - ret = i2c_master_send(hdata->hdmiphy_port, buffer, 32); - if (ret != 32) { - DRM_ERROR("failed to configure HDMIPHY via I2C\n"); + ret = hdmiphy_reg_write_buf(hdata, 0, hdmiphy_data, 32); + if (ret) { + DRM_ERROR("failed to configure HDMIPHY\n"); return; }
usleep_range(10000, 12000);
- /* operation mode */ - operation[0] = 0x1f; - operation[1] = 0x80; - - ret = i2c_master_send(hdata->hdmiphy_port, operation, 2); - if (ret != 2) { + ret = hdmiphy_reg_writeb(hdata, 0x1f, 0x80); + if (ret < 0) { DRM_ERROR("failed to enable hdmiphy\n"); return; }
- ret = i2c_master_recv(hdata->hdmiphy_port, read_buffer, 32); + ret = hdmiphy_reg_read_buf(hdata, 0, read_buffer, 32); if (ret < 0) { DRM_ERROR("failed to read hdmiphy config\n"); return; @@ -2000,6 +2187,7 @@ static int hdmi_probe(struct platform_device *pdev) struct hdmi_context *hdata; struct s5p_hdmi_platform_data *pdata; struct resource *res; + struct device_node *phy_node; int ret;
DRM_DEBUG_KMS("[%d]\n", __LINE__); @@ -2088,14 +2276,38 @@ static int hdmi_probe(struct platform_device *pdev)
hdata->ddc_port = hdmi_ddc;
- /* hdmiphy i2c driver */ - if (i2c_add_driver(&hdmiphy_driver)) { - DRM_ERROR("failed to register hdmiphy i2c driver\n"); - ret = -ENOENT; + /* hdmiphy driver */ + phy_node = of_parse_phandle(dev->of_node, "phy", 0); + if (IS_ERR_OR_NULL(phy_node)) { + DRM_ERROR("failed to get phandle for phy.\n"); + return -ENOENT; goto err_ddc; }
- hdata->hdmiphy_port = hdmi_hdmiphy; + if (of_device_is_compatible(phy_node, "samsung,exynos5420-hdmiphy")) { + u32 buf[2]; + + if (of_property_read_u32_array(phy_node, "reg", buf, 2)) { + DRM_ERROR("faild to get reg for hdmi-phy\n"); + ret = -EINVAL; + goto err_ddc; + } + + hdata->regs_hdmiphy = devm_ioremap(hdata->dev, buf[0], buf[1]); + if (!hdata->regs_hdmiphy) { + DRM_ERROR("failed to ioremap hdmi-phy\n"); + ret = -ENOMEM; + goto err_ddc; + } + hdata->hdmiphy_port = NULL; + } else { + if (i2c_add_driver(&hdmiphy_driver)) { + DRM_ERROR("failed to register hdmiphy i2c driver\n"); + ret = -ENOENT; + goto err_ddc; + } + hdata->hdmiphy_port = hdmi_hdmiphy; + }
hdata->irq = gpio_to_irq(hdata->hpd_gpio); if (hdata->irq < 0) {
Add support for exynos5420 mixer IP in the drm mixer driver.
Signed-off-by: Rahul Sharma rahul.sharma@samsung.com --- drivers/gpu/drm/exynos/exynos_mixer.c | 49 +++++++++++++++++++++++++-------- drivers/gpu/drm/exynos/regs-mixer.h | 7 +++++ 2 files changed, 44 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c index 58dfd3f..101d5bb 100644 --- a/drivers/gpu/drm/exynos/exynos_mixer.c +++ b/drivers/gpu/drm/exynos/exynos_mixer.c @@ -78,6 +78,7 @@ struct mixer_resources { enum mixer_version_id { MXR_VER_0_0_0_16, MXR_VER_16_0_33_0, + MXR_VER_128_0_0_184, };
struct mixer_context { @@ -283,17 +284,19 @@ static void mixer_cfg_scan(struct mixer_context *ctx, unsigned int height) val = (ctx->interlace ? MXR_CFG_SCAN_INTERLACE : MXR_CFG_SCAN_PROGRASSIVE);
- /* choosing between porper HD and SD mode */ - if (height <= 480) - val |= MXR_CFG_SCAN_NTSC | MXR_CFG_SCAN_SD; - else if (height <= 576) - val |= MXR_CFG_SCAN_PAL | MXR_CFG_SCAN_SD; - else if (height <= 720) - val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD; - else if (height <= 1080) - val |= MXR_CFG_SCAN_HD_1080 | MXR_CFG_SCAN_HD; - else - val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD; + if (ctx->mxr_ver != MXR_VER_128_0_0_184) { + /* choosing between proper HD and SD mode */ + if (height <= 480) + val |= MXR_CFG_SCAN_NTSC | MXR_CFG_SCAN_SD; + else if (height <= 576) + val |= MXR_CFG_SCAN_PAL | MXR_CFG_SCAN_SD; + else if (height <= 720) + val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD; + else if (height <= 1080) + val |= MXR_CFG_SCAN_HD_1080 | MXR_CFG_SCAN_HD; + else + val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD; + }
mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_SCAN_MASK); } @@ -557,6 +560,14 @@ static void mixer_graph_buffer(struct mixer_context *ctx, int win) /* setup geometry */ mixer_reg_write(res, MXR_GRAPHIC_SPAN(win), win_data->fb_width);
+ /* setup display size */ + if (ctx->mxr_ver == MXR_VER_128_0_0_184 && + win == MIXER_DEFAULT_WIN) { + val = MXR_MXR_RES_HEIGHT(win_data->fb_height); + val |= MXR_MXR_RES_WIDTH(win_data->fb_width); + mixer_reg_write(res, MXR_RESOLUTION, val); + } + val = MXR_GRP_WH_WIDTH(win_data->crtc_width); val |= MXR_GRP_WH_HEIGHT(win_data->crtc_height); val |= MXR_GRP_WH_H_SCALE(x_ratio); @@ -581,7 +592,8 @@ static void mixer_graph_buffer(struct mixer_context *ctx, int win) mixer_cfg_layer(ctx, win, true);
/* layer update mandatory for mixer 16.0.33.0 */ - if (ctx->mxr_ver == MXR_VER_16_0_33_0) + if (ctx->mxr_ver == MXR_VER_16_0_33_0 || + ctx->mxr_ver == MXR_VER_128_0_0_184) mixer_layer_update(ctx);
mixer_run(ctx); @@ -822,6 +834,7 @@ static void mixer_win_disable(void *ctx, int win)
static int mixer_check_mode(void *ctx, struct drm_display_mode *mode) { + struct mixer_context *mixer_ctx = ctx; u32 w, h;
w = mode->hdisplay; @@ -831,6 +844,10 @@ static int mixer_check_mode(void *ctx, struct drm_display_mode *mode) mode->hdisplay, mode->vdisplay, mode->vrefresh, (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0);
+ if (mixer_ctx->mxr_ver == MXR_VER_0_0_0_16 || + mixer_ctx->mxr_ver == MXR_VER_128_0_0_184) + return 0; + if ((w >= 464 && w <= 720 && h >= 261 && h <= 576) || (w >= 1024 && w <= 1280 && h >= 576 && h <= 720) || (w >= 1664 && w <= 1920 && h >= 936 && h <= 1080)) @@ -1127,6 +1144,11 @@ static int vp_resources_init(struct exynos_drm_hdmi_context *ctx, return 0; }
+static struct mixer_drv_data exynos5420_mxr_drv_data = { + .version = MXR_VER_128_0_0_184, + .is_vp_enabled = 0, +}; + static struct mixer_drv_data exynos5250_mxr_drv_data = { .version = MXR_VER_16_0_33_0, .is_vp_enabled = 0, @@ -1151,6 +1173,9 @@ static struct platform_device_id mixer_driver_types[] = {
static struct of_device_id mixer_match_types[] = { { + .compatible = "samsung,exynos5420-mixer", + .data = &exynos5420_mxr_drv_data, + }, { .compatible = "samsung,exynos5250-mixer", .data = &exynos5250_mxr_drv_data, }, { diff --git a/drivers/gpu/drm/exynos/regs-mixer.h b/drivers/gpu/drm/exynos/regs-mixer.h index 5d8dbc0..4537026 100644 --- a/drivers/gpu/drm/exynos/regs-mixer.h +++ b/drivers/gpu/drm/exynos/regs-mixer.h @@ -44,6 +44,9 @@ #define MXR_CM_COEFF_Y 0x0080 #define MXR_CM_COEFF_CB 0x0084 #define MXR_CM_COEFF_CR 0x0088 +#define MXR_MO 0x0304 +#define MXR_RESOLUTION 0x0310 + #define MXR_GRAPHIC0_BASE_S 0x2024 #define MXR_GRAPHIC1_BASE_S 0x2044
@@ -119,6 +122,10 @@ #define MXR_GRP_WH_WIDTH(x) MXR_MASK_VAL(x, 26, 16) #define MXR_GRP_WH_HEIGHT(x) MXR_MASK_VAL(x, 10, 0)
+/* bits for MXR_RESOLUTION */ +#define MXR_MXR_RES_HEIGHT(x) MXR_MASK_VAL(x, 26, 16) +#define MXR_MXR_RES_WIDTH(x) MXR_MASK_VAL(x, 10, 0) + /* bits for MXR_GRAPHICn_SXY */ #define MXR_GRP_SXY_SX(x) MXR_MASK_VAL(x, 26, 16) #define MXR_GRP_SXY_SY(x) MXR_MASK_VAL(x, 10, 0)
Hello Rahul,
This patch looks good to me just with mixer part of 2nd patch because there is no hdmiphy related things.
On 2013년 06월 11일 23:11, Rahul Sharma wrote:
Add support for exynos5420 mixer IP in the drm mixer driver.
Signed-off-by: Rahul Sharma rahul.sharma@samsung.com
drivers/gpu/drm/exynos/exynos_mixer.c | 49 +++++++++++++++++++++++++-------- drivers/gpu/drm/exynos/regs-mixer.h | 7 +++++ 2 files changed, 44 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c index 58dfd3f..101d5bb 100644 --- a/drivers/gpu/drm/exynos/exynos_mixer.c +++ b/drivers/gpu/drm/exynos/exynos_mixer.c @@ -78,6 +78,7 @@ struct mixer_resources { enum mixer_version_id { MXR_VER_0_0_0_16, MXR_VER_16_0_33_0,
- MXR_VER_128_0_0_184,
};
struct mixer_context { @@ -283,17 +284,19 @@ static void mixer_cfg_scan(struct mixer_context *ctx, unsigned int height) val = (ctx->interlace ? MXR_CFG_SCAN_INTERLACE : MXR_CFG_SCAN_PROGRASSIVE);
- /* choosing between porper HD and SD mode */
- if (height <= 480)
val |= MXR_CFG_SCAN_NTSC | MXR_CFG_SCAN_SD;- else if (height <= 576)
val |= MXR_CFG_SCAN_PAL | MXR_CFG_SCAN_SD;- else if (height <= 720)
val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD;- else if (height <= 1080)
val |= MXR_CFG_SCAN_HD_1080 | MXR_CFG_SCAN_HD;- else
val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD;
if (ctx->mxr_ver != MXR_VER_128_0_0_184) {
/* choosing between proper HD and SD mode */if (height <= 480)val |= MXR_CFG_SCAN_NTSC | MXR_CFG_SCAN_SD;else if (height <= 576)val |= MXR_CFG_SCAN_PAL | MXR_CFG_SCAN_SD;else if (height <= 720)val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD;else if (height <= 1080)val |= MXR_CFG_SCAN_HD_1080 | MXR_CFG_SCAN_HD;elseval |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD;}
mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_SCAN_MASK);
} @@ -557,6 +560,14 @@ static void mixer_graph_buffer(struct mixer_context *ctx, int win) /* setup geometry */ mixer_reg_write(res, MXR_GRAPHIC_SPAN(win), win_data->fb_width);
- /* setup display size */
- if (ctx->mxr_ver == MXR_VER_128_0_0_184 &&
win == MIXER_DEFAULT_WIN) {val = MXR_MXR_RES_HEIGHT(win_data->fb_height);val |= MXR_MXR_RES_WIDTH(win_data->fb_width);mixer_reg_write(res, MXR_RESOLUTION, val);- }
- val = MXR_GRP_WH_WIDTH(win_data->crtc_width); val |= MXR_GRP_WH_HEIGHT(win_data->crtc_height); val |= MXR_GRP_WH_H_SCALE(x_ratio);
@@ -581,7 +592,8 @@ static void mixer_graph_buffer(struct mixer_context *ctx, int win) mixer_cfg_layer(ctx, win, true);
/* layer update mandatory for mixer 16.0.33.0 */
- if (ctx->mxr_ver == MXR_VER_16_0_33_0)
if (ctx->mxr_ver == MXR_VER_16_0_33_0 ||
ctx->mxr_ver == MXR_VER_128_0_0_184)mixer_layer_update(ctx);
mixer_run(ctx);
@@ -822,6 +834,7 @@ static void mixer_win_disable(void *ctx, int win)
static int mixer_check_mode(void *ctx, struct drm_display_mode *mode) {
struct mixer_context *mixer_ctx = ctx; u32 w, h;
w = mode->hdisplay;
@@ -831,6 +844,10 @@ static int mixer_check_mode(void *ctx, struct drm_display_mode *mode) mode->hdisplay, mode->vdisplay, mode->vrefresh, (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0);
- if (mixer_ctx->mxr_ver == MXR_VER_0_0_0_16 ||
mixer_ctx->mxr_ver == MXR_VER_128_0_0_184)return 0;- if ((w >= 464 && w <= 720 && h >= 261 && h <= 576) || (w >= 1024 && w <= 1280 && h >= 576 && h <= 720) || (w >= 1664 && w <= 1920 && h >= 936 && h <= 1080))
@@ -1127,6 +1144,11 @@ static int vp_resources_init(struct exynos_drm_hdmi_context *ctx, return 0; }
+static struct mixer_drv_data exynos5420_mxr_drv_data = {
- .version = MXR_VER_128_0_0_184,
- .is_vp_enabled = 0,
+};
static struct mixer_drv_data exynos5250_mxr_drv_data = { .version = MXR_VER_16_0_33_0, .is_vp_enabled = 0, @@ -1151,6 +1173,9 @@ static struct platform_device_id mixer_driver_types[] = {
static struct of_device_id mixer_match_types[] = { {
.compatible = "samsung,exynos5420-mixer",.data = &exynos5420_mxr_drv_data,- }, { .compatible = "samsung,exynos5250-mixer", .data = &exynos5250_mxr_drv_data, }, {
diff --git a/drivers/gpu/drm/exynos/regs-mixer.h b/drivers/gpu/drm/exynos/regs-mixer.h index 5d8dbc0..4537026 100644 --- a/drivers/gpu/drm/exynos/regs-mixer.h +++ b/drivers/gpu/drm/exynos/regs-mixer.h @@ -44,6 +44,9 @@ #define MXR_CM_COEFF_Y 0x0080 #define MXR_CM_COEFF_CB 0x0084 #define MXR_CM_COEFF_CR 0x0088 +#define MXR_MO 0x0304 +#define MXR_RESOLUTION 0x0310
#define MXR_GRAPHIC0_BASE_S 0x2024 #define MXR_GRAPHIC1_BASE_S 0x2044
@@ -119,6 +122,10 @@ #define MXR_GRP_WH_WIDTH(x) MXR_MASK_VAL(x, 26, 16) #define MXR_GRP_WH_HEIGHT(x) MXR_MASK_VAL(x, 10, 0)
+/* bits for MXR_RESOLUTION */ +#define MXR_MXR_RES_HEIGHT(x) MXR_MASK_VAL(x, 26, 16) +#define MXR_MXR_RES_WIDTH(x) MXR_MASK_VAL(x, 10, 0)
/* bits for MXR_GRAPHICn_SXY */ #define MXR_GRP_SXY_SX(x) MXR_MASK_VAL(x, 26, 16) #define MXR_GRP_SXY_SY(x) MXR_MASK_VAL(x, 10, 0)
Modified code for calculating hdmi IP register values from drm timing values. The modification is based on the inputs from hw team and specifically proposed for 1440x576i and 1440x480i. But same changes holds good for other interlaced resolutions also.
Signed-off-by: Rahul Sharma rahul.sharma@samsung.com --- drivers/gpu/drm/exynos/exynos_hdmi.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c index 423bdc6..1eb5ffb 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c @@ -1767,8 +1767,7 @@ static void hdmi_4212_mode_set(struct hdmi_context *hdata, (m->vsync_start - m->vdisplay) / 2); hdmi_set_reg(core->v2_blank, 2, m->vtotal / 2); hdmi_set_reg(core->v1_blank, 2, (m->vtotal - m->vdisplay) / 2); - hdmi_set_reg(core->v_blank_f0, 2, (m->vtotal + - ((m->vsync_end - m->vsync_start) * 4) + 5) / 2); + hdmi_set_reg(core->v_blank_f0, 2, m->vtotal - m->vdisplay / 2); hdmi_set_reg(core->v_blank_f1, 2, m->vtotal); hdmi_set_reg(core->v_sync_line_aft_2, 2, (m->vtotal / 2) + 7); hdmi_set_reg(core->v_sync_line_aft_1, 2, (m->vtotal / 2) + 2); @@ -1778,7 +1777,10 @@ static void hdmi_4212_mode_set(struct hdmi_context *hdata, (m->htotal / 2) + (m->hsync_start - m->hdisplay)); hdmi_set_reg(tg->vact_st, 2, (m->vtotal - m->vdisplay) / 2); hdmi_set_reg(tg->vact_sz, 2, m->vdisplay / 2); - hdmi_set_reg(tg->vact_st2, 2, 0x249);/* Reset value + 1*/ + hdmi_set_reg(tg->vact_st2, 2, m->vtotal - m->vdisplay / 2); + hdmi_set_reg(tg->vsync2, 2, (m->vtotal / 2) + 1); + hdmi_set_reg(tg->vsync_bot_hdmi, 2, (m->vtotal / 2) + 1); + hdmi_set_reg(tg->field_bot_hdmi, 2, (m->vtotal / 2) + 1); hdmi_set_reg(tg->vact_st3, 2, 0x0); hdmi_set_reg(tg->vact_st4, 2, 0x0); } else { @@ -1800,6 +1802,9 @@ static void hdmi_4212_mode_set(struct hdmi_context *hdata, hdmi_set_reg(tg->vact_st2, 2, 0x248); /* Reset value */ hdmi_set_reg(tg->vact_st3, 2, 0x47b); /* Reset value */ hdmi_set_reg(tg->vact_st4, 2, 0x6ae); /* Reset value */ + hdmi_set_reg(tg->vsync2, 2, 0x233); /* Reset value */ + hdmi_set_reg(tg->vsync_bot_hdmi, 2, 0x233); /* Reset value */ + hdmi_set_reg(tg->field_bot_hdmi, 2, 0x233); /* Reset value */ }
/* Following values & calculations are same irrespective of mode type */ @@ -1831,12 +1836,9 @@ static void hdmi_4212_mode_set(struct hdmi_context *hdata, hdmi_set_reg(tg->hact_sz, 2, m->hdisplay); hdmi_set_reg(tg->v_fsz, 2, m->vtotal); hdmi_set_reg(tg->vsync, 2, 0x1); - hdmi_set_reg(tg->vsync2, 2, 0x233); /* Reset value */ hdmi_set_reg(tg->field_chg, 2, 0x233); /* Reset value */ hdmi_set_reg(tg->vsync_top_hdmi, 2, 0x1); /* Reset value */ - hdmi_set_reg(tg->vsync_bot_hdmi, 2, 0x233); /* Reset value */ hdmi_set_reg(tg->field_top_hdmi, 2, 0x1); /* Reset value */ - hdmi_set_reg(tg->field_bot_hdmi, 2, 0x233); /* Reset value */ hdmi_set_reg(tg->tg_3d, 1, 0x0); }
Cleanup by removing flags variable from drm_hdmi_dt_parse_pdata which is not used anywhere. Swtiching to of_get_named_gpio instead of of_get_named_gpio_flags solved this.
Signed-off-by: Rahul Sharma rahul.sharma@samsung.com --- drivers/gpu/drm/exynos/exynos_hdmi.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c index 1eb5ffb..fc6a9b0 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c @@ -2081,7 +2081,6 @@ static struct s5p_hdmi_platform_data *drm_hdmi_dt_parse_pdata { struct device_node *np = dev->of_node; struct s5p_hdmi_platform_data *pd; - enum of_gpio_flags flags; u32 value;
pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); @@ -2095,7 +2094,7 @@ static struct s5p_hdmi_platform_data *drm_hdmi_dt_parse_pdata goto err_data; }
- pd->hpd_gpio = of_get_named_gpio_flags(np, "hpd-gpio", 0, &flags); + pd->hpd_gpio = of_get_named_gpio(np, "hpd-gpio", 0);
return pd;
Hello Rahul,
this patch is not related with others and it looks good to me.
On 2013년 06월 11일 23:11, Rahul Sharma wrote:
Cleanup by removing flags variable from drm_hdmi_dt_parse_pdata which is not used anywhere. Swtiching to of_get_named_gpio instead of of_get_named_gpio_flags solved this.
Signed-off-by: Rahul Sharma rahul.sharma@samsung.com
Acked-by: Seung-Woo Kim sw0312.kim@samsung.com
drivers/gpu/drm/exynos/exynos_hdmi.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c index 1eb5ffb..fc6a9b0 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c @@ -2081,7 +2081,6 @@ static struct s5p_hdmi_platform_data *drm_hdmi_dt_parse_pdata { struct device_node *np = dev->of_node; struct s5p_hdmi_platform_data *pd;
enum of_gpio_flags flags; u32 value;
pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
@@ -2095,7 +2094,7 @@ static struct s5p_hdmi_platform_data *drm_hdmi_dt_parse_pdata goto err_data; }
- pd->hpd_gpio = of_get_named_gpio_flags(np, "hpd-gpio", 0, &flags);
pd->hpd_gpio = of_get_named_gpio(np, "hpd-gpio", 0);
return pd;
Applied.
Thanks, Inki Dae
2013/6/14 김승우 sw0312.kim@samsung.com
Hello Rahul,
this patch is not related with others and it looks good to me.
On 2013년 06월 11일 23:11, Rahul Sharma wrote:
Cleanup by removing flags variable from drm_hdmi_dt_parse_pdata which is not used anywhere. Swtiching to of_get_named_gpio instead of of_get_named_gpio_flags solved this.
Signed-off-by: Rahul Sharma rahul.sharma@samsung.com
Acked-by: Seung-Woo Kim sw0312.kim@samsung.com
drivers/gpu/drm/exynos/exynos_hdmi.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 1eb5ffb..fc6a9b0 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c @@ -2081,7 +2081,6 @@ static struct s5p_hdmi_platform_data
*drm_hdmi_dt_parse_pdata
{ struct device_node *np = dev->of_node; struct s5p_hdmi_platform_data *pd;
enum of_gpio_flags flags; u32 value; pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);@@ -2095,7 +2094,7 @@ static struct s5p_hdmi_platform_data
*drm_hdmi_dt_parse_pdata
goto err_data; }
pd->hpd_gpio = of_get_named_gpio_flags(np, "hpd-gpio", 0, &flags);
pd->hpd_gpio = of_get_named_gpio(np, "hpd-gpio", 0); return pd;-- Seung-Woo Kim Samsung Software R&D Center --
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Thanks Mr. Dae,
Please discard the REST of the patches in this series. I am posting a another patch-set which has all the patches independent of hdmiphy related changes.
regards, Rahul Sharma.
On Mon, Jun 17, 2013 at 8:22 AM, Inki Dae inki.dae@samsung.com wrote:
Applied.
Thanks, Inki Dae
2013/6/14 김승우 sw0312.kim@samsung.com
Hello Rahul,
this patch is not related with others and it looks good to me.
On 2013년 06월 11일 23:11, Rahul Sharma wrote:
Cleanup by removing flags variable from drm_hdmi_dt_parse_pdata which is not used anywhere. Swtiching to of_get_named_gpio instead of of_get_named_gpio_flags solved this.
Signed-off-by: Rahul Sharma rahul.sharma@samsung.com
Acked-by: Seung-Woo Kim sw0312.kim@samsung.com
drivers/gpu/drm/exynos/exynos_hdmi.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c index 1eb5ffb..fc6a9b0 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c @@ -2081,7 +2081,6 @@ static struct s5p_hdmi_platform_data *drm_hdmi_dt_parse_pdata { struct device_node *np = dev->of_node; struct s5p_hdmi_platform_data *pd;
enum of_gpio_flags flags; u32 value; pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);@@ -2095,7 +2094,7 @@ static struct s5p_hdmi_platform_data *drm_hdmi_dt_parse_pdata goto err_data; }
pd->hpd_gpio = of_get_named_gpio_flags(np, "hpd-gpio", 0, &flags);
pd->hpd_gpio = of_get_named_gpio(np, "hpd-gpio", 0); return pd;-- Seung-Woo Kim Samsung Software R&D Center --
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dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
Add property to hdmi node to get phandle for hdmiphy node. This is required to check the compatible type of phy in hdmi driver. If phy is compatible to exynos5420, it needs to be treated as a platform device rather than a i2c device.
Signed-off-by: Rahul Sharma rahul.sharma@samsung.com --- arch/arm/boot/dts/exynos5250-smdk5250.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 0ec6856..239341d 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -101,7 +101,7 @@ samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>;
- hdmiphy@38 { + hdmiphy: hdmiphy@38 { compatible = "samsung,exynos4210-hdmiphy"; reg = <0x38>; }; @@ -187,6 +187,7 @@
hdmi { hpd-gpio = <&gpx3 7 0>; + phy = <&hdmiphy>; };
codec@11000000 {
Update device tree binding documentation for hdmi subsystem with the clock information, phy property information and compatible strings for exynos5420.
Signed-off-by: Rahul Sharma rahul.sharma@samsung.com --- .../devicetree/bindings/video/exynos_hdmi.txt | 19 +++++++++++++++++++ .../devicetree/bindings/video/exynos_hdmiphy.txt | 10 ++++++++-- .../devicetree/bindings/video/exynos_mixer.txt | 7 +++++++ 3 files changed, 34 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt b/Documentation/devicetree/bindings/video/exynos_hdmi.txt index 2ac01ca..e3c5853 100644 --- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt +++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt @@ -4,6 +4,7 @@ Required properties: - compatible: value should be one among the following: 1) "samsung,exynos4210-hdmi" 2) "samsung,exynos4212-hdmi" + 3) "samsung,exynos5420-hdmi" - reg: physical base address of the hdmi and length of memory mapped region. - interrupts: interrupt number to the cpu. @@ -13,6 +14,20 @@ Required properties: c) pin function mode. d) optional flags and pull up/down. e) drive strength. +- clocks: list of clock IDs from SoC clock driver. + a) hdmi: It is required for gate operation on aclk_200_disp1 clock + which clocks the display1 block. + b) sclk_hdmi: It is required for gate operation on sclk_hdmi clock + which clocks hdmi IP. + c) sclk_pixel: Parent for mux mout_hdmi. + d) sclk_hdmiphy: Parent for mux mout_hdmi. + e) mout_hdmi: It is required by the driver to switch between the 2 + parents i.e. sclk_pixel and sclk_hdmiphy. If hdmiphy is stable + after configuration, parent is set to sclk_hdmiphy else + sclk_pixel. +- clock-names: aliases as per driver requirements for above clock IDs: + "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy" and "mout_hdmi". +- phy: this property holds the phandle for hdmiphy node.
Example:
@@ -21,4 +36,8 @@ Example: reg = <0x14530000 0x100000>; interrupts = <0 95 0>; hpd-gpio = <&gpx3 7 0xf 1 3>; + clocks = <&clock 344>, <&clock 136>, <&clock 137>, + <&clock 157>, <&clock 1024>; + clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", + "sclk_hdmiphy", "mout_hdmi"; }; diff --git a/Documentation/devicetree/bindings/video/exynos_hdmiphy.txt b/Documentation/devicetree/bindings/video/exynos_hdmiphy.txt index fb688a6..e2b12ed 100644 --- a/Documentation/devicetree/bindings/video/exynos_hdmiphy.txt +++ b/Documentation/devicetree/bindings/video/exynos_hdmiphy.txt @@ -1,8 +1,14 @@ Device-Tree bindings for hdmiphy driver
Required properties: -- compatible: value should be "samsung,exynos4210-hdmiphy". -- reg: I2C address of the hdmiphy device. +- compatible: value should be one among the following + 1) Samsung,exynos4210-hdmiphy". + 2) Samsung,exynos5420-hdmiphy". + +- reg: it holds the physical address infomration for the hdmiphy device. + If it is a i2c device, reg holds the I2C address of the phy. For + platform bus mapped phy, reg property holds physical address as + well as size of the register region.
Example:
diff --git a/Documentation/devicetree/bindings/video/exynos_mixer.txt b/Documentation/devicetree/bindings/video/exynos_mixer.txt index a8b063f..38e4e5c 100644 --- a/Documentation/devicetree/bindings/video/exynos_mixer.txt +++ b/Documentation/devicetree/bindings/video/exynos_mixer.txt @@ -4,10 +4,15 @@ Required properties: - compatible: value should be: 1) "samsung,exynos4210-mixer" 2) "samsung,exynos5250-mixer" + 3) "samsung,exynos5420-mixer"
- reg: physical base address of the mixer and length of memory mapped region. - interrupts: interrupt number to the cpu. +- clocks: list of clock IDs from SoC clock driver. + a) mixer: It is required for gate operation on aclk_200_disp1 clock + which clocks the display1 block. + b) sclk_hdmi: Parent for mux mout_mixer.
Example:
@@ -15,4 +20,6 @@ Example: compatible = "samsung,exynos5250-mixer"; reg = <0x14450000 0x10000>; interrupts = <0 94 0>; + clocks = <&clock 343>, <&clock 136>; + clock-names = "mixer", "sclk_hdmi"; };
On Tue, 11 Jun 2013 19:41:31 +0530, Rahul Sharma rahul.sharma@samsung.com wrote:
Update device tree binding documentation for hdmi subsystem with the clock information, phy property information and compatible strings for exynos5420.
Signed-off-by: Rahul Sharma rahul.sharma@samsung.com
Binding looks reasonable to me. I'll leave it to the video maintainers to say whether or not it is covers the right amount of configuration data.
g.
.../devicetree/bindings/video/exynos_hdmi.txt | 19 +++++++++++++++++++ .../devicetree/bindings/video/exynos_hdmiphy.txt | 10 ++++++++-- .../devicetree/bindings/video/exynos_mixer.txt | 7 +++++++ 3 files changed, 34 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt b/Documentation/devicetree/bindings/video/exynos_hdmi.txt index 2ac01ca..e3c5853 100644 --- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt +++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt @@ -4,6 +4,7 @@ Required properties:
- compatible: value should be one among the following:
- "samsung,exynos4210-hdmi"
- "samsung,exynos4212-hdmi"
- "samsung,exynos5420-hdmi"
- reg: physical base address of the hdmi and length of memory mapped region.
- interrupts: interrupt number to the cpu.
@@ -13,6 +14,20 @@ Required properties: c) pin function mode. d) optional flags and pull up/down. e) drive strength. +- clocks: list of clock IDs from SoC clock driver.
- a) hdmi: It is required for gate operation on aclk_200_disp1 clock
which clocks the display1 block.- b) sclk_hdmi: It is required for gate operation on sclk_hdmi clock
which clocks hdmi IP.- c) sclk_pixel: Parent for mux mout_hdmi.
- d) sclk_hdmiphy: Parent for mux mout_hdmi.
- e) mout_hdmi: It is required by the driver to switch between the 2
parents i.e. sclk_pixel and sclk_hdmiphy. If hdmiphy is stableafter configuration, parent is set to sclk_hdmiphy elsesclk_pixel.+- clock-names: aliases as per driver requirements for above clock IDs:
- "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy" and "mout_hdmi".
+- phy: this property holds the phandle for hdmiphy node.
Example:
@@ -21,4 +36,8 @@ Example: reg = <0x14530000 0x100000>; interrupts = <0 95 0>; hpd-gpio = <&gpx3 7 0xf 1 3>;
clocks = <&clock 344>, <&clock 136>, <&clock 137>,<&clock 157>, <&clock 1024>;clock-names = "hdmi", "sclk_hdmi", "sclk_pixel","sclk_hdmiphy", "mout_hdmi";diff --git a/Documentation/devicetree/bindings/video/exynos_hdmiphy.txt b/Documentation/devicetree/bindings/video/exynos_hdmiphy.txt index fb688a6..e2b12ed 100644 --- a/Documentation/devicetree/bindings/video/exynos_hdmiphy.txt +++ b/Documentation/devicetree/bindings/video/exynos_hdmiphy.txt @@ -1,8 +1,14 @@ Device-Tree bindings for hdmiphy driver
Required properties: -- compatible: value should be "samsung,exynos4210-hdmiphy". -- reg: I2C address of the hdmiphy device. +- compatible: value should be one among the following
- Samsung,exynos4210-hdmiphy".
- Samsung,exynos5420-hdmiphy".
+- reg: it holds the physical address infomration for the hdmiphy device.
- If it is a i2c device, reg holds the I2C address of the phy. For
- platform bus mapped phy, reg property holds physical address as
- well as size of the register region.
Example:
diff --git a/Documentation/devicetree/bindings/video/exynos_mixer.txt b/Documentation/devicetree/bindings/video/exynos_mixer.txt index a8b063f..38e4e5c 100644 --- a/Documentation/devicetree/bindings/video/exynos_mixer.txt +++ b/Documentation/devicetree/bindings/video/exynos_mixer.txt @@ -4,10 +4,15 @@ Required properties:
- compatible: value should be:
- "samsung,exynos4210-mixer"
- "samsung,exynos5250-mixer"
- "samsung,exynos5420-mixer"
- reg: physical base address of the mixer and length of memory mapped region.
- interrupts: interrupt number to the cpu.
+- clocks: list of clock IDs from SoC clock driver.
- a) mixer: It is required for gate operation on aclk_200_disp1 clock
which clocks the display1 block.- b) sclk_hdmi: Parent for mux mout_mixer.
Example:
@@ -15,4 +20,6 @@ Example: compatible = "samsung,exynos5250-mixer"; reg = <0x14450000 0x10000>; interrupts = <0 94 0>;
clocks = <&clock 343>, <&clock 136>;clock-names = "mixer", "sclk_hdmi";-- 1.7.10.4
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