Hello Rob,

Thanks for your review. I add comments below:

On Thu, 2022-02-24 at 13:19 -0600, Rob Herring wrote:

On Tue, Feb 22, 2022 at 01:28:00PM +0800, Rex-BC Chen wrote:

...

Add MT8186 SoC binding to AAL, CCORR, COLOR, DITHER, GAMMA, MUTEX, OVL, POSTMASK and RDMA.

Signed-off-by: Rex-BC Chen rex-bc.chen@mediatek.com

.../devicetree/bindings/display/mediatek/mediatek,aal.yaml | 7 +++++++ .../bindings/display/mediatek/mediatek,ccorr.yaml | 5 +++++ .../bindings/display/mediatek/mediatek,color.yaml | 1 + .../bindings/display/mediatek/mediatek,dither.yaml | 1 + .../bindings/display/mediatek/mediatek,gamma.yaml | 1 + .../bindings/display/mediatek/mediatek,mutex.yaml | 2 ++ .../bindings/display/mediatek/mediatek,ovl-2l.yaml | 5 +++++ .../devicetree/bindings/display/mediatek/mediatek,ovl.yaml | 5 +++++ .../bindings/display/mediatek/mediatek,postmask.yaml | 5 +++++ .../bindings/display/mediatek/mediatek,rdma.yaml | 1 + 10 files changed, 33 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.y aml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.y aml index 225f9dd726d2..3a5416937293 100644

---

a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.y aml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.y aml @@ -23,6 +23,8 @@ properties: oneOf: - items: - const: mediatek,mt8173-disp-aal

•  - items:
  

•      - const: mediatek,mt8183-disp-aal
  

This patch is for 8186...

I will split it to another commit in next version.

...

   - items:
       - enum:
           - mediatek,mt2712-disp-aal

@@ -31,6 +33,11 @@ properties: - mediatek,mt8195-disp-aal - enum: - mediatek,mt8173-disp-aal

•  - items:
  

•      - enum:
  

•          - mediatek,mt8186-disp-aal
  

•      - enum:
  

•          - mediatek,mt8183-disp-aal
  

There won't be more than 1 fallback, so use const rather than enum.

I will modify it in next version.

...

reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr .yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr .yaml index 6894b6999412..8ac87b5896ac 100644

---

a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr .yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr .yaml @@ -30,6 +30,11 @@ properties: - mediatek,mt8195-disp-ccorr - enum: - mediatek,mt8192-disp-ccorr

•  - items:
  

•      - enum:
  

•          - mediatek,mt8186-disp-ccorr
  

•      - enum:
  

•          - mediatek,mt8183-disp-ccorr
  

Same here.

I will modify it in next version.

...

reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color .yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color .yaml index bc83155b3b4c..d0a4b9eb71fd 100644

---

a/Documentation/devicetree/bindings/display/mediatek/mediatek,color .yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color .yaml @@ -37,6 +37,7 @@ properties: - items: - enum: - mediatek,mt8183-disp-color

•          - mediatek,mt8186-disp-color
           - mediatek,mt8192-disp-color
           - mediatek,mt8195-disp-color
       - enum:
  

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dithe r.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dithe r.yaml index 9d89297f5f1d..9a08514ed909 100644

---

a/Documentation/devicetree/bindings/display/mediatek/mediatek,dithe r.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dithe r.yaml @@ -26,6 +26,7 @@ properties: - const: mediatek,mt8183-disp-dither - items: - enum:

•          - mediatek,mt8186-disp-dither
           - mediatek,mt8192-disp-dither
           - mediatek,mt8195-disp-dither
       - enum:
  

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma .yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma .yaml index 247baad147b3..6d96f6736d91 100644

---

a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma .yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma .yaml @@ -27,6 +27,7 @@ properties: - const: mediatek,mt8183-disp-gamma - items: - enum:

•          - mediatek,mt8186-disp-gamma
           - mediatek,mt8192-disp-gamma
           - mediatek,mt8195-disp-gamma
       - enum:
  

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex .yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex .yaml index 6eca525eced0..55391b5c08c4 100644

---

a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex .yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex .yaml @@ -34,6 +34,8 @@ properties: - const: mediatek,mt8173-disp-mutex - items: - const: mediatek,mt8183-disp-mutex

•  - items:
  

•      - const: mediatek,mt8186-disp-mutex
   - items:
       - const: mediatek,mt8192-disp-mutex
  

All these single entry cases can be a single enum.

I will modify it in next version.

...

   - items:

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl- 2l.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl- 2l.yaml index 611a2dbdefa4..f7f89485a5ae 100644

---

a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl- 2l.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl- 2l.yaml @@ -25,6 +25,11 @@ properties: - const: mediatek,mt8183-disp-ovl-2l - items: - const: mediatek,mt8192-disp-ovl-2l

•  - items:
  

•      - enum:
  

•          - mediatek,mt8186-disp-ovl-2l
  

•      - enum:
  

•          - mediatek,mt8192-disp-ovl-2l
  
  

  reg: maxItems: 1

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.y aml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.y aml index e71f79bc2dee..110e6b2747bc 100644

---

a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.y aml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.y aml @@ -40,6 +40,11 @@ properties: - mediatek,mt8195-disp-ovl - enum: - mediatek,mt8183-disp-ovl

•  - items:
  

•      - enum:
  

•          - mediatek,mt8186-disp-ovl
  

•      - enum:
  

•          - mediatek,mt8192-disp-ovl
  
  

  reg: maxItems: 1

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,postm ask.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,postm ask.yaml index 6ac1da2e8871..22c333d09465 100644

---

a/Documentation/devicetree/bindings/display/mediatek/mediatek,postm ask.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,postm ask.yaml @@ -23,6 +23,11 @@ properties: oneOf: - items: - const: mediatek,mt8192-disp-postmask

•  - items:
  

•      - enum:
  

•          - mediatek,mt8186-disp-postmask
  

•      - enum:
  

•          - mediatek,mt8192-disp-postmask
  
  

  reg: maxItems: 1

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma. yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma. yaml index 8ef821641672..4f1c935cdf70 100644

---

a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma. yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma. yaml @@ -39,6 +39,7 @@ properties: - mediatek,mt2701-disp-rdma - items: - enum:

•          - mediatek,mt8186-disp-rdma
           - mediatek,mt8192-disp-rdma
       - enum:
           - mediatek,mt8183-disp-rdma
  

-- 2.18.0

BRs, Rex

On 22/02/2022 06:28, Rex-BC Chen wrote:

From: Yongqiang Niu yongqiang.niu@mediatek.com

Add new routing table for MT8186. In MT8186, there are two routing pipelines for internal and external display.

Internal display: OVL0->RDMA0->COLOR0->CCORR0->AAL0->GAMMA->POSTMASK0-> DITHER->DSI0 External display: OVL_2L0->RDMA1->DPI0

Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Rex-BC Chen rex-bc.chen@mediatek.com

applied, thanks!

---

drivers/soc/mediatek/mt8186-mmsys.h | 113 ++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 11 +++ 2 files changed, 124 insertions(+) create mode 100644 drivers/soc/mediatek/mt8186-mmsys.h

diff --git a/drivers/soc/mediatek/mt8186-mmsys.h b/drivers/soc/mediatek/mt8186-mmsys.h new file mode 100644 index 000000000000..7de329f2d729 --- /dev/null +++ b/drivers/soc/mediatek/mt8186-mmsys.h @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: GPL-2.0-only */

+#ifndef __SOC_MEDIATEK_MT8186_MMSYS_H +#define __SOC_MEDIATEK_MT8186_MMSYS_H

+#define MT8186_MMSYS_OVL_CON 0xF04 +#define MT8186_MMSYS_OVL0_CON_MASK 0x3 +#define MT8186_MMSYS_OVL0_2L_CON_MASK 0xC +#define MT8186_OVL0_GO_BLEND BIT(0) +#define MT8186_OVL0_GO_BG BIT(1) +#define MT8186_OVL0_2L_GO_BLEND BIT(2) +#define MT8186_OVL0_2L_GO_BG BIT(3) +#define MT8186_DISP_RDMA0_SOUT_SEL 0xF0C +#define MT8186_RDMA0_SOUT_SEL_MASK 0xF +#define MT8186_RDMA0_SOUT_TO_DSI0 (0) +#define MT8186_RDMA0_SOUT_TO_COLOR0 (1) +#define MT8186_RDMA0_SOUT_TO_DPI0 (2) +#define MT8186_DISP_OVL0_2L_MOUT_EN 0xF14 +#define MT8186_OVL0_2L_MOUT_EN_MASK 0xF +#define MT8186_OVL0_2L_MOUT_TO_RDMA0 BIT(0) +#define MT8186_OVL0_2L_MOUT_TO_RDMA1 BIT(3) +#define MT8186_DISP_OVL0_MOUT_EN 0xF18 +#define MT8186_OVL0_MOUT_EN_MASK 0xF +#define MT8186_OVL0_MOUT_TO_RDMA0 BIT(0) +#define MT8186_OVL0_MOUT_TO_RDMA1 BIT(3) +#define MT8186_DISP_DITHER0_MOUT_EN 0xF20 +#define MT8186_DITHER0_MOUT_EN_MASK 0xF +#define MT8186_DITHER0_MOUT_TO_DSI0 BIT(0) +#define MT8186_DITHER0_MOUT_TO_RDMA1 BIT(2) +#define MT8186_DITHER0_MOUT_TO_DPI0 BIT(3) +#define MT8186_DISP_RDMA0_SEL_IN 0xF28 +#define MT8186_RDMA0_SEL_IN_MASK 0xF +#define MT8186_RDMA0_FROM_OVL0 0 +#define MT8186_RDMA0_FROM_OVL0_2L 2 +#define MT8186_DISP_DSI0_SEL_IN 0xF30 +#define MT8186_DSI0_SEL_IN_MASK 0xF +#define MT8186_DSI0_FROM_RDMA0 0 +#define MT8186_DSI0_FROM_DITHER0 1 +#define MT8186_DSI0_FROM_RDMA1 2 +#define MT8186_DISP_RDMA1_MOUT_EN 0xF3C +#define MT8186_RDMA1_MOUT_EN_MASK 0xF +#define MT8186_RDMA1_MOUT_TO_DPI0_SEL BIT(0) +#define MT8186_RDMA1_MOUT_TO_DSI0_SEL BIT(2) +#define MT8186_DISP_RDMA1_SEL_IN 0xF40 +#define MT8186_RDMA1_SEL_IN_MASK 0xF +#define MT8186_RDMA1_FROM_OVL0 0 +#define MT8186_RDMA1_FROM_OVL0_2L 2 +#define MT8186_RDMA1_FROM_DITHER0 3 +#define MT8186_DISP_DPI0_SEL_IN 0xF44 +#define MT8186_DPI0_SEL_IN_MASK 0xF +#define MT8186_DPI0_FROM_RDMA1 0 +#define MT8186_DPI0_FROM_DITHER0 1 +#define MT8186_DPI0_FROM_RDMA0 2

+static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = {

• {

• DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
  

• MT8186_DISP_OVL0_MOUT_EN, MT8186_OVL0_MOUT_EN_MASK,
  

• MT8186_OVL0_MOUT_TO_RDMA0
  

• },
• {

• DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
  

• MT8186_DISP_RDMA0_SEL_IN, MT8186_RDMA0_SEL_IN_MASK,
  

• MT8186_RDMA0_FROM_OVL0
  

• },
• {

• DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
  

• MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_CON_MASK,
  

• MT8186_OVL0_GO_BLEND
  

• },
• {

• DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
  

• MT8186_DISP_RDMA0_SOUT_SEL, MT8186_RDMA0_SOUT_SEL_MASK,
  

• MT8186_RDMA0_SOUT_TO_COLOR0
  

• },
• {

• DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
  

• MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK,
  

• MT8186_DITHER0_MOUT_TO_DSI0,
  

• },
• {

• DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
  

• MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK,
  

• MT8186_DSI0_FROM_DITHER0
  

• },
• {

• DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,
  

• MT8186_DISP_OVL0_2L_MOUT_EN, MT8186_OVL0_2L_MOUT_EN_MASK,
  

• MT8186_OVL0_2L_MOUT_TO_RDMA1
  

• },
• {

• DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,
  

• MT8186_DISP_RDMA1_SEL_IN, MT8186_RDMA1_SEL_IN_MASK,
  

• MT8186_RDMA1_FROM_OVL0_2L
  

• },
• {

• DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,
  

• MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_2L_CON_MASK,
  

• MT8186_OVL0_2L_GO_BLEND
  

• },
• {

• DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
  

• MT8186_DISP_RDMA1_MOUT_EN, MT8186_RDMA1_MOUT_EN_MASK,
  

• MT8186_RDMA1_MOUT_TO_DPI0_SEL
  

• },
• {

• DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
  

• MT8186_DISP_DPI0_SEL_IN, MT8186_DPI0_SEL_IN_MASK,
  

• MT8186_DPI0_FROM_RDMA1
  

• },

+};

+#endif /* __SOC_MEDIATEK_MT8186_MMSYS_H */ diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 1e448f1ffefb..0da25069ffb3 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -15,6 +15,7 @@ #include "mtk-mmsys.h" #include "mt8167-mmsys.h" #include "mt8183-mmsys.h" +#include "mt8186-mmsys.h" #include "mt8192-mmsys.h" #include "mt8365-mmsys.h"

@@ -56,6 +57,12 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table), };

+static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {

• .clk_driver = "clk-mt8186-mm",
• .routes = mmsys_mt8186_routing_table,
• .num_routes = ARRAY_SIZE(mmsys_mt8186_routing_table),

+};

• static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { .clk_driver = "clk-mt8192-mm", .routes = mmsys_mt8192_routing_table,

@@ -242,6 +249,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = { .compatible = "mediatek,mt8183-mmsys", .data = &mt8183_mmsys_driver_data, },

• {

• .compatible = "mediatek,mt8186-mmsys",
  

• .data = &mt8186_mmsys_driver_data,
  

• }, { .compatible = "mediatek,mt8192-mmsys", .data = &mt8192_mmsys_driver_data,

On 22/02/2022 06:28, Rex-BC Chen wrote:

From: Yongqiang Niu yongqiang.niu@mediatek.com

Add MTK mutex support for MT8186 SoC. We need MTK mutex to control timing of display modules and there are two display pipelines for MT8186 including internal and external display.

MTK mutex for internal display:

• Timing source: DSI
• Control modules: OVL0/RDMA0/COLOR0/CCORR/AAL0/GAMMA/POSTMASK0/DITHER

MTK mutex for external display:

• Timing source : DPI
• Control modules: OVL_2L0/RDMA1

Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com Signed-off-by: Rex-BC Chen rex-bc.chen@mediatek.com

applied thanks

---

drivers/soc/mediatek/mtk-mutex.c | 45 ++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+)

diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index 2ca55bb5a8be..aaf8fc1abb43 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -26,6 +26,23 @@

#define INT_MUTEX BIT(1)

+#define MT8186_MUTEX_MOD_DISP_OVL0 0 +#define MT8186_MUTEX_MOD_DISP_OVL0_2L 1 +#define MT8186_MUTEX_MOD_DISP_RDMA0 2 +#define MT8186_MUTEX_MOD_DISP_COLOR0 4 +#define MT8186_MUTEX_MOD_DISP_CCORR0 5 +#define MT8186_MUTEX_MOD_DISP_AAL0 7 +#define MT8186_MUTEX_MOD_DISP_GAMMA0 8 +#define MT8186_MUTEX_MOD_DISP_POSTMASK0 9 +#define MT8186_MUTEX_MOD_DISP_DITHER0 10 +#define MT8186_MUTEX_MOD_DISP_RDMA1 17

+#define MT8186_MUTEX_SOF_SINGLE_MODE 0 +#define MT8186_MUTEX_SOF_DSI0 1 +#define MT8186_MUTEX_SOF_DPI0 2 +#define MT8186_MUTEX_EOF_DSI0 (MT8186_MUTEX_SOF_DSI0 << 6) +#define MT8186_MUTEX_EOF_DPI0 (MT8186_MUTEX_SOF_DPI0 << 6)

• #define MT8167_MUTEX_MOD_DISP_PWM 1 #define MT8167_MUTEX_MOD_DISP_OVL0 6 #define MT8167_MUTEX_MOD_DISP_OVL1 7

@@ -226,6 +243,19 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, };

+static const unsigned int mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = {

• [DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0,
• [DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0,
• [DDP_COMPONENT_COLOR0] = MT8186_MUTEX_MOD_DISP_COLOR0,
• [DDP_COMPONENT_DITHER] = MT8186_MUTEX_MOD_DISP_DITHER0,
• [DDP_COMPONENT_GAMMA] = MT8186_MUTEX_MOD_DISP_GAMMA0,
• [DDP_COMPONENT_OVL0] = MT8186_MUTEX_MOD_DISP_OVL0,
• [DDP_COMPONENT_OVL_2L0] = MT8186_MUTEX_MOD_DISP_OVL0_2L,
• [DDP_COMPONENT_POSTMASK0] = MT8186_MUTEX_MOD_DISP_POSTMASK0,
• [DDP_COMPONENT_RDMA0] = MT8186_MUTEX_MOD_DISP_RDMA0,
• [DDP_COMPONENT_RDMA1] = MT8186_MUTEX_MOD_DISP_RDMA1,

+};

• static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0, [DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,

@@ -264,6 +294,12 @@ static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = { [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, };

+static const unsigned int mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = {

• [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
• [MUTEX_SOF_DSI0] = MT8186_MUTEX_SOF_DSI0 | MT8186_MUTEX_EOF_DSI0,
• [MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 | MT8186_MUTEX_EOF_DPI0,

+};

• static const struct mtk_mutex_data mt2701_mutex_driver_data = { .mutex_mod = mt2701_mutex_mod, .mutex_sof = mt2712_mutex_sof,

@@ -301,6 +337,13 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = { .no_clk = true, };

+static const struct mtk_mutex_data mt8186_mutex_driver_data = {

• .mutex_mod = mt8186_mutex_mod,
• .mutex_sof = mt8186_mutex_sof,
• .mutex_mod_reg = MT8183_MUTEX0_MOD0,
• .mutex_sof_reg = MT8183_MUTEX0_SOF0,

+};

• static const struct mtk_mutex_data mt8192_mutex_driver_data = { .mutex_mod = mt8192_mutex_mod, .mutex_sof = mt8183_mutex_sof,

@@ -540,6 +583,8 @@ static const struct of_device_id mutex_driver_dt_match[] = { .data = &mt8173_mutex_driver_data}, { .compatible = "mediatek,mt8183-disp-mutex", .data = &mt8183_mutex_driver_data},

• { .compatible = "mediatek,mt8186-disp-mutex",

•  .data = &mt8186_mutex_driver_data},
  

  { .compatible = "mediatek,mt8192-disp-mutex", .data = &mt8192_mutex_driver_data}, {},